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CommitLineData
1da177e4
LT
1/*
2 * linux/arch/arm/vfp/vfpmodule.c
3 *
4 * Copyright (C) 2004 ARM Limited.
5 * Written by Deep Blue Solutions Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
1da177e4
LT
12#include <linux/types.h>
13#include <linux/kernel.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/init.h>
d6551e88
RK
17
18#include <asm/thread_notify.h>
1da177e4
LT
19#include <asm/vfp.h>
20
21#include "vfpinstr.h"
22#include "vfp.h"
23
24/*
25 * Our undef handlers (in entry.S)
26 */
27void vfp_testing_entry(void);
28void vfp_support_entry(void);
5d4cae5f 29void vfp_null_entry(void);
1da177e4 30
5d4cae5f 31void (*vfp_vector)(void) = vfp_null_entry;
c6428464 32union vfp_state *last_VFP_context[NR_CPUS];
1da177e4
LT
33
34/*
35 * Dual-use variable.
36 * Used in startup: set to non-zero if VFP checks fail
37 * After startup, holds VFP architecture
38 */
39unsigned int VFP_arch;
40
0d782dc4
RK
41/*
42 * Per-thread VFP initialization.
43 */
44static void vfp_thread_flush(struct thread_info *thread)
45{
46 union vfp_state *vfp = &thread->vfpstate;
47 unsigned int cpu;
48
49 memset(vfp, 0, sizeof(union vfp_state));
50
51 vfp->hard.fpexc = FPEXC_EN;
52 vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
53
54 /*
55 * Disable VFP to ensure we initialize it first. We must ensure
56 * that the modification of last_VFP_context[] and hardware disable
57 * are done for the same CPU and without preemption.
58 */
59 cpu = get_cpu();
60 if (last_VFP_context[cpu] == vfp)
61 last_VFP_context[cpu] = NULL;
62 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
63 put_cpu();
64}
65
797245f5 66static void vfp_thread_exit(struct thread_info *thread)
0d782dc4
RK
67{
68 /* release case: Per-thread VFP cleanup. */
69 union vfp_state *vfp = &thread->vfpstate;
797245f5 70 unsigned int cpu = get_cpu();
0d782dc4
RK
71
72 if (last_VFP_context[cpu] == vfp)
73 last_VFP_context[cpu] = NULL;
797245f5 74 put_cpu();
0d782dc4
RK
75}
76
77/*
78 * When this function is called with the following 'cmd's, the following
79 * is true while this function is being run:
80 * THREAD_NOFTIFY_SWTICH:
81 * - the previously running thread will not be scheduled onto another CPU.
82 * - the next thread to be run (v) will not be running on another CPU.
83 * - thread->cpu is the local CPU number
84 * - not preemptible as we're called in the middle of a thread switch
85 * THREAD_NOTIFY_FLUSH:
86 * - the thread (v) will be running on the local CPU, so
87 * v === current_thread_info()
88 * - thread->cpu is the local CPU number at the time it is accessed,
89 * but may change at any time.
90 * - we could be preempted if tree preempt rcu is enabled, so
91 * it is unsafe to use thread->cpu.
797245f5
RK
92 * THREAD_NOTIFY_EXIT
93 * - the thread (v) will be running on the local CPU, so
94 * v === current_thread_info()
95 * - thread->cpu is the local CPU number at the time it is accessed,
96 * but may change at any time.
97 * - we could be preempted if tree preempt rcu is enabled, so
98 * it is unsafe to use thread->cpu.
0d782dc4 99 */
d6551e88 100static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
1da177e4 101{
d6551e88 102 struct thread_info *thread = v;
1da177e4 103
681a4991 104 if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
c6428464
CM
105 u32 fpexc = fmrx(FPEXC);
106
107#ifdef CONFIG_SMP
0d782dc4
RK
108 unsigned int cpu = thread->cpu;
109
c6428464
CM
110 /*
111 * On SMP, if VFP is enabled, save the old state in
112 * case the thread migrates to a different CPU. The
113 * restoring is done lazily.
114 */
228adef1 115 if ((fpexc & FPEXC_EN) && last_VFP_context[cpu]) {
c6428464
CM
116 vfp_save_state(last_VFP_context[cpu], fpexc);
117 last_VFP_context[cpu]->hard.cpu = cpu;
118 }
119 /*
120 * Thread migration, just force the reloading of the
121 * state on the new CPU in case the VFP registers
122 * contain stale data.
123 */
124 if (thread->vfpstate.hard.cpu != cpu)
125 last_VFP_context[cpu] = NULL;
126#endif
127
681a4991
RK
128 /*
129 * Always disable VFP so we can lazily save/restore the
130 * old state.
131 */
228adef1 132 fmxr(FPEXC, fpexc & ~FPEXC_EN);
681a4991
RK
133 return NOTIFY_DONE;
134 }
135
0d782dc4
RK
136 if (cmd == THREAD_NOTIFY_FLUSH)
137 vfp_thread_flush(thread);
138 else
797245f5 139 vfp_thread_exit(thread);
681a4991 140
d6551e88 141 return NOTIFY_DONE;
1da177e4
LT
142}
143
d6551e88
RK
144static struct notifier_block vfp_notifier_block = {
145 .notifier_call = vfp_notifier,
146};
147
1da177e4
LT
148/*
149 * Raise a SIGFPE for the current process.
150 * sicode describes the signal being raised.
151 */
152void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
153{
154 siginfo_t info;
155
156 memset(&info, 0, sizeof(info));
157
158 info.si_signo = SIGFPE;
159 info.si_code = sicode;
35d59fc5 160 info.si_addr = (void __user *)(instruction_pointer(regs) - 4);
1da177e4
LT
161
162 /*
163 * This is the same as NWFPE, because it's not clear what
164 * this is used for
165 */
166 current->thread.error_code = 0;
167 current->thread.trap_no = 6;
168
da41119a 169 send_sig_info(SIGFPE, &info, current);
1da177e4
LT
170}
171
c98929c0 172static void vfp_panic(char *reason, u32 inst)
1da177e4
LT
173{
174 int i;
175
176 printk(KERN_ERR "VFP: Error: %s\n", reason);
177 printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
c98929c0 178 fmrx(FPEXC), fmrx(FPSCR), inst);
1da177e4
LT
179 for (i = 0; i < 32; i += 2)
180 printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
181 i, vfp_get_float(i), i+1, vfp_get_float(i+1));
182}
183
184/*
185 * Process bitmask of exception conditions.
186 */
187static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs)
188{
189 int si_code = 0;
190
191 pr_debug("VFP: raising exceptions %08x\n", exceptions);
192
7c6f2514 193 if (exceptions == VFP_EXCEPTION_ERROR) {
c98929c0 194 vfp_panic("unhandled bounce", inst);
1da177e4
LT
195 vfp_raise_sigfpe(0, regs);
196 return;
197 }
198
199 /*
dbead405 200 * If any of the status flags are set, update the FPSCR.
1da177e4
LT
201 * Comparison instructions always return at least one of
202 * these flags set.
203 */
dbead405
CM
204 if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
205 fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
206
1da177e4
LT
207 fpscr |= exceptions;
208
209 fmxr(FPSCR, fpscr);
210
211#define RAISE(stat,en,sig) \
212 if (exceptions & stat && fpscr & en) \
213 si_code = sig;
214
215 /*
216 * These are arranged in priority order, least to highest.
217 */
e0f205d9 218 RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV);
1da177e4
LT
219 RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES);
220 RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND);
221 RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF);
222 RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV);
223
224 if (si_code)
225 vfp_raise_sigfpe(si_code, regs);
226}
227
228/*
229 * Emulate a VFP instruction.
230 */
231static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
232{
7c6f2514 233 u32 exceptions = VFP_EXCEPTION_ERROR;
1da177e4
LT
234
235 pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);
236
237 if (INST_CPRTDO(inst)) {
238 if (!INST_CPRT(inst)) {
239 /*
240 * CPDO
241 */
242 if (vfp_single(inst)) {
243 exceptions = vfp_single_cpdo(inst, fpscr);
244 } else {
245 exceptions = vfp_double_cpdo(inst, fpscr);
246 }
247 } else {
248 /*
249 * A CPRT instruction can not appear in FPINST2, nor
250 * can it cause an exception. Therefore, we do not
251 * have to emulate it.
252 */
253 }
254 } else {
255 /*
256 * A CPDT instruction can not appear in FPINST2, nor can
257 * it cause an exception. Therefore, we do not have to
258 * emulate it.
259 */
260 }
928bd1b4 261 return exceptions & ~VFP_NAN_FLAG;
1da177e4
LT
262}
263
264/*
265 * Package up a bounce condition.
266 */
c98929c0 267void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
1da177e4 268{
c98929c0 269 u32 fpscr, orig_fpscr, fpsid, exceptions;
1da177e4
LT
270
271 pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);
272
273 /*
c98929c0
CM
274 * At this point, FPEXC can have the following configuration:
275 *
276 * EX DEX IXE
277 * 0 1 x - synchronous exception
278 * 1 x 0 - asynchronous exception
279 * 1 x 1 - sychronous on VFP subarch 1 and asynchronous on later
280 * 0 0 1 - synchronous on VFP9 (non-standard subarch 1
281 * implementation), undefined otherwise
282 *
283 * Clear various bits and enable access to the VFP so we can
284 * handle the bounce.
1da177e4 285 */
c98929c0 286 fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK));
1da177e4 287
c98929c0 288 fpsid = fmrx(FPSID);
1da177e4
LT
289 orig_fpscr = fpscr = fmrx(FPSCR);
290
291 /*
c98929c0 292 * Check for the special VFP subarch 1 and FPSCR.IXE bit case
1da177e4 293 */
c98929c0
CM
294 if ((fpsid & FPSID_ARCH_MASK) == (1 << FPSID_ARCH_BIT)
295 && (fpscr & FPSCR_IXE)) {
296 /*
297 * Synchronous exception, emulate the trigger instruction
298 */
1da177e4
LT
299 goto emulate;
300 }
301
c98929c0 302 if (fpexc & FPEXC_EX) {
85d6943a 303#ifndef CONFIG_CPU_FEROCEON
c98929c0
CM
304 /*
305 * Asynchronous exception. The instruction is read from FPINST
306 * and the interrupted instruction has to be restarted.
307 */
308 trigger = fmrx(FPINST);
309 regs->ARM_pc -= 4;
85d6943a 310#endif
c98929c0
CM
311 } else if (!(fpexc & FPEXC_DEX)) {
312 /*
313 * Illegal combination of bits. It can be caused by an
314 * unallocated VFP instruction but with FPSCR.IXE set and not
315 * on VFP subarch 1.
316 */
317 vfp_raise_exceptions(VFP_EXCEPTION_ERROR, trigger, fpscr, regs);
f2255be8 318 goto exit;
c98929c0 319 }
1da177e4
LT
320
321 /*
c98929c0
CM
322 * Modify fpscr to indicate the number of iterations remaining.
323 * If FPEXC.EX is 0, FPEXC.DEX is 1 and the FPEXC.VV bit indicates
324 * whether FPEXC.VECITR or FPSCR.LEN is used.
1da177e4 325 */
c98929c0 326 if (fpexc & (FPEXC_EX | FPEXC_VV)) {
1da177e4
LT
327 u32 len;
328
329 len = fpexc + (1 << FPEXC_LENGTH_BIT);
330
331 fpscr &= ~FPSCR_LENGTH_MASK;
332 fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT);
333 }
334
335 /*
336 * Handle the first FP instruction. We used to take note of the
337 * FPEXC bounce reason, but this appears to be unreliable.
338 * Emulate the bounced instruction instead.
339 */
c98929c0 340 exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
1da177e4 341 if (exceptions)
c98929c0 342 vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
1da177e4
LT
343
344 /*
c98929c0
CM
345 * If there isn't a second FP instruction, exit now. Note that
346 * the FPEXC.FP2V bit is valid only if FPEXC.EX is 1.
1da177e4 347 */
c98929c0 348 if (fpexc ^ (FPEXC_EX | FPEXC_FP2V))
f2255be8 349 goto exit;
1da177e4
LT
350
351 /*
352 * The barrier() here prevents fpinst2 being read
353 * before the condition above.
354 */
355 barrier();
356 trigger = fmrx(FPINST2);
1da177e4
LT
357
358 emulate:
c98929c0 359 exceptions = vfp_emulate_instruction(trigger, orig_fpscr, regs);
1da177e4
LT
360 if (exceptions)
361 vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
f2255be8
GD
362 exit:
363 preempt_enable();
1da177e4 364}
efe90d27 365
8e140362
RK
366static void vfp_enable(void *unused)
367{
368 u32 access = get_copro_access();
369
370 /*
371 * Enable full access to VFP (cp10 and cp11)
372 */
373 set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
374}
375
fc0b7a20
BD
376#ifdef CONFIG_PM
377#include <linux/sysdev.h>
378
379static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state)
380{
381 struct thread_info *ti = current_thread_info();
382 u32 fpexc = fmrx(FPEXC);
383
384 /* if vfp is on, then save state for resumption */
385 if (fpexc & FPEXC_EN) {
386 printk(KERN_DEBUG "%s: saving vfp state\n", __func__);
387 vfp_save_state(&ti->vfpstate, fpexc);
388
389 /* disable, just in case */
390 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
391 }
392
393 /* clear any information we had about last context state */
394 memset(last_VFP_context, 0, sizeof(last_VFP_context));
395
396 return 0;
397}
398
399static int vfp_pm_resume(struct sys_device *dev)
400{
401 /* ensure we have access to the vfp */
402 vfp_enable(NULL);
403
404 /* and disable it to ensure the next usage restores the state */
405 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
406
407 return 0;
408}
409
410static struct sysdev_class vfp_pm_sysclass = {
411 .name = "vfp",
412 .suspend = vfp_pm_suspend,
413 .resume = vfp_pm_resume,
414};
415
416static struct sys_device vfp_pm_sysdev = {
417 .cls = &vfp_pm_sysclass,
418};
419
420static void vfp_pm_init(void)
421{
422 sysdev_class_register(&vfp_pm_sysclass);
423 sysdev_register(&vfp_pm_sysdev);
424}
425
426
427#else
428static inline void vfp_pm_init(void) { }
429#endif /* CONFIG_PM */
430
3d1228ea
CM
431/*
432 * Synchronise the hardware VFP state of a thread other than current with the
433 * saved one. This function is used by the ptrace mechanism.
434 */
435#ifdef CONFIG_SMP
ad187f95
RK
436void vfp_sync_hwstate(struct thread_info *thread)
437{
438}
439
440void vfp_flush_hwstate(struct thread_info *thread)
3d1228ea
CM
441{
442 /*
443 * On SMP systems, the VFP state is automatically saved at every
444 * context switch. We mark the thread VFP state as belonging to a
445 * non-existent CPU so that the saved one will be reloaded when
446 * needed.
447 */
448 thread->vfpstate.hard.cpu = NR_CPUS;
449}
450#else
ad187f95 451void vfp_sync_hwstate(struct thread_info *thread)
3d1228ea
CM
452{
453 unsigned int cpu = get_cpu();
3d1228ea
CM
454
455 /*
54cb3dbb
RK
456 * If the thread we're interested in is the current owner of the
457 * hardware VFP state, then we need to save its state.
3d1228ea 458 */
54cb3dbb
RK
459 if (last_VFP_context[cpu] == &thread->vfpstate) {
460 u32 fpexc = fmrx(FPEXC);
3d1228ea 461
54cb3dbb
RK
462 /*
463 * Save the last VFP state on this CPU.
464 */
465 fmxr(FPEXC, fpexc | FPEXC_EN);
466 vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN);
ad187f95
RK
467 fmxr(FPEXC, fpexc);
468 }
3d1228ea 469
ad187f95
RK
470 put_cpu();
471}
472
473void vfp_flush_hwstate(struct thread_info *thread)
474{
475 unsigned int cpu = get_cpu();
3d1228ea
CM
476
477 /*
ad187f95
RK
478 * If the thread we're interested in is the current owner of the
479 * hardware VFP state, then we need to save its state.
3d1228ea 480 */
ad187f95
RK
481 if (last_VFP_context[cpu] == &thread->vfpstate) {
482 u32 fpexc = fmrx(FPEXC);
483
54cb3dbb 484 fmxr(FPEXC, fpexc & ~FPEXC_EN);
3d1228ea 485
54cb3dbb
RK
486 /*
487 * Set the context to NULL to force a reload the next time
488 * the thread uses the VFP.
489 */
490 last_VFP_context[cpu] = NULL;
491 }
3d1228ea 492
3d1228ea
CM
493 put_cpu();
494}
495#endif
496
8e140362
RK
497#include <linux/smp.h>
498
1da177e4
LT
499/*
500 * VFP support code initialisation.
501 */
502static int __init vfp_init(void)
503{
504 unsigned int vfpsid;
efe90d27 505 unsigned int cpu_arch = cpu_architecture();
efe90d27 506
c98929c0
CM
507 if (cpu_arch >= CPU_ARCH_ARMv6)
508 vfp_enable(NULL);
1da177e4
LT
509
510 /*
511 * First check that there is a VFP that we can use.
512 * The handler is already setup to just log calls, so
513 * we just need to read the VFPSID register.
514 */
5d4cae5f 515 vfp_vector = vfp_testing_entry;
b9338a78 516 barrier();
1da177e4 517 vfpsid = fmrx(FPSID);
8e140362 518 barrier();
5d4cae5f 519 vfp_vector = vfp_null_entry;
1da177e4
LT
520
521 printk(KERN_INFO "VFP support v0.3: ");
c98929c0 522 if (VFP_arch)
1da177e4 523 printk("not present\n");
c98929c0 524 else if (vfpsid & FPSID_NODOUBLE) {
1da177e4
LT
525 printk("no double precision support\n");
526 } else {
8691e5a8 527 smp_call_function(vfp_enable, NULL, 1);
8e140362 528
1da177e4
LT
529 VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */
530 printk("implementor %02x architecture %d part %02x variant %x rev %x\n",
531 (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
532 (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
533 (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
534 (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
535 (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
efe90d27 536
1da177e4 537 vfp_vector = vfp_support_entry;
d6551e88
RK
538
539 thread_register_notifier(&vfp_notifier_block);
fc0b7a20 540 vfp_pm_init();
efe90d27
RK
541
542 /*
543 * We detected VFP, and the support code is
544 * in place; report VFP support to userspace.
545 */
546 elf_hwcap |= HWCAP_VFP;
7279dc3e 547#ifdef CONFIG_VFPv3
325ffc36 548 if (VFP_arch >= 2) {
7279dc3e
CM
549 elf_hwcap |= HWCAP_VFPv3;
550
551 /*
552 * Check for VFPv3 D16. CPUs in this configuration
553 * only have 16 x 64bit registers.
554 */
555 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1)
556 elf_hwcap |= HWCAP_VFPv3D16;
557 }
558#endif
2bedbdf4
CM
559#ifdef CONFIG_NEON
560 /*
561 * Check for the presence of the Advanced SIMD
562 * load/store instructions, integer and single
563 * precision floating point operations.
564 */
565 if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
566 elf_hwcap |= HWCAP_NEON;
567#endif
1da177e4
LT
568 }
569 return 0;
570}
571
572late_initcall(vfp_init);