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ARM: S5P6440: Add Clock and PLL support
[net-next-2.6.git] / arch / arm / plat-samsung / include / plat / clock.h
CommitLineData
a503059c 1/* linux/arch/arm/plat-s3c/include/plat/clock.h
1da177e4
LT		 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Written by Ben Dooks, <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
c3391e36
BD		 12#include <linux/spinlock.h>
13
b3bf41be
BD		 14struct clk;
15
16/**
17 * struct clk_ops - standard clock operations
18 * @set_rate: set the clock rate, see clk_set_rate().
19 * @get_rate: get the clock rate, see clk_get_rate().
20 * @round_rate: round a given clock rate, see clk_round_rate().
21 * @set_parent: set the clock's parent, see clk_set_parent().
22 *
23 * Group the common clock implementations together so that we
24 * don't have to keep setting the same fiels again. We leave
25 * enable in struct clk.
26 *
27 * Adding an extra layer of indirection into the process should
28 * not be a problem as it is unlikely these operations are going
29 * to need to be called quickly.
30 */
31struct clk_ops {
32 int (*set_rate)(struct clk *c, unsigned long rate);
33 unsigned long (*get_rate)(struct clk *c);
34 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
35 int (*set_parent)(struct clk *c, struct clk *parent);
36};
37
1da177e4
LT		 38struct clk {
39 struct list_head list;
40 struct module *owner;
41 struct clk *parent;
42 const char *name;
43 int id;
2a513ce7 44 int usage;
1da177e4
LT		 45 unsigned long rate;
46 unsigned long ctrlbit;
d3468daa 47
b3bf41be 48 struct clk_ops *ops;
1da177e4
LT		 49 int (*enable)(struct clk *, int enable);
50};
51
52/* other clocks which may be registered by board support */
53
54extern struct clk s3c24xx_dclk0;
55extern struct clk s3c24xx_dclk1;
56extern struct clk s3c24xx_clkout0;
57extern struct clk s3c24xx_clkout1;
58extern struct clk s3c24xx_uclk;
59
36c64af4
BD		 60extern struct clk clk_usb_bus;
61
99c13853
BD		 62/* core clock support */
63
64extern struct clk clk_f;
65extern struct clk clk_h;
66extern struct clk clk_p;
513846f8 67extern struct clk clk_mpll;
99c13853 68extern struct clk clk_upll;
4b31d8b2 69extern struct clk clk_epll;
513846f8 70extern struct clk clk_xtal;
4b31d8b2
BD		 71extern struct clk clk_ext;
72
73/* S3C64XX specific clocks */
a03f7daf 74extern struct clk clk_h2;
4b31d8b2
BD		 75extern struct clk clk_27m;
76extern struct clk clk_48m;
99c13853 77
ed276849
KK		 78extern int clk_default_setrate(struct clk *clk, unsigned long rate);
79extern struct clk_ops clk_ops_def_setrate;
80
1da177e4
LT		 81/* exports for arch/arm/mach-s3c2410
82 *
83 * Please DO NOT use these outside of arch/arm/mach-s3c2410
84*/
85
c3391e36 86extern spinlock_t clocks_lock;
36c64af4 87
99c13853
BD		 88extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
89
1da177e4 90extern int s3c24xx_register_clock(struct clk *clk);
ce89c206 91extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
1da177e4 92
1d9f13c4
BD		 93extern void s3c_register_clocks(struct clk *clk, int nr_clks);
94
e425382e
BD		 95extern int s3c24xx_register_baseclocks(unsigned long xtal);
96
4b31d8b2 97extern void s3c64xx_register_clocks(void);
1a0e8a52 98extern void s5p_register_clocks(unsigned long xtal_freq);
4b31d8b2 99
e425382e
BD		 100extern void s3c24xx_setup_clocks(unsigned long fclk,
101 unsigned long hclk,
102 unsigned long pclk);
103
104extern void s3c2410_setup_clocks(void);
105extern void s3c2412_setup_clocks(void);
106extern void s3c244x_setup_clocks(void);
107extern void s3c2443_setup_clocks(void);
108
cf18acf0
BD		 109/* S3C64XX specific functions and clocks */
110
111extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
9d325f23
BD		 112
113/* Init for pwm clock code */
114
115extern void s3c_pwmclk_init(void);
116
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