[net-next-2.6.git] / arch / arm / plat-samsung / gpio-config.c

/* linux/arch/arm/plat-s3c/gpio-config.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008-2010 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C series GPIO configuration core
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/io.h>

#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>

int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
{
	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	unsigned long flags;
	int offset;
	int ret;

	if (!chip)
		return -EINVAL;

	offset = pin - chip->chip.base;

	s3c_gpio_lock(chip, flags);
	ret = s3c_gpio_do_setcfg(chip, offset, config);
	s3c_gpio_unlock(chip, flags);

	return ret;
}
EXPORT_SYMBOL(s3c_gpio_cfgpin);

int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
			  unsigned int cfg)
{
	int ret;

	for (; nr > 0; nr--, start++) {
		ret = s3c_gpio_cfgpin(start, cfg);
		if (ret != 0)
			return ret;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);

int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
			  unsigned int cfg, s3c_gpio_pull_t pull)
{
	int ret;

	for (; nr > 0; nr--, start++) {
		s3c_gpio_setpull(start, pull);
		ret = s3c_gpio_cfgpin(start, cfg);
		if (ret != 0)
			return ret;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);

unsigned s3c_gpio_getcfg(unsigned int pin)
{
	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	unsigned long flags;
	unsigned ret = 0;
	int offset;

	if (chip) {
		offset = pin - chip->chip.base;

		s3c_gpio_lock(chip, flags);
		ret = s3c_gpio_do_getcfg(chip, offset);
		s3c_gpio_unlock(chip, flags);
	}

	return ret;
}
EXPORT_SYMBOL(s3c_gpio_getcfg);


int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
{
	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	unsigned long flags;
	int offset, ret;

	if (!chip)
		return -EINVAL;

	offset = pin - chip->chip.base;

	s3c_gpio_lock(chip, flags);
	ret = s3c_gpio_do_setpull(chip, offset, pull);
	s3c_gpio_unlock(chip, flags);

	return ret;
}
EXPORT_SYMBOL(s3c_gpio_setpull);

#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
			      unsigned int off, unsigned int cfg)
{
	void __iomem *reg = chip->base;
	unsigned int shift = off;
	u32 con;

	if (s3c_gpio_is_cfg_special(cfg)) {
		cfg &= 0xf;

		/* Map output to 0, and SFN2 to 1 */
		cfg -= 1;
		if (cfg > 1)
			return -EINVAL;

		cfg <<= shift;
	}

	con = __raw_readl(reg);
	con &= ~(0x1 << shift);
	con |= cfg;
	__raw_writel(con, reg);

	return 0;
}

unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
				   unsigned int off)
{
	u32 con;

	con = __raw_readl(chip->base);
	con >>= off;
	con &= 1;
	con++;

	return S3C_GPIO_SFN(con);
}

int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
			    unsigned int off, unsigned int cfg)
{
	void __iomem *reg = chip->base;
	unsigned int shift = off * 2;
	u32 con;

	if (s3c_gpio_is_cfg_special(cfg)) {
		cfg &= 0xf;
		if (cfg > 3)
			return -EINVAL;

		cfg <<= shift;
	}

	con = __raw_readl(reg);
	con &= ~(0x3 << shift);
	con |= cfg;
	__raw_writel(con, reg);

	return 0;
}

unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
				     unsigned int off)
{
	u32 con;

	con = __raw_readl(chip->base);
	con >>= off * 2;
	con &= 3;

	/* this conversion works for IN and OUT as well as special mode */
	return S3C_GPIO_SPECIAL(con);
}
#endif

#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
				 unsigned int off, unsigned int cfg)
{
	void __iomem *reg = chip->base;
	unsigned int shift = (off & 7) * 4;
	u32 con;

	if (off < 8 && chip->chip.ngpio > 8)
		reg -= 4;

	if (s3c_gpio_is_cfg_special(cfg)) {
		cfg &= 0xf;
		cfg <<= shift;
	}

	con = __raw_readl(reg);
	con &= ~(0xf << shift);
	con |= cfg;
	__raw_writel(con, reg);

	return 0;
}

unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
				      unsigned int off)
{
	void __iomem *reg = chip->base;
	unsigned int shift = (off & 7) * 4;
	u32 con;

	if (off < 8 && chip->chip.ngpio > 8)
		reg -= 4;

	con = __raw_readl(reg);
	con >>= shift;
	con &= 0xf;

	/* this conversion works for IN and OUT as well as special mode */
	return S3C_GPIO_SPECIAL(con);
}

#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */

#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
			    unsigned int off, s3c_gpio_pull_t pull)
{
	void __iomem *reg = chip->base + 0x08;
	int shift = off * 2;
	u32 pup;

	pup = __raw_readl(reg);
	pup &= ~(3 << shift);
	pup |= pull << shift;
	__raw_writel(pup, reg);

	return 0;
}

s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
					unsigned int off)
{
	void __iomem *reg = chip->base + 0x08;
	int shift = off * 2;
	u32 pup = __raw_readl(reg);

	pup >>= shift;
	pup &= 0x3;
	return (__force s3c_gpio_pull_t)pup;
}
#endif

#ifdef CONFIG_S3C_GPIO_PULL_UP
int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
			 unsigned int off, s3c_gpio_pull_t pull)
{
	void __iomem *reg = chip->base + 0x08;
	u32 pup = __raw_readl(reg);

	pup = __raw_readl(reg);

	if (pup == S3C_GPIO_PULL_UP)
		pup &= ~(1 << off);
	else if (pup == S3C_GPIO_PULL_NONE)
		pup |= (1 << off);
	else
		return -EINVAL;

	__raw_writel(pup, reg);
	return 0;
}

s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
				     unsigned int off)
{
	void __iomem *reg = chip->base + 0x08;
	u32 pup = __raw_readl(reg);

	pup &= (1 << off);
	return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
}
#endif /* CONFIG_S3C_GPIO_PULL_UP */

#ifdef CONFIG_S5P_GPIO_DRVSTR
s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
{
	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	unsigned int off;
	void __iomem *reg;
	int shift;
	u32 drvstr;

	if (!chip)
		return -EINVAL;

	off = pin - chip->chip.base;
	shift = off * 2;
	reg = chip->base + 0x0C;

	drvstr = __raw_readl(reg);
	drvstr = drvstr >> shift;
	drvstr &= 0x3;

	return (__force s5p_gpio_drvstr_t)drvstr;
}
EXPORT_SYMBOL(s5p_gpio_get_drvstr);

int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
{
	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	unsigned int off;
	void __iomem *reg;
	int shift;
	u32 tmp;

	if (!chip)
		return -EINVAL;

	off = pin - chip->chip.base;
	shift = off * 2;
	reg = chip->base + 0x0C;

	tmp = __raw_readl(reg);
	tmp &= ~(0x3 << shift);
	tmp |= drvstr << shift;

	__raw_writel(tmp, reg);

	return 0;
}
EXPORT_SYMBOL(s5p_gpio_set_drvstr);
#endif	/* CONFIG_S5P_GPIO_DRVSTR */
Commit	Line	Data
21b23664 BD	1	/* linux/arch/arm/plat-s3c/gpio-config.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
97a33999	4	* Copyright 2008-2010 Simtec Electronics
21b23664 BD	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* S3C series GPIO configuration core
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
db756394	16	#include <linux/module.h>
21b23664 BD	17	#include <linux/gpio.h>
	18	#include <linux/io.h>
	19
e856bb1f	20	#include <plat/gpio-core.h>
21b23664 BD	21	#include <plat/gpio-cfg.h>
	22	#include <plat/gpio-cfg-helpers.h>
	23
	24	int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
	25	{
	26	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	27	unsigned long flags;
	28	int offset;
	29	int ret;
	30
	31	if (!chip)
	32	return -EINVAL;
	33
	34	offset = pin - chip->chip.base;
	35
fcef85c0	36	s3c_gpio_lock(chip, flags);
21b23664	37	ret = s3c_gpio_do_setcfg(chip, offset, config);
fcef85c0	38	s3c_gpio_unlock(chip, flags);
21b23664 BD	39
	40	return ret;
	41	}
db756394	42	EXPORT_SYMBOL(s3c_gpio_cfgpin);
21b23664	43
4b46fbba BD	44	int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
	45	unsigned int cfg)
	46	{
	47	int ret;
	48
	49	for (; nr > 0; nr--, start++) {
	50	ret = s3c_gpio_cfgpin(start, cfg);
	51	if (ret != 0)
	52	return ret;
	53	}
	54
	55	return 0;
	56	}
	57	EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
	58
5459148b BD	59	int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
	60	unsigned int cfg, s3c_gpio_pull_t pull)
	61	{
	62	int ret;
	63
	64	for (; nr > 0; nr--, start++) {
	65	s3c_gpio_setpull(start, pull);
	66	ret = s3c_gpio_cfgpin(start, cfg);
	67	if (ret != 0)
	68	return ret;
	69	}
	70
	71	return 0;
	72	}
	73	EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
	74
9933847b BD	75	unsigned s3c_gpio_getcfg(unsigned int pin)
	76	{
	77	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	78	unsigned long flags;
	79	unsigned ret = 0;
	80	int offset;
	81
	82	if (chip) {
	83	offset = pin - chip->chip.base;
	84
fcef85c0	85	s3c_gpio_lock(chip, flags);
9933847b	86	ret = s3c_gpio_do_getcfg(chip, offset);
fcef85c0	87	s3c_gpio_unlock(chip, flags);
9933847b BD	88	}
	89
	90	return ret;
	91	}
	92	EXPORT_SYMBOL(s3c_gpio_getcfg);
	93
	94
21b23664 BD	95	int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
	96	{
	97	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	98	unsigned long flags;
	99	int offset, ret;
	100
	101	if (!chip)
	102	return -EINVAL;
	103
	104	offset = pin - chip->chip.base;
	105
fcef85c0	106	s3c_gpio_lock(chip, flags);
21b23664	107	ret = s3c_gpio_do_setpull(chip, offset, pull);
fcef85c0	108	s3c_gpio_unlock(chip, flags);
21b23664 BD	109
	110	return ret;
	111	}
db756394	112	EXPORT_SYMBOL(s3c_gpio_setpull);
21b23664 BD	113
21b23664 BD	114	#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
9bbb851c BD	115	int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
9bbb851c BD	116	unsigned int off, unsigned int cfg)
21b23664 BD	117	{
	118	void __iomem *reg = chip->base;
	119	unsigned int shift = off;
	120	u32 con;
	121
	122	if (s3c_gpio_is_cfg_special(cfg)) {
	123	cfg &= 0xf;
	124
	125	/* Map output to 0, and SFN2 to 1 */
	126	cfg -= 1;
	127	if (cfg > 1)
	128	return -EINVAL;
	129
	130	cfg <<= shift;
	131	}
	132
	133	con = __raw_readl(reg);
	134	con &= ~(0x1 << shift);
	135	con \|= cfg;
	136	__raw_writel(con, reg);
	137
	138	return 0;
	139	}
	140
97a33999 BD	141	unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
	142	unsigned int off)
	143	{
	144	u32 con;
	145
	146	con = __raw_readl(chip->base);
	147	con >>= off;
	148	con &= 1;
	149	con++;
	150
	151	return S3C_GPIO_SFN(con);
	152	}
	153
21b23664 BD	154	int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
	155	unsigned int off, unsigned int cfg)
	156	{
	157	void __iomem *reg = chip->base;
	158	unsigned int shift = off * 2;
	159	u32 con;
	160
	161	if (s3c_gpio_is_cfg_special(cfg)) {
	162	cfg &= 0xf;
	163	if (cfg > 3)
	164	return -EINVAL;
	165
	166	cfg <<= shift;
	167	}
	168
	169	con = __raw_readl(reg);
	170	con &= ~(0x3 << shift);
	171	con \|= cfg;
	172	__raw_writel(con, reg);
	173
	174	return 0;
	175	}
97a33999 BD	176
	177	unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
	178	unsigned int off)
	179	{
	180	u32 con;
	181
	182	con = __raw_readl(chip->base);
	183	con >>= off * 2;
	184	con &= 3;
	185
	186	/* this conversion works for IN and OUT as well as special mode */
	187	return S3C_GPIO_SPECIAL(con);
	188	}
21b23664 BD	189	#endif
	190
	191	#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
	192	int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
	193	unsigned int off, unsigned int cfg)
	194	{
	195	void __iomem *reg = chip->base;
	196	unsigned int shift = (off & 7) * 4;
	197	u32 con;
	198
49fb88af	199	if (off < 8 && chip->chip.ngpio > 8)
21b23664 BD	200	reg -= 4;
	201
	202	if (s3c_gpio_is_cfg_special(cfg)) {
	203	cfg &= 0xf;
	204	cfg <<= shift;
	205	}
	206
	207	con = __raw_readl(reg);
	208	con &= ~(0xf << shift);
	209	con \|= cfg;
	210	__raw_writel(con, reg);
	211
	212	return 0;
	213	}
97a33999 BD	214
	215	unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
	216	unsigned int off)
	217	{
	218	void __iomem *reg = chip->base;
	219	unsigned int shift = (off & 7) * 4;
	220	u32 con;
	221
	222	if (off < 8 && chip->chip.ngpio > 8)
	223	reg -= 4;
	224
	225	con = __raw_readl(reg);
	226	con >>= shift;
	227	con &= 0xf;
	228
	229	/* this conversion works for IN and OUT as well as special mode */
	230	return S3C_GPIO_SPECIAL(con);
	231	}
	232
21b23664 BD	233	#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
	234
	235	#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
	236	int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
	237	unsigned int off, s3c_gpio_pull_t pull)
	238	{
	239	void __iomem *reg = chip->base + 0x08;
	240	int shift = off * 2;
	241	u32 pup;
	242
	243	pup = __raw_readl(reg);
	244	pup &= ~(3 << shift);
	245	pup \|= pull << shift;
	246	__raw_writel(pup, reg);
	247
	248	return 0;
	249	}
	250
	251	s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
	252	unsigned int off)
	253	{
	254	void __iomem *reg = chip->base + 0x08;
	255	int shift = off * 2;
	256	u32 pup = __raw_readl(reg);
	257
	258	pup >>= shift;
	259	pup &= 0x3;
	260	return (__force s3c_gpio_pull_t)pup;
	261	}
	262	#endif
1ec7269f BD	263
	264	#ifdef CONFIG_S3C_GPIO_PULL_UP
	265	int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
	266	unsigned int off, s3c_gpio_pull_t pull)
	267	{
	268	void __iomem *reg = chip->base + 0x08;
	269	u32 pup = __raw_readl(reg);
	270
	271	pup = __raw_readl(reg);
	272
	273	if (pup == S3C_GPIO_PULL_UP)
	274	pup &= ~(1 << off);
	275	else if (pup == S3C_GPIO_PULL_NONE)
	276	pup \|= (1 << off);
	277	else
	278	return -EINVAL;
	279
	280	__raw_writel(pup, reg);
	281	return 0;
	282	}
	283
	284	s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
	285	unsigned int off)
	286	{
	287	void __iomem *reg = chip->base + 0x08;
	288	u32 pup = __raw_readl(reg);
	289
	290	pup &= (1 << off);
	291	return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
	292	}
	293	#endif /* CONFIG_S3C_GPIO_PULL_UP */
	294
838c6d49 MS	295	#ifdef CONFIG_S5P_GPIO_DRVSTR
	296	s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
	297	{
	298	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	299	unsigned int off;
	300	void __iomem *reg;
	301	int shift;
	302	u32 drvstr;
	303
	304	if (!chip)
	305	return -EINVAL;
	306
cbd2780f	307	off = pin - chip->chip.base;
838c6d49 MS	308	shift = off * 2;
	309	reg = chip->base + 0x0C;
	310
	311	drvstr = __raw_readl(reg);
838c6d49	312	drvstr = drvstr >> shift;
cbd2780f	313	drvstr &= 0x3;
838c6d49 MS	314
	315	return (__force s5p_gpio_drvstr_t)drvstr;
	316	}
	317	EXPORT_SYMBOL(s5p_gpio_get_drvstr);
	318
	319	int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
	320	{
	321	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
	322	unsigned int off;
	323	void __iomem *reg;
	324	int shift;
	325	u32 tmp;
	326
	327	if (!chip)
	328	return -EINVAL;
	329
cbd2780f	330	off = pin - chip->chip.base;
838c6d49 MS	331	shift = off * 2;
	332	reg = chip->base + 0x0C;
	333
	334	tmp = __raw_readl(reg);
cbd2780f	335	tmp &= ~(0x3 << shift);
838c6d49 MS	336	tmp \|= drvstr << shift;
	337
	338	__raw_writel(tmp, reg);
	339
	340	return 0;
	341	}
	342	EXPORT_SYMBOL(s5p_gpio_set_drvstr);
	343	#endif /* CONFIG_S5P_GPIO_DRVSTR */