[net-next-2.6.git] / arch / arm / plat-s3c24xx / gpiolib.c

/* linux/arch/arm/plat-s3c24xx/gpiolib.c
 *
 * Copyright (c) 2008-2010 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX GPIOlib support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/pm.h>

#include <mach/regs-gpio.h>

static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
{
	return -EINVAL;
}

static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
	void __iomem *base = ourchip->base;
	unsigned long flags;
	unsigned long dat;
	unsigned long con;

	local_irq_save(flags);

	con = __raw_readl(base + 0x00);
	dat = __raw_readl(base + 0x04);

	dat &= ~(1 << offset);
	if (value)
		dat |= 1 << offset;

	__raw_writel(dat, base + 0x04);

	con &= ~(1 << offset);

	__raw_writel(con, base + 0x00);
	__raw_writel(dat, base + 0x04);

	local_irq_restore(flags);
	return 0;
}

static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
{
	if (offset < 4)
		return IRQ_EINT0 + offset;
	
	if (offset < 8)
		return IRQ_EINT4 + offset - 4;
	
	return -EINVAL;
}

static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
{
	return IRQ_EINT8 + offset;
}

static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
	.set_config	= s3c_gpio_setcfg_s3c24xx_a,
	.get_config	= s3c_gpio_getcfg_s3c24xx_a,
};

struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
	.set_config	= s3c_gpio_setcfg_s3c24xx,
	.get_config	= s3c_gpio_getcfg_s3c24xx,
};

struct s3c_gpio_chip s3c24xx_gpios[] = {
	[0] = {
		.base	= S3C2410_GPACON,
		.pm	= __gpio_pm(&s3c_gpio_pm_1bit),
		.config	= &s3c24xx_gpiocfg_banka,
		.chip	= {
			.base			= S3C2410_GPA(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOA",
			.ngpio			= 24,
			.direction_input	= s3c24xx_gpiolib_banka_input,
			.direction_output	= s3c24xx_gpiolib_banka_output,
		},
	},
	[1] = {
		.base	= S3C2410_GPBCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPB(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOB",
			.ngpio			= 16,
		},
	},
	[2] = {
		.base	= S3C2410_GPCCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPC(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOC",
			.ngpio			= 16,
		},
	},
	[3] = {
		.base	= S3C2410_GPDCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPD(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOD",
			.ngpio			= 16,
		},
	},
	[4] = {
		.base	= S3C2410_GPECON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPE(0),
			.label			= "GPIOE",
			.owner			= THIS_MODULE,
			.ngpio			= 16,
		},
	},
	[5] = {
		.base	= S3C2410_GPFCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPF(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOF",
			.ngpio			= 8,
			.to_irq			= s3c24xx_gpiolib_bankf_toirq,
		},
	},
	[6] = {
		.base	= S3C2410_GPGCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPG(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOG",
			.ngpio			= 16,
			.to_irq			= s3c24xx_gpiolib_bankg_toirq,
		},
	}, {
		.base	= S3C2410_GPHCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPH(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOH",
			.ngpio			= 11,
		},
	},
		/* GPIOS for the S3C2443 and later devices. */
	{
		.base	= S3C2440_GPJCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPJ(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOJ",
			.ngpio			= 16,
		},
	}, {
		.base	= S3C2443_GPKCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPK(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOK",
			.ngpio			= 16,
		},
	}, {
		.base	= S3C2443_GPLCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPL(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOL",
			.ngpio			= 15,
		},
	}, {
		.base	= S3C2443_GPMCON,
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPM(0),
			.owner			= THIS_MODULE,
			.label			= "GPIOM",
			.ngpio			= 2,
		},
	},
};


static __init int s3c24xx_gpiolib_init(void)
{
	struct s3c_gpio_chip *chip = s3c24xx_gpios;
	int gpn;

	for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
		if (!chip->config)
			chip->config = &s3c24xx_gpiocfg_default;

		s3c_gpiolib_add(chip);
	}

	return 0;
}

core_initcall(s3c24xx_gpiolib_init);
Commit	Line	Data
f348a2a2 BD	1	/* linux/arch/arm/plat-s3c24xx/gpiolib.c
f348a2a2 BD	2	*
7ced5eab	3	* Copyright (c) 2008-2010 Simtec Electronics
f348a2a2 BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C24XX GPIOlib support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/interrupt.h>
86c03c52	18	#include <linux/sysdev.h>
f348a2a2 BD	19	#include <linux/ioport.h>
	20	#include <linux/io.h>
	21	#include <linux/gpio.h>
	22
e856bb1f	23	#include <plat/gpio-core.h>
9bbb851c BD	24	#include <plat/gpio-cfg.h>
9bbb851c BD	25	#include <plat/gpio-cfg-helpers.h>
a09e64fb	26	#include <mach/hardware.h>
f348a2a2	27	#include <asm/irq.h>
d87964c4	28	#include <plat/pm.h>
f348a2a2	29
a09e64fb	30	#include <mach/regs-gpio.h>
f348a2a2	31
f348a2a2 BD	32	static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
	33	{
	34	return -EINVAL;
	35	}
	36
	37	static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
	38	unsigned offset, int value)
	39	{
7db6c82a	40	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
f348a2a2 BD	41	void __iomem *base = ourchip->base;
	42	unsigned long flags;
	43	unsigned long dat;
	44	unsigned long con;
	45
	46	local_irq_save(flags);
	47
	48	con = __raw_readl(base + 0x00);
	49	dat = __raw_readl(base + 0x04);
	50
	51	dat &= ~(1 << offset);
	52	if (value)
	53	dat \|= 1 << offset;
	54
	55	__raw_writel(dat, base + 0x04);
	56
	57	con &= ~(1 << offset);
	58
	59	__raw_writel(con, base + 0x00);
	60	__raw_writel(dat, base + 0x04);
	61
	62	local_irq_restore(flags);
	63	return 0;
	64	}
	65
43ae6599 BD	66	static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
	67	{
	68	if (offset < 4)
	69	return IRQ_EINT0 + offset;
	70
	71	if (offset < 8)
	72	return IRQ_EINT4 + offset - 4;
	73
	74	return -EINVAL;
	75	}
	76
	77	static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
	78	{
	79	return IRQ_EINT8 + offset;
	80	}
	81
9bbb851c BD	82	static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
9bbb851c BD	83	.set_config = s3c_gpio_setcfg_s3c24xx_a,
97a33999	84	.get_config = s3c_gpio_getcfg_s3c24xx_a,
9bbb851c BD	85	};
	86
	87	struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
	88	.set_config = s3c_gpio_setcfg_s3c24xx,
97a33999	89	.get_config = s3c_gpio_getcfg_s3c24xx,
9bbb851c BD	90	};
9bbb851c BD	91
21b23664	92	struct s3c_gpio_chip s3c24xx_gpios[] = {
f348a2a2	93	[0] = {
fda7b2b0	94	.base = S3C2410_GPACON,
d87964c4	95	.pm = __gpio_pm(&s3c_gpio_pm_1bit),
9bbb851c	96	.config = &s3c24xx_gpiocfg_banka,
f348a2a2	97	.chip = {
070276d5	98	.base = S3C2410_GPA(0),
f348a2a2 BD	99	.owner = THIS_MODULE,
	100	.label = "GPIOA",
	101	.ngpio = 24,
	102	.direction_input = s3c24xx_gpiolib_banka_input,
	103	.direction_output = s3c24xx_gpiolib_banka_output,
f348a2a2 BD	104	},
	105	},
	106	[1] = {
fda7b2b0	107	.base = S3C2410_GPBCON,
d87964c4	108	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	109	.chip = {
070276d5	110	.base = S3C2410_GPB(0),
f348a2a2 BD	111	.owner = THIS_MODULE,
	112	.label = "GPIOB",
	113	.ngpio = 16,
f348a2a2 BD	114	},
	115	},
	116	[2] = {
fda7b2b0	117	.base = S3C2410_GPCCON,
d87964c4	118	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	119	.chip = {
070276d5	120	.base = S3C2410_GPC(0),
f348a2a2 BD	121	.owner = THIS_MODULE,
	122	.label = "GPIOC",
	123	.ngpio = 16,
f348a2a2 BD	124	},
	125	},
	126	[3] = {
fda7b2b0	127	.base = S3C2410_GPDCON,
d87964c4	128	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	129	.chip = {
070276d5	130	.base = S3C2410_GPD(0),
f348a2a2 BD	131	.owner = THIS_MODULE,
	132	.label = "GPIOD",
	133	.ngpio = 16,
f348a2a2 BD	134	},
	135	},
	136	[4] = {
fda7b2b0	137	.base = S3C2410_GPECON,
d87964c4	138	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	139	.chip = {
070276d5	140	.base = S3C2410_GPE(0),
f348a2a2 BD	141	.label = "GPIOE",
	142	.owner = THIS_MODULE,
	143	.ngpio = 16,
f348a2a2 BD	144	},
	145	},
	146	[5] = {
fda7b2b0	147	.base = S3C2410_GPFCON,
d87964c4	148	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	149	.chip = {
070276d5	150	.base = S3C2410_GPF(0),
f348a2a2 BD	151	.owner = THIS_MODULE,
	152	.label = "GPIOF",
	153	.ngpio = 8,
43ae6599	154	.to_irq = s3c24xx_gpiolib_bankf_toirq,
f348a2a2 BD	155	},
	156	},
	157	[6] = {
fda7b2b0	158	.base = S3C2410_GPGCON,
d87964c4	159	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2	160	.chip = {
070276d5	161	.base = S3C2410_GPG(0),
f348a2a2 BD	162	.owner = THIS_MODULE,
f348a2a2 BD	163	.label = "GPIOG",
5233c178	164	.ngpio = 16,
43ae6599	165	.to_irq = s3c24xx_gpiolib_bankg_toirq,
f348a2a2	166	},
5233c178 BD	167	}, {
	168	.base = S3C2410_GPHCON,
	169	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	170	.chip = {
	171	.base = S3C2410_GPH(0),
	172	.owner = THIS_MODULE,
	173	.label = "GPIOH",
	174	.ngpio = 11,
	175	},
f348a2a2	176	},
7ced5eab BD	177	/* GPIOS for the S3C2443 and later devices. */
	178	{
	179	.base = S3C2440_GPJCON,
	180	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	181	.chip = {
	182	.base = S3C2410_GPJ(0),
	183	.owner = THIS_MODULE,
	184	.label = "GPIOJ",
	185	.ngpio = 16,
	186	},
	187	}, {
	188	.base = S3C2443_GPKCON,
	189	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	190	.chip = {
	191	.base = S3C2410_GPK(0),
	192	.owner = THIS_MODULE,
	193	.label = "GPIOK",
	194	.ngpio = 16,
	195	},
	196	}, {
	197	.base = S3C2443_GPLCON,
	198	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	199	.chip = {
	200	.base = S3C2410_GPL(0),
	201	.owner = THIS_MODULE,
	202	.label = "GPIOL",
	203	.ngpio = 15,
	204	},
	205	}, {
	206	.base = S3C2443_GPMCON,
	207	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
	208	.chip = {
	209	.base = S3C2410_GPM(0),
	210	.owner = THIS_MODULE,
	211	.label = "GPIOM",
	212	.ngpio = 2,
	213	},
	214	},
f348a2a2 BD	215	};
f348a2a2 BD	216
7ced5eab	217
f348a2a2 BD	218	static __init int s3c24xx_gpiolib_init(void)
f348a2a2 BD	219	{
21b23664	220	struct s3c_gpio_chip *chip = s3c24xx_gpios;
f348a2a2 BD	221	int gpn;
f348a2a2 BD	222
9bbb851c BD	223	for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
	224	if (!chip->config)
	225	chip->config = &s3c24xx_gpiocfg_default;
	226
7db6c82a	227	s3c_gpiolib_add(chip);
9bbb851c	228	}
f348a2a2 BD	229
	230	return 0;
	231	}
	232
9c0ec957	233	core_initcall(s3c24xx_gpiolib_init);