[net-next-2.6.git] / arch / arm / plat-omap / include / plat / mux.h

/*
 * arch/arm/plat-omap/include/mach/mux.h
 *
 * Table of the Omap register configurations for the FUNC_MUX and
 * PULL_DWN combinations.
 *
 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
 * Copyright (C) 2003 - 2008 Nokia Corporation
 *
 * Written by Tony Lindgren
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * NOTE: Please use the following naming style for new pin entries.
 *	 For example, W8_1610_MMC2_DAT0, where:
 *	 - W8	     = ball
 *	 - 1610	     = 1510 or 1610, none if common for both 1510 and 1610
 *	 - MMC2_DAT0 = function
 */

#ifndef __ASM_ARCH_MUX_H
#define __ASM_ARCH_MUX_H

#define PU_PD_SEL_NA		0	/* No pu_pd reg available */
#define PULL_DWN_CTRL_NA	0	/* No pull-down control needed */

#ifdef	CONFIG_OMAP_MUX_DEBUG
#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
					.mux_reg = FUNC_MUX_CTRL_##reg, \
					.mask_offset = mode_offset, \
					.mask = mode,

#define PULL_REG(reg, bit, status)	.pull_name = "PULL_DWN_CTRL_"#reg, \
					.pull_reg = PULL_DWN_CTRL_##reg, \
					.pull_bit = bit, \
					.pull_val = status,

#define PU_PD_REG(reg, status)		.pu_pd_name = "PU_PD_SEL_"#reg, \
					.pu_pd_reg = PU_PD_SEL_##reg, \
					.pu_pd_val = status,

#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
					.mux_reg = OMAP7XX_IO_CONF_##reg, \
					.mask_offset = mode_offset, \
					.mask = mode,

#define PULL_REG_7XX(reg, bit, status)	.pull_name = "OMAP7XX_IO_CONF_"#reg, \
					.pull_reg = OMAP7XX_IO_CONF_##reg, \
					.pull_bit = bit, \
					.pull_val = status,

#else

#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
					.mask_offset = mode_offset, \
					.mask = mode,

#define PULL_REG(reg, bit, status)	.pull_reg = PULL_DWN_CTRL_##reg, \
					.pull_bit = bit, \
					.pull_val = status,

#define PU_PD_REG(reg, status)		.pu_pd_reg = PU_PD_SEL_##reg, \
					.pu_pd_val = status,

#define MUX_REG_7XX(reg, mode_offset, mode) \
					.mux_reg = OMAP7XX_IO_CONF_##reg, \
					.mask_offset = mode_offset, \
					.mask = mode,

#define PULL_REG_7XX(reg, bit, status)	.pull_reg = OMAP7XX_IO_CONF_##reg, \
					.pull_bit = bit, \
					.pull_val = status,

#endif /* CONFIG_OMAP_MUX_DEBUG */

#define MUX_CFG(desc, mux_reg, mode_offset, mode,	\
		pull_reg, pull_bit, pull_status,	\
		pu_pd_reg, pu_pd_status, debug_status)	\
{							\
	.name =	 desc,					\
	.debug = debug_status,				\
	MUX_REG(mux_reg, mode_offset, mode)		\
	PULL_REG(pull_reg, pull_bit, pull_status)	\
	PU_PD_REG(pu_pd_reg, pu_pd_status)		\
},


/*
 * OMAP730/850 has a slightly different config for the pin mux.
 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
 *   not the FUNC_MUX_CTRL_x regs from hardware.h
 * - for pull-up/down, only has one enable bit which is is in the same register
 *   as mux config
 */
#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,	\
		   pull_bit, pull_status, debug_status)\
{							\
	.name =	 desc,					\
	.debug = debug_status,				\
	MUX_REG_7XX(mux_reg, mode_offset, mode)		\
	PULL_REG_7XX(mux_reg, pull_bit, pull_status)	\
	PU_PD_REG(NA, 0)		\
},

#define MUX_CFG_24XX(desc, reg_offset, mode,			\
				pull_en, pull_mode, dbg)	\
{								\
	.name		= desc,					\
	.debug		= dbg,					\
	.mux_reg	= reg_offset,				\
	.mask		= mode,					\
	.pull_val	= pull_en,				\
	.pu_pd_val	= pull_mode,				\
},

/* 24xx/34xx mux bit defines */
#define OMAP2_PULL_ENA		(1 << 3)
#define OMAP2_PULL_UP		(1 << 4)
#define OMAP2_ALTELECTRICALSEL	(1 << 5)

struct pin_config {
	char 			*name;
	const unsigned int 	mux_reg;
	unsigned char		debug;

#if	defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
	const unsigned char mask_offset;
	const unsigned char mask;

	const char *pull_name;
	const unsigned int pull_reg;
	const unsigned char pull_val;
	const unsigned char pull_bit;

	const char *pu_pd_name;
	const unsigned int pu_pd_reg;
	const unsigned char pu_pd_val;
#endif

#if	defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
	const char *mux_reg_name;
#endif

};

enum omap7xx_index {
	/* OMAP 730 keyboard */
	E2_7XX_KBR0,
	J7_7XX_KBR1,
	E1_7XX_KBR2,
	F3_7XX_KBR3,
	D2_7XX_KBR4,
	C2_7XX_KBC0,
	D3_7XX_KBC1,
	E4_7XX_KBC2,
	F4_7XX_KBC3,
	E3_7XX_KBC4,

	/* USB */
	AA17_7XX_USB_DM,
	W16_7XX_USB_PU_EN,
	W17_7XX_USB_VBUSI,
	W18_7XX_USB_DMCK_OUT,
	W19_7XX_USB_DCRST,

	/* MMC */
	MMC_7XX_CMD,
	MMC_7XX_CLK,
	MMC_7XX_DAT0,
};

enum omap1xxx_index {
	/* UART1 (BT_UART_GATING)*/
	UART1_TX = 0,
	UART1_RTS,

	/* UART2 (COM_UART_GATING)*/
	UART2_TX,
	UART2_RX,
	UART2_CTS,
	UART2_RTS,

	/* UART3 (GIGA_UART_GATING) */
	UART3_TX,
	UART3_RX,
	UART3_CTS,
	UART3_RTS,
	UART3_CLKREQ,
	UART3_BCLK,	/* 12MHz clock out */
	Y15_1610_UART3_RTS,

	/* PWT & PWL */
	PWT,
	PWL,

	/* USB master generic */
	R18_USB_VBUS,
	R18_1510_USB_GPIO0,
	W4_USB_PUEN,
	W4_USB_CLKO,
	W4_USB_HIGHZ,
	W4_GPIO58,

	/* USB1 master */
	USB1_SUSP,
	USB1_SEO,
	W13_1610_USB1_SE0,
	USB1_TXEN,
	USB1_TXD,
	USB1_VP,
	USB1_VM,
	USB1_RCV,
	USB1_SPEED,
	R13_1610_USB1_SPEED,
	R13_1710_USB1_SE0,

	/* USB2 master */
	USB2_SUSP,
	USB2_VP,
	USB2_TXEN,
	USB2_VM,
	USB2_RCV,
	USB2_SEO,
	USB2_TXD,

	/* OMAP-1510 GPIO */
	R18_1510_GPIO0,
	R19_1510_GPIO1,
	M14_1510_GPIO2,

	/* OMAP1610 GPIO */
	P18_1610_GPIO3,
	Y15_1610_GPIO17,

	/* OMAP-1710 GPIO */
	R18_1710_GPIO0,
	V2_1710_GPIO10,
	N21_1710_GPIO14,
	W15_1710_GPIO40,

	/* MPUIO */
	MPUIO2,
	N15_1610_MPUIO2,
	MPUIO4,
	MPUIO5,
	T20_1610_MPUIO5,
	W11_1610_MPUIO6,
	V10_1610_MPUIO7,
	W11_1610_MPUIO9,
	V10_1610_MPUIO10,
	W10_1610_MPUIO11,
	E20_1610_MPUIO13,
	U20_1610_MPUIO14,
	E19_1610_MPUIO15,

	/* MCBSP2 */
	MCBSP2_CLKR,
	MCBSP2_CLKX,
	MCBSP2_DR,
	MCBSP2_DX,
	MCBSP2_FSR,
	MCBSP2_FSX,

	/* MCBSP3 */
	MCBSP3_CLKX,

	/* Misc ballouts */
	BALLOUT_V8_ARMIO3,
	N20_HDQ,

	/* OMAP-1610 MMC2 */
	W8_1610_MMC2_DAT0,
	V8_1610_MMC2_DAT1,
	W15_1610_MMC2_DAT2,
	R10_1610_MMC2_DAT3,
	Y10_1610_MMC2_CLK,
	Y8_1610_MMC2_CMD,
	V9_1610_MMC2_CMDDIR,
	V5_1610_MMC2_DATDIR0,
	W19_1610_MMC2_DATDIR1,
	R18_1610_MMC2_CLKIN,

	/* OMAP-1610 External Trace Interface */
	M19_1610_ETM_PSTAT0,
	L15_1610_ETM_PSTAT1,
	L18_1610_ETM_PSTAT2,
	L19_1610_ETM_D0,
	J19_1610_ETM_D6,
	J18_1610_ETM_D7,

	/* OMAP16XX GPIO */
	P20_1610_GPIO4,
	V9_1610_GPIO7,
	W8_1610_GPIO9,
	N20_1610_GPIO11,
	N19_1610_GPIO13,
	P10_1610_GPIO22,
	V5_1610_GPIO24,
	AA20_1610_GPIO_41,
	W19_1610_GPIO48,
	M7_1610_GPIO62,
	V14_16XX_GPIO37,
	R9_16XX_GPIO18,
	L14_16XX_GPIO49,

	/* OMAP-1610 uWire */
	V19_1610_UWIRE_SCLK,
	U18_1610_UWIRE_SDI,
	W21_1610_UWIRE_SDO,
	N14_1610_UWIRE_CS0,
	P15_1610_UWIRE_CS3,
	N15_1610_UWIRE_CS1,

	/* OMAP-1610 SPI */
	U19_1610_SPIF_SCK,
	U18_1610_SPIF_DIN,
	P20_1610_SPIF_DIN,
	W21_1610_SPIF_DOUT,
	R18_1610_SPIF_DOUT,
	N14_1610_SPIF_CS0,
	N15_1610_SPIF_CS1,
	T19_1610_SPIF_CS2,
	P15_1610_SPIF_CS3,

	/* OMAP-1610 Flash */
	L3_1610_FLASH_CS2B_OE,
	M8_1610_FLASH_CS2B_WE,

	/* First MMC */
	MMC_CMD,
	MMC_DAT1,
	MMC_DAT2,
	MMC_DAT0,
	MMC_CLK,
	MMC_DAT3,

	/* OMAP-1710 MMC CMDDIR and DATDIR0 */
	M15_1710_MMC_CLKI,
	P19_1710_MMC_CMDDIR,
	P20_1710_MMC_DATDIR0,

	/* OMAP-1610 USB0 alternate pin configuration */
	W9_USB0_TXEN,
	AA9_USB0_VP,
	Y5_USB0_RCV,
	R9_USB0_VM,
	V6_USB0_TXD,
	W5_USB0_SE0,
	V9_USB0_SPEED,
	V9_USB0_SUSP,

	/* USB2 */
	W9_USB2_TXEN,
	AA9_USB2_VP,
	Y5_USB2_RCV,
	R9_USB2_VM,
	V6_USB2_TXD,
	W5_USB2_SE0,

	/* 16XX UART */
	R13_1610_UART1_TX,
	V14_16XX_UART1_RX,
	R14_1610_UART1_CTS,
	AA15_1610_UART1_RTS,
	R9_16XX_UART2_RX,
	L14_16XX_UART3_RX,

	/* I2C OMAP-1610 */
	I2C_SCL,
	I2C_SDA,

	/* Keypad */
	F18_1610_KBC0,
	D20_1610_KBC1,
	D19_1610_KBC2,
	E18_1610_KBC3,
	C21_1610_KBC4,
	G18_1610_KBR0,
	F19_1610_KBR1,
	H14_1610_KBR2,
	E20_1610_KBR3,
	E19_1610_KBR4,
	N19_1610_KBR5,

	/* Power management */
	T20_1610_LOW_PWR,

	/* MCLK Settings */
	V5_1710_MCLK_ON,
	V5_1710_MCLK_OFF,
	R10_1610_MCLK_ON,
	R10_1610_MCLK_OFF,

	/* CompactFlash controller */
	P11_1610_CF_CD2,
	R11_1610_CF_IOIS16,
	V10_1610_CF_IREQ,
	W10_1610_CF_RESET,
	W11_1610_CF_CD1,

	/* parallel camera */
	J15_1610_CAM_LCLK,
	J18_1610_CAM_D7,
	J19_1610_CAM_D6,
	J14_1610_CAM_D5,
	K18_1610_CAM_D4,
	K19_1610_CAM_D3,
	K15_1610_CAM_D2,
	K14_1610_CAM_D1,
	L19_1610_CAM_D0,
	L18_1610_CAM_VS,
	L15_1610_CAM_HS,
	M19_1610_CAM_RSTZ,
	Y15_1610_CAM_OUTCLK,

	/* serial camera */
	H19_1610_CAM_EXCLK,
	Y12_1610_CCP_CLKP,
	W13_1610_CCP_CLKM,
	W14_1610_CCP_DATAP,
	Y14_1610_CCP_DATAM,

};

enum omap24xx_index {
	/* 24xx I2C */
	M19_24XX_I2C1_SCL,
	L15_24XX_I2C1_SDA,
	J15_24XX_I2C2_SCL,
	H19_24XX_I2C2_SDA,

	/* 24xx Menelaus interrupt */
	W19_24XX_SYS_NIRQ,

	/* 24xx clock */
	W14_24XX_SYS_CLKOUT,

	/* 24xx GPMC chipselects, wait pin monitoring */
	E2_GPMC_NCS2,
	L2_GPMC_NCS7,
	L3_GPMC_WAIT0,
	N7_GPMC_WAIT1,
	M1_GPMC_WAIT2,
	P1_GPMC_WAIT3,

	/* 242X McBSP */
	Y15_24XX_MCBSP2_CLKX,
	R14_24XX_MCBSP2_FSX,
	W15_24XX_MCBSP2_DR,
	V15_24XX_MCBSP2_DX,

	/* 24xx GPIO */
	M21_242X_GPIO11,
	P21_242X_GPIO12,
	AA10_242X_GPIO13,
	AA6_242X_GPIO14,
	AA4_242X_GPIO15,
	Y11_242X_GPIO16,
	AA12_242X_GPIO17,
	AA8_242X_GPIO58,
	Y20_24XX_GPIO60,
	W4__24XX_GPIO74,
	N15_24XX_GPIO85,
	M15_24XX_GPIO92,
	P20_24XX_GPIO93,
	P18_24XX_GPIO95,
	M18_24XX_GPIO96,
	L14_24XX_GPIO97,
	J15_24XX_GPIO99,
	V14_24XX_GPIO117,
	P14_24XX_GPIO125,

	/* 242x DBG GPIO */
	V4_242X_GPIO49,
	W2_242X_GPIO50,
	U4_242X_GPIO51,
	V3_242X_GPIO52,
	V2_242X_GPIO53,
	V6_242X_GPIO53,
	T4_242X_GPIO54,
	Y4_242X_GPIO54,
	T3_242X_GPIO55,
	U2_242X_GPIO56,

	/* 24xx external DMA requests */
	AA10_242X_DMAREQ0,
	AA6_242X_DMAREQ1,
	E4_242X_DMAREQ2,
	G4_242X_DMAREQ3,
	D3_242X_DMAREQ4,
	E3_242X_DMAREQ5,

	/* UART3 */
	K15_24XX_UART3_TX,
	K14_24XX_UART3_RX,

	/* MMC/SDIO */
	G19_24XX_MMC_CLKO,
	H18_24XX_MMC_CMD,
	F20_24XX_MMC_DAT0,
	H14_24XX_MMC_DAT1,
	E19_24XX_MMC_DAT2,
	D19_24XX_MMC_DAT3,
	F19_24XX_MMC_DAT_DIR0,
	E20_24XX_MMC_DAT_DIR1,
	F18_24XX_MMC_DAT_DIR2,
	E18_24XX_MMC_DAT_DIR3,
	G18_24XX_MMC_CMD_DIR,
	H15_24XX_MMC_CLKI,

	/* Full speed USB */
	J20_24XX_USB0_PUEN,
	J19_24XX_USB0_VP,
	K20_24XX_USB0_VM,
	J18_24XX_USB0_RCV,
	K19_24XX_USB0_TXEN,
	J14_24XX_USB0_SE0,
	K18_24XX_USB0_DAT,

	N14_24XX_USB1_SE0,
	W12_24XX_USB1_SE0,
	P15_24XX_USB1_DAT,
	R13_24XX_USB1_DAT,
	W20_24XX_USB1_TXEN,
	P13_24XX_USB1_TXEN,
	V19_24XX_USB1_RCV,
	V12_24XX_USB1_RCV,

	AA10_24XX_USB2_SE0,
	Y11_24XX_USB2_DAT,
	AA12_24XX_USB2_TXEN,
	AA6_24XX_USB2_RCV,
	AA4_24XX_USB2_TLLSE0,

	/* Keypad GPIO*/
	T19_24XX_KBR0,
	R19_24XX_KBR1,
	V18_24XX_KBR2,
	M21_24XX_KBR3,
	E5__24XX_KBR4,
	M18_24XX_KBR5,
	R20_24XX_KBC0,
	M14_24XX_KBC1,
	H19_24XX_KBC2,
	V17_24XX_KBC3,
	P21_24XX_KBC4,
	L14_24XX_KBC5,
	N19_24XX_KBC6,

	/* 24xx Menelaus Keypad GPIO */
	B3__24XX_KBR5,
	AA4_24XX_KBC2,
	B13_24XX_KBC6,

	/* 2430 USB */
	AD9_2430_USB0_PUEN,
	Y11_2430_USB0_VP,
	AD7_2430_USB0_VM,
	AE7_2430_USB0_RCV,
	AD4_2430_USB0_TXEN,
	AF9_2430_USB0_SE0,
	AE6_2430_USB0_DAT,
	AD24_2430_USB1_SE0,
	AB24_2430_USB1_RCV,
	Y25_2430_USB1_TXEN,
	AA26_2430_USB1_DAT,

	/* 2430 HS-USB */
	AD9_2430_USB0HS_DATA3,
	Y11_2430_USB0HS_DATA4,
	AD7_2430_USB0HS_DATA5,
	AE7_2430_USB0HS_DATA6,
	AD4_2430_USB0HS_DATA2,
	AF9_2430_USB0HS_DATA0,
	AE6_2430_USB0HS_DATA1,
	AE8_2430_USB0HS_CLK,
	AD8_2430_USB0HS_DIR,
	AE5_2430_USB0HS_STP,
	AE9_2430_USB0HS_NXT,
	AC7_2430_USB0HS_DATA7,

	/* 2430 McBSP */
	AD6_2430_MCBSP_CLKS,

	AB2_2430_MCBSP1_CLKR,
	AD5_2430_MCBSP1_FSR,
	AA1_2430_MCBSP1_DX,
	AF3_2430_MCBSP1_DR,
	AB3_2430_MCBSP1_FSX,
	Y9_2430_MCBSP1_CLKX,

	AC10_2430_MCBSP2_FSX,
	AD16_2430_MCBSP2_CLX,
	AE13_2430_MCBSP2_DX,
	AD13_2430_MCBSP2_DR,
	AC10_2430_MCBSP2_FSX_OFF,
	AD16_2430_MCBSP2_CLX_OFF,
	AE13_2430_MCBSP2_DX_OFF,
	AD13_2430_MCBSP2_DR_OFF,

	AC9_2430_MCBSP3_CLKX,
	AE4_2430_MCBSP3_FSX,
	AE2_2430_MCBSP3_DR,
	AF4_2430_MCBSP3_DX,

	N3_2430_MCBSP4_CLKX,
	AD23_2430_MCBSP4_DR,
	AB25_2430_MCBSP4_DX,
	AC25_2430_MCBSP4_FSX,

	AE16_2430_MCBSP5_CLKX,
	AF12_2430_MCBSP5_FSX,
	K7_2430_MCBSP5_DX,
	M1_2430_MCBSP5_DR,

	/* 2430 McSPI*/
	Y18_2430_MCSPI1_CLK,
	AD15_2430_MCSPI1_SIMO,
	AE17_2430_MCSPI1_SOMI,
	U1_2430_MCSPI1_CS0,

	/* Touchscreen GPIO */
	AF19_2430_GPIO_85,

};

struct omap_mux_cfg {
	struct pin_config	*pins;
	unsigned long		size;
	int			(*cfg_reg)(const struct pin_config *cfg);
};

#ifdef	CONFIG_OMAP_MUX
/* setup pin muxing in Linux */
extern int omap1_mux_init(void);
extern int omap_mux_register(struct omap_mux_cfg *);
extern int omap_cfg_reg(unsigned long reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
static inline int omap1_mux_init(void) { return 0; }
static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
#endif

extern int omap2_mux_init(void);

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/mux.h
1da177e4 LT	3	*
	4	* Table of the Omap register configurations for the FUNC_MUX and
	5	* PULL_DWN combinations.
	6	*
9330899e TL	7	* Copyright (C) 2004 - 2008 Texas Instruments Inc.
9330899e TL	8	* Copyright (C) 2003 - 2008 Nokia Corporation
1da177e4	9	*
9330899e	10	* Written by Tony Lindgren
1da177e4 LT	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2 of the License, or
	15	* (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	25	*
	26	* NOTE: Please use the following naming style for new pin entries.
	27	* For example, W8_1610_MMC2_DAT0, where:
	28	* - W8 = ball
	29	* - 1610 = 1510 or 1610, none if common for both 1510 and 1610
	30	* - MMC2_DAT0 = function
1da177e4 LT	31	*/
	32
	33	#ifndef __ASM_ARCH_MUX_H
	34	#define __ASM_ARCH_MUX_H
	35
	36	#define PU_PD_SEL_NA 0 /* No pu_pd reg available */
	37	#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
	38
	39	#ifdef CONFIG_OMAP_MUX_DEBUG
	40	#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
	41	.mux_reg = FUNC_MUX_CTRL_##reg, \
	42	.mask_offset = mode_offset, \
	43	.mask = mode,
	44
	45	#define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
	46	.pull_reg = PULL_DWN_CTRL_##reg, \
	47	.pull_bit = bit, \
	48	.pull_val = status,
	49
	50	#define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
	51	.pu_pd_reg = PU_PD_SEL_##reg, \
	52	.pu_pd_val = status,
	53
7c006926	54	#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
b51988db	55	.mux_reg = OMAP7XX_IO_CONF_##reg, \
9ad5897c TL	56	.mask_offset = mode_offset, \
	57	.mask = mode,
	58
7c006926	59	#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
b51988db	60	.pull_reg = OMAP7XX_IO_CONF_##reg, \
9ad5897c TL	61	.pull_bit = bit, \
	62	.pull_val = status,
	63
1da177e4 LT	64	#else
	65
	66	#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
	67	.mask_offset = mode_offset, \
	68	.mask = mode,
	69
	70	#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
	71	.pull_bit = bit, \
	72	.pull_val = status,
	73
	74	#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
	75	.pu_pd_val = status,
	76
7c006926	77	#define MUX_REG_7XX(reg, mode_offset, mode) \
b51988db	78	.mux_reg = OMAP7XX_IO_CONF_##reg, \
9ad5897c TL	79	.mask_offset = mode_offset, \
	80	.mask = mode,
	81
7c006926	82	#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
9ad5897c TL	83	.pull_bit = bit, \
	84	.pull_val = status,
	85
1da177e4 LT	86	#endif /* CONFIG_OMAP_MUX_DEBUG */
	87
	88	#define MUX_CFG(desc, mux_reg, mode_offset, mode, \
	89	pull_reg, pull_bit, pull_status, \
	90	pu_pd_reg, pu_pd_status, debug_status) \
	91	{ \
	92	.name = desc, \
	93	.debug = debug_status, \
	94	MUX_REG(mux_reg, mode_offset, mode) \
	95	PULL_REG(pull_reg, pull_bit, pull_status) \
	96	PU_PD_REG(pu_pd_reg, pu_pd_status) \
	97	},
	98
9ad5897c TL	99
9ad5897c TL	100	/*
56739a69	101	* OMAP730/850 has a slightly different config for the pin mux.
b51988db	102	* - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
9ad5897c TL	103	* not the FUNC_MUX_CTRL_x regs from hardware.h
	104	* - for pull-up/down, only has one enable bit which is is in the same register
	105	* as mux config
	106	*/
7c006926	107	#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
8d7f9f50	108	pull_bit, pull_status, debug_status)\
9ad5897c TL	109	{ \
	110	.name = desc, \
	111	.debug = debug_status, \
7c006926 AB	112	MUX_REG_7XX(mux_reg, mode_offset, mode) \
7c006926 AB	113	PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
8d7f9f50	114	PU_PD_REG(NA, 0) \
9ad5897c TL	115	},
	116
	117	#define MUX_CFG_24XX(desc, reg_offset, mode, \
	118	pull_en, pull_mode, dbg) \
	119	{ \
	120	.name = desc, \
	121	.debug = dbg, \
	122	.mux_reg = reg_offset, \
	123	.mask = mode, \
	124	.pull_val = pull_en, \
	125	.pu_pd_val = pull_mode, \
	126	},
	127
2351872c VP	128	/* 24xx/34xx mux bit defines */
	129	#define OMAP2_PULL_ENA (1 << 3)
	130	#define OMAP2_PULL_UP (1 << 4)
	131	#define OMAP2_ALTELECTRICALSEL (1 << 5)
	132
9ad5897c	133	struct pin_config {
2351872c VP	134	char *name;
	135	const unsigned int mux_reg;
	136	unsigned char debug;
1da177e4	137
2351872c	138	#if defined(CONFIG_ARCH_OMAP1) \|\| defined(CONFIG_ARCH_OMAP24XX)
1da177e4 LT	139	const unsigned char mask_offset;
	140	const unsigned char mask;
	141
	142	const char *pull_name;
	143	const unsigned int pull_reg;
	144	const unsigned char pull_val;
	145	const unsigned char pull_bit;
	146
	147	const char *pu_pd_name;
	148	const unsigned int pu_pd_reg;
	149	const unsigned char pu_pd_val;
2351872c VP	150	#endif
	151
	152	#if defined(CONFIG_OMAP_MUX_DEBUG) \|\| defined(CONFIG_OMAP_MUX_WARNINGS)
	153	const char *mux_reg_name;
	154	#endif
	155
9ad5897c	156	};
1da177e4	157
7c006926	158	enum omap7xx_index {
9ad5897c	159	/* OMAP 730 keyboard */
7c006926 AB	160	E2_7XX_KBR0,
	161	J7_7XX_KBR1,
	162	E1_7XX_KBR2,
	163	F3_7XX_KBR3,
	164	D2_7XX_KBR4,
	165	C2_7XX_KBC0,
	166	D3_7XX_KBC1,
	167	E4_7XX_KBC2,
	168	F4_7XX_KBC3,
	169	E3_7XX_KBC4,
8d7f9f50 TL	170
8d7f9f50 TL	171	/* USB */
7c006926 AB	172	AA17_7XX_USB_DM,
	173	W16_7XX_USB_PU_EN,
	174	W17_7XX_USB_VBUSI,
106997c1 CM	175	W18_7XX_USB_DMCK_OUT,
106997c1 CM	176	W19_7XX_USB_DCRST,
490a5665 CM	177
	178	/* MMC */
	179	MMC_7XX_CMD,
	180	MMC_7XX_CLK,
	181	MMC_7XX_DAT0,
9ad5897c TL	182	};
	183
	184	enum omap1xxx_index {
1da177e4 LT	185	/* UART1 (BT_UART_GATING)*/
	186	UART1_TX = 0,
	187	UART1_RTS,
	188
	189	/* UART2 (COM_UART_GATING)*/
	190	UART2_TX,
	191	UART2_RX,
	192	UART2_CTS,
	193	UART2_RTS,
	194
	195	/* UART3 (GIGA_UART_GATING) */
	196	UART3_TX,
	197	UART3_RX,
	198	UART3_CTS,
	199	UART3_RTS,
	200	UART3_CLKREQ,
	201	UART3_BCLK, /* 12MHz clock out */
	202	Y15_1610_UART3_RTS,
	203
	204	/* PWT & PWL */
	205	PWT,
	206	PWL,
	207
	208	/* USB master generic */
	209	R18_USB_VBUS,
	210	R18_1510_USB_GPIO0,
	211	W4_USB_PUEN,
	212	W4_USB_CLKO,
	213	W4_USB_HIGHZ,
	214	W4_GPIO58,
	215
	216	/* USB1 master */
	217	USB1_SUSP,
	218	USB1_SEO,
	219	W13_1610_USB1_SE0,
	220	USB1_TXEN,
	221	USB1_TXD,
	222	USB1_VP,
	223	USB1_VM,
	224	USB1_RCV,
	225	USB1_SPEED,
	226	R13_1610_USB1_SPEED,
	227	R13_1710_USB1_SE0,
	228
	229	/* USB2 master */
	230	USB2_SUSP,
	231	USB2_VP,
	232	USB2_TXEN,
	233	USB2_VM,
	234	USB2_RCV,
	235	USB2_SEO,
	236	USB2_TXD,
	237
	238	/* OMAP-1510 GPIO */
	239	R18_1510_GPIO0,
	240	R19_1510_GPIO1,
	241	M14_1510_GPIO2,
	242
	243	/* OMAP1610 GPIO */
	244	P18_1610_GPIO3,
	245	Y15_1610_GPIO17,
	246
	247	/* OMAP-1710 GPIO */
	248	R18_1710_GPIO0,
249	V2_1710_GPIO10,
250	N21_1710_GPIO14,
251	W15_1710_GPIO40,
252
253	/* MPUIO */
254	MPUIO2,
9839c6b8	255	N15_1610_MPUIO2,
1da177e4 LT	256	MPUIO4,
	257	MPUIO5,
	258	T20_1610_MPUIO5,
	259	W11_1610_MPUIO6,
	260	V10_1610_MPUIO7,
	261	W11_1610_MPUIO9,
	262	V10_1610_MPUIO10,
	263	W10_1610_MPUIO11,
	264	E20_1610_MPUIO13,
	265	U20_1610_MPUIO14,
	266	E19_1610_MPUIO15,
	267
	268	/* MCBSP2 */
	269	MCBSP2_CLKR,
	270	MCBSP2_CLKX,
	271	MCBSP2_DR,
	272	MCBSP2_DX,
	273	MCBSP2_FSR,
	274	MCBSP2_FSX,
	275
	276	/* MCBSP3 */
	277	MCBSP3_CLKX,
	278
	279	/* Misc ballouts */
	280	BALLOUT_V8_ARMIO3,
9839c6b8	281	N20_HDQ,
1da177e4 LT	282
	283	/* OMAP-1610 MMC2 */
	284	W8_1610_MMC2_DAT0,
	285	V8_1610_MMC2_DAT1,
	286	W15_1610_MMC2_DAT2,
	287	R10_1610_MMC2_DAT3,
	288	Y10_1610_MMC2_CLK,
	289	Y8_1610_MMC2_CMD,
	290	V9_1610_MMC2_CMDDIR,
	291	V5_1610_MMC2_DATDIR0,
	292	W19_1610_MMC2_DATDIR1,
	293	R18_1610_MMC2_CLKIN,
	294
	295	/* OMAP-1610 External Trace Interface */
	296	M19_1610_ETM_PSTAT0,
	297	L15_1610_ETM_PSTAT1,
	298	L18_1610_ETM_PSTAT2,
	299	L19_1610_ETM_D0,
	300	J19_1610_ETM_D6,
	301	J18_1610_ETM_D7,
	302
bb13b5fd	303	/* OMAP16XX GPIO */
1da177e4 LT	304	P20_1610_GPIO4,
	305	V9_1610_GPIO7,
	306	W8_1610_GPIO9,
9839c6b8	307	N20_1610_GPIO11,
1da177e4 LT	308	N19_1610_GPIO13,
	309	P10_1610_GPIO22,
	310	V5_1610_GPIO24,
	311	AA20_1610_GPIO_41,
	312	W19_1610_GPIO48,
	313	M7_1610_GPIO62,
bb13b5fd TL	314	V14_16XX_GPIO37,
	315	R9_16XX_GPIO18,
	316	L14_16XX_GPIO49,
1da177e4 LT	317
	318	/* OMAP-1610 uWire */
	319	V19_1610_UWIRE_SCLK,
	320	U18_1610_UWIRE_SDI,
	321	W21_1610_UWIRE_SDO,
	322	N14_1610_UWIRE_CS0,
9839c6b8	323	P15_1610_UWIRE_CS3,
1da177e4 LT	324	N15_1610_UWIRE_CS1,
1da177e4 LT	325
75a1d10e MH	326	/* OMAP-1610 SPI */
	327	U19_1610_SPIF_SCK,
	328	U18_1610_SPIF_DIN,
	329	P20_1610_SPIF_DIN,
	330	W21_1610_SPIF_DOUT,
	331	R18_1610_SPIF_DOUT,
	332	N14_1610_SPIF_CS0,
	333	N15_1610_SPIF_CS1,
	334	T19_1610_SPIF_CS2,
	335	P15_1610_SPIF_CS3,
	336
1da177e4 LT	337	/* OMAP-1610 Flash */
	338	L3_1610_FLASH_CS2B_OE,
	339	M8_1610_FLASH_CS2B_WE,
	340
	341	/* First MMC */
	342	MMC_CMD,
	343	MMC_DAT1,
	344	MMC_DAT2,
	345	MMC_DAT0,
	346	MMC_CLK,
	347	MMC_DAT3,
	348
	349	/* OMAP-1710 MMC CMDDIR and DATDIR0 */
	350	M15_1710_MMC_CLKI,
	351	P19_1710_MMC_CMDDIR,
	352	P20_1710_MMC_DATDIR0,
	353
	354	/* OMAP-1610 USB0 alternate pin configuration */
	355	W9_USB0_TXEN,
	356	AA9_USB0_VP,
	357	Y5_USB0_RCV,
	358	R9_USB0_VM,
	359	V6_USB0_TXD,
	360	W5_USB0_SE0,
	361	V9_USB0_SPEED,
	362	V9_USB0_SUSP,
	363
	364	/* USB2 */
	365	W9_USB2_TXEN,
	366	AA9_USB2_VP,
	367	Y5_USB2_RCV,
	368	R9_USB2_VM,
	369	V6_USB2_TXD,
	370	W5_USB2_SE0,
	371
bb13b5fd	372	/* 16XX UART */
1da177e4	373	R13_1610_UART1_TX,
bb13b5fd	374	V14_16XX_UART1_RX,
1da177e4 LT	375	R14_1610_UART1_CTS,
1da177e4 LT	376	AA15_1610_UART1_RTS,
bb13b5fd TL	377	R9_16XX_UART2_RX,
bb13b5fd TL	378	L14_16XX_UART3_RX,
1da177e4 LT	379
	380	/* I2C OMAP-1610 */
	381	I2C_SCL,
	382	I2C_SDA,
	383
	384	/* Keypad */
	385	F18_1610_KBC0,
	386	D20_1610_KBC1,
	387	D19_1610_KBC2,
	388	E18_1610_KBC3,
	389	C21_1610_KBC4,
	390	G18_1610_KBR0,
	391	F19_1610_KBR1,
	392	H14_1610_KBR2,
	393	E20_1610_KBR3,
	394	E19_1610_KBR4,
	395	N19_1610_KBR5,
	396
	397	/* Power management */
	398	T20_1610_LOW_PWR,
	399
	400	/* MCLK Settings */
	401	V5_1710_MCLK_ON,
	402	V5_1710_MCLK_OFF,
	403	R10_1610_MCLK_ON,
	404	R10_1610_MCLK_OFF,
	405
	406	/* CompactFlash controller */
	407	P11_1610_CF_CD2,
	408	R11_1610_CF_IOIS16,
	409	V10_1610_CF_IREQ,
	410	W10_1610_CF_RESET,
	411	W11_1610_CF_CD1,
c72d8950 DB	412
	413	/* parallel camera */
	414	J15_1610_CAM_LCLK,
	415	J18_1610_CAM_D7,
	416	J19_1610_CAM_D6,
	417	J14_1610_CAM_D5,
	418	K18_1610_CAM_D4,
	419	K19_1610_CAM_D3,
	420	K15_1610_CAM_D2,
	421	K14_1610_CAM_D1,
	422	L19_1610_CAM_D0,
	423	L18_1610_CAM_VS,
	424	L15_1610_CAM_HS,
	425	M19_1610_CAM_RSTZ,
	426	Y15_1610_CAM_OUTCLK,
	427
	428	/* serial camera */
	429	H19_1610_CAM_EXCLK,
	430	Y12_1610_CCP_CLKP,
	431	W13_1610_CCP_CLKM,
	432	W14_1610_CCP_DATAP,
	433	Y14_1610_CCP_DATAM,
	434
9ad5897c	435	};
1da177e4	436
9ad5897c TL	437	enum omap24xx_index {
	438	/* 24xx I2C */
	439	M19_24XX_I2C1_SCL,
	440	L15_24XX_I2C1_SDA,
	441	J15_24XX_I2C2_SCL,
	442	H19_24XX_I2C2_SDA,
1da177e4	443
9ad5897c TL	444	/* 24xx Menelaus interrupt */
9ad5897c TL	445	W19_24XX_SYS_NIRQ,
1da177e4	446
8d7f9f50 TL	447	/* 24xx clock */
	448	W14_24XX_SYS_CLKOUT,
	449
7bbb3cc5 KP	450	/* 24xx GPMC chipselects, wait pin monitoring */
	451	E2_GPMC_NCS2,
	452	L2_GPMC_NCS7,
3cbc9605 TL	453	L3_GPMC_WAIT0,
	454	N7_GPMC_WAIT1,
	455	M1_GPMC_WAIT2,
	456	P1_GPMC_WAIT3,
	457
8d7f9f50 TL	458	/* 242X McBSP */
	459	Y15_24XX_MCBSP2_CLKX,
	460	R14_24XX_MCBSP2_FSX,
	461	W15_24XX_MCBSP2_DR,
	462	V15_24XX_MCBSP2_DX,
	463
9ad5897c	464	/* 24xx GPIO */
8d7f9f50	465	M21_242X_GPIO11,
7bbb3cc5	466	P21_242X_GPIO12,
8d7f9f50 TL	467	AA10_242X_GPIO13,
	468	AA6_242X_GPIO14,
	469	AA4_242X_GPIO15,
	470	Y11_242X_GPIO16,
	471	AA12_242X_GPIO17,
	472	AA8_242X_GPIO58,
9ad5897c	473	Y20_24XX_GPIO60,
8d7f9f50	474	W4__24XX_GPIO74,
f7337a19	475	N15_24XX_GPIO85,
9ad5897c	476	M15_24XX_GPIO92,
f7337a19 TL	477	P20_24XX_GPIO93,
	478	P18_24XX_GPIO95,
	479	M18_24XX_GPIO96,
	480	L14_24XX_GPIO97,
7bbb3cc5	481	J15_24XX_GPIO99,
8d7f9f50	482	V14_24XX_GPIO117,
7bbb3cc5	483	P14_24XX_GPIO125,
8d7f9f50	484
5ac42153 TL	485	/* 242x DBG GPIO */
	486	V4_242X_GPIO49,
	487	W2_242X_GPIO50,
	488	U4_242X_GPIO51,
	489	V3_242X_GPIO52,
	490	V2_242X_GPIO53,
	491	V6_242X_GPIO53,
	492	T4_242X_GPIO54,
	493	Y4_242X_GPIO54,
	494	T3_242X_GPIO55,
	495	U2_242X_GPIO56,
	496
	497	/* 24xx external DMA requests */
	498	AA10_242X_DMAREQ0,
	499	AA6_242X_DMAREQ1,
	500	E4_242X_DMAREQ2,
	501	G4_242X_DMAREQ3,
	502	D3_242X_DMAREQ4,
	503	E3_242X_DMAREQ5,
	504
8d7f9f50 TL	505	/* UART3 */
	506	K15_24XX_UART3_TX,
	507	K14_24XX_UART3_RX,
	508
abc45e1d KP	509	/* MMC/SDIO */
	510	G19_24XX_MMC_CLKO,
	511	H18_24XX_MMC_CMD,
	512	F20_24XX_MMC_DAT0,
	513	H14_24XX_MMC_DAT1,
	514	E19_24XX_MMC_DAT2,
	515	D19_24XX_MMC_DAT3,
	516	F19_24XX_MMC_DAT_DIR0,
	517	E20_24XX_MMC_DAT_DIR1,
	518	F18_24XX_MMC_DAT_DIR2,
	519	E18_24XX_MMC_DAT_DIR3,
	520	G18_24XX_MMC_CMD_DIR,
	521	H15_24XX_MMC_CLKI,
	522
7bbb3cc5 KP	523	/* Full speed USB */
	524	J20_24XX_USB0_PUEN,
	525	J19_24XX_USB0_VP,
	526	K20_24XX_USB0_VM,
	527	J18_24XX_USB0_RCV,
	528	K19_24XX_USB0_TXEN,
	529	J14_24XX_USB0_SE0,
	530	K18_24XX_USB0_DAT,
	531
	532	N14_24XX_USB1_SE0,
	533	W12_24XX_USB1_SE0,
	534	P15_24XX_USB1_DAT,
	535	R13_24XX_USB1_DAT,
	536	W20_24XX_USB1_TXEN,
	537	P13_24XX_USB1_TXEN,
	538	V19_24XX_USB1_RCV,
	539	V12_24XX_USB1_RCV,
	540
	541	AA10_24XX_USB2_SE0,
	542	Y11_24XX_USB2_DAT,
	543	AA12_24XX_USB2_TXEN,
	544	AA6_24XX_USB2_RCV,
	545	AA4_24XX_USB2_TLLSE0,
	546
8d7f9f50 TL	547	/* Keypad GPIO*/
	548	T19_24XX_KBR0,
	549	R19_24XX_KBR1,
	550	V18_24XX_KBR2,
	551	M21_24XX_KBR3,
	552	E5__24XX_KBR4,
	553	M18_24XX_KBR5,
	554	R20_24XX_KBC0,
	555	M14_24XX_KBC1,
	556	H19_24XX_KBC2,
	557	V17_24XX_KBC3,
	558	P21_24XX_KBC4,
	559	L14_24XX_KBC5,
	560	N19_24XX_KBC6,
	561
	562	/* 24xx Menelaus Keypad GPIO */
	563	B3__24XX_KBR5,
	564	AA4_24XX_KBC2,
	565	B13_24XX_KBC6,
f7337a19 TL	566
	567	/* 2430 USB */
	568	AD9_2430_USB0_PUEN,
	569	Y11_2430_USB0_VP,
	570	AD7_2430_USB0_VM,
	571	AE7_2430_USB0_RCV,
	572	AD4_2430_USB0_TXEN,
	573	AF9_2430_USB0_SE0,
	574	AE6_2430_USB0_DAT,
	575	AD24_2430_USB1_SE0,
	576	AB24_2430_USB1_RCV,
	577	Y25_2430_USB1_TXEN,
	578	AA26_2430_USB1_DAT,
	579
	580	/* 2430 HS-USB */
	581	AD9_2430_USB0HS_DATA3,
	582	Y11_2430_USB0HS_DATA4,
	583	AD7_2430_USB0HS_DATA5,
	584	AE7_2430_USB0HS_DATA6,
	585	AD4_2430_USB0HS_DATA2,
	586	AF9_2430_USB0HS_DATA0,
	587	AE6_2430_USB0HS_DATA1,
	588	AE8_2430_USB0HS_CLK,
	589	AD8_2430_USB0HS_DIR,
	590	AE5_2430_USB0HS_STP,
	591	AE9_2430_USB0HS_NXT,
	592	AC7_2430_USB0HS_DATA7,
	593
	594	/* 2430 McBSP */
2619bc32 AK	595	AD6_2430_MCBSP_CLKS,
	596
	597	AB2_2430_MCBSP1_CLKR,
	598	AD5_2430_MCBSP1_FSR,
	599	AA1_2430_MCBSP1_DX,
	600	AF3_2430_MCBSP1_DR,
	601	AB3_2430_MCBSP1_FSX,
	602	Y9_2430_MCBSP1_CLKX,
	603
f7337a19 TL	604	AC10_2430_MCBSP2_FSX,
	605	AD16_2430_MCBSP2_CLX,
	606	AE13_2430_MCBSP2_DX,
	607	AD13_2430_MCBSP2_DR,
	608	AC10_2430_MCBSP2_FSX_OFF,
	609	AD16_2430_MCBSP2_CLX_OFF,
	610	AE13_2430_MCBSP2_DX_OFF,
	611	AD13_2430_MCBSP2_DR_OFF,
	612
2619bc32 AK	613	AC9_2430_MCBSP3_CLKX,
	614	AE4_2430_MCBSP3_FSX,
	615	AE2_2430_MCBSP3_DR,
	616	AF4_2430_MCBSP3_DX,
	617
	618	N3_2430_MCBSP4_CLKX,
	619	AD23_2430_MCBSP4_DR,
	620	AB25_2430_MCBSP4_DX,
	621	AC25_2430_MCBSP4_FSX,
	622
	623	AE16_2430_MCBSP5_CLKX,
	624	AF12_2430_MCBSP5_FSX,
	625	K7_2430_MCBSP5_DX,
	626	M1_2430_MCBSP5_DR,
	627
	628	/* 2430 McSPI*/
	629	Y18_2430_MCSPI1_CLK,
	630	AD15_2430_MCSPI1_SIMO,
	631	AE17_2430_MCSPI1_SOMI,
	632	U1_2430_MCSPI1_CS0,
	633
	634	/* Touchscreen GPIO */
	635	AF19_2430_GPIO_85,
	636
9ad5897c	637	};
1da177e4	638
7d7f665d TL	639	struct omap_mux_cfg {
	640	struct pin_config *pins;
	641	unsigned long size;
	642	int (cfg_reg)(const struct pin_config cfg);
	643	};
	644
1da177e4 LT	645	#ifdef CONFIG_OMAP_MUX
1da177e4 LT	646	/* setup pin muxing in Linux */
9ad5897c	647	extern int omap1_mux_init(void);
7d7f665d	648	extern int omap_mux_register(struct omap_mux_cfg *);
9ad5897c	649	extern int omap_cfg_reg(unsigned long reg_cfg);
1da177e4 LT	650	#else
1da177e4 LT	651	/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
9ad5897c	652	static inline int omap1_mux_init(void) { return 0; }
9ad5897c	653	static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
1da177e4 LT	654	#endif
1da177e4 LT	655
15f45e6f TL	656	extern int omap2_mux_init(void);
15f45e6f TL	657
1da177e4	658	#endif