[net-next-2.6.git] / arch / arm / oprofile / op_model_arm11_core.h

/**
 * @file op_model_arm11_core.h
 * ARM11 Event Monitor Driver
 * @remark Copyright 2004 ARM SMP Development Team
 * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
 * @remark Copyright 2000-2004 MontaVista Software Inc
 * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
 * @remark Copyright 2004 Intel Corporation
 * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
 * @remark Copyright 2004 Oprofile Authors
 *
 * @remark Read the file COPYING
 *
 * @author Zwane Mwaikambo
 */
#ifndef OP_MODEL_ARM11_CORE_H
#define OP_MODEL_ARM11_CORE_H

/*
 * Per-CPU PMCR
 */
#define PMCR_E		(1 << 0)	/* Enable */
#define PMCR_P		(1 << 1)	/* Count reset */
#define PMCR_C		(1 << 2)	/* Cycle counter reset */
#define PMCR_D		(1 << 3)	/* Cycle counter counts every 64th cpu cycle */
#define PMCR_IEN_PMN0	(1 << 4)	/* Interrupt enable count reg 0 */
#define PMCR_IEN_PMN1	(1 << 5)	/* Interrupt enable count reg 1 */
#define PMCR_IEN_CCNT	(1 << 6)	/* Interrupt enable cycle counter */
#define PMCR_OFL_PMN0	(1 << 8)	/* Count reg 0 overflow */
#define PMCR_OFL_PMN1	(1 << 9)	/* Count reg 1 overflow */
#define PMCR_OFL_CCNT	(1 << 10)	/* Cycle counter overflow */

#define PMN0 0
#define PMN1 1
#define CCNT 2

#define CPU_COUNTER(cpu, counter)	((cpu) * 3 + (counter))

int arm11_setup_pmu(void);
int arm11_start_pmu(void);
int arm11_stop_pmu(void);
int arm11_request_interrupts(const int *, int);
void arm11_release_interrupts(const int *, int);

#endif
Commit	Line	Data
c265a762 RK	1	/**
	2	* @file op_model_arm11_core.h
	3	* ARM11 Event Monitor Driver
	4	* @remark Copyright 2004 ARM SMP Development Team
	5	* @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
	6	* @remark Copyright 2000-2004 MontaVista Software Inc
	7	* @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
	8	* @remark Copyright 2004 Intel Corporation
	9	* @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
	10	* @remark Copyright 2004 Oprofile Authors
	11	*
	12	* @remark Read the file COPYING
	13	*
	14	* @author Zwane Mwaikambo
	15	*/
	16	#ifndef OP_MODEL_ARM11_CORE_H
	17	#define OP_MODEL_ARM11_CORE_H
	18
	19	/*
	20	* Per-CPU PMCR
	21	*/
	22	#define PMCR_E (1 << 0) /* Enable */
	23	#define PMCR_P (1 << 1) /* Count reset */
	24	#define PMCR_C (1 << 2) /* Cycle counter reset */
	25	#define PMCR_D (1 << 3) /* Cycle counter counts every 64th cpu cycle */
	26	#define PMCR_IEN_PMN0 (1 << 4) /* Interrupt enable count reg 0 */
	27	#define PMCR_IEN_PMN1 (1 << 5) /* Interrupt enable count reg 1 */
	28	#define PMCR_IEN_CCNT (1 << 6) /* Interrupt enable cycle counter */
	29	#define PMCR_OFL_PMN0 (1 << 8) /* Count reg 0 overflow */
	30	#define PMCR_OFL_PMN1 (1 << 9) /* Count reg 1 overflow */
	31	#define PMCR_OFL_CCNT (1 << 10) /* Cycle counter overflow */
	32
	33	#define PMN0 0
	34	#define PMN1 1
	35	#define CCNT 2
	36
	37	#define CPU_COUNTER(cpu, counter) ((cpu) * 3 + (counter))
	38
	39	int arm11_setup_pmu(void);
	40	int arm11_start_pmu(void);
	41	int arm11_stop_pmu(void);
1618fdd9 JI	42	int arm11_request_interrupts(const int *, int);
1618fdd9 JI	43	void arm11_release_interrupts(const int *, int);
c265a762 RK	44
c265a762 RK	45	#endif