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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-v6.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
d090ddda | 5 | * Modified by Catalin Marinas for noMMU support |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This is the "shell" of the ARMv6 processor support. | |
12 | */ | |
991da17e | 13 | #include <linux/init.h> |
1da177e4 LT |
14 | #include <linux/linkage.h> |
15 | #include <asm/assembler.h> | |
e6ae744d | 16 | #include <asm/asm-offsets.h> |
5ec9407d | 17 | #include <asm/hwcap.h> |
74945c86 | 18 | #include <asm/pgtable-hwdef.h> |
1da177e4 LT |
19 | #include <asm/pgtable.h> |
20 | ||
21 | #include "proc-macros.S" | |
22 | ||
23 | #define D_CACHE_LINE_SIZE 32 | |
24 | ||
3747b36e RK |
25 | #define TTB_C (1 << 0) |
26 | #define TTB_S (1 << 1) | |
27 | #define TTB_IMP (1 << 2) | |
28 | #define TTB_RGN_NC (0 << 3) | |
29 | #define TTB_RGN_WBWA (1 << 3) | |
30 | #define TTB_RGN_WT (2 << 3) | |
31 | #define TTB_RGN_WB (3 << 3) | |
32 | ||
f00ec48f RK |
33 | #define TTB_FLAGS_UP TTB_RGN_WBWA |
34 | #define PMD_FLAGS_UP PMD_SECT_WB | |
35 | #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S | |
36 | #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S | |
f2131d34 | 37 | |
1da177e4 LT |
38 | ENTRY(cpu_v6_proc_init) |
39 | mov pc, lr | |
40 | ||
41 | ENTRY(cpu_v6_proc_fin) | |
67c5587a TL |
42 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
43 | bic r0, r0, #0x1000 @ ...i............ | |
44 | bic r0, r0, #0x0006 @ .............ca. | |
45 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 46 | mov pc, lr |
1da177e4 LT |
47 | |
48 | /* | |
49 | * cpu_v6_reset(loc) | |
50 | * | |
51 | * Perform a soft reset of the system. Put the CPU into the | |
52 | * same state as it would be if it had been reset, and branch | |
53 | * to what would be the reset vector. | |
54 | * | |
55 | * - loc - location to jump to for soft reset | |
1da177e4 LT |
56 | */ |
57 | .align 5 | |
58 | ENTRY(cpu_v6_reset) | |
59 | mov pc, r0 | |
60 | ||
61 | /* | |
62 | * cpu_v6_do_idle() | |
63 | * | |
64 | * Idle the processor (eg, wait for interrupt). | |
65 | * | |
66 | * IRQs are already disabled. | |
67 | */ | |
68 | ENTRY(cpu_v6_do_idle) | |
8553cb67 CM |
69 | mov r1, #0 |
70 | mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode | |
1da177e4 LT |
71 | mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt |
72 | mov pc, lr | |
73 | ||
74 | ENTRY(cpu_v6_dcache_clean_area) | |
75 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
76 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
77 | add r0, r0, #D_CACHE_LINE_SIZE | |
78 | subs r1, r1, #D_CACHE_LINE_SIZE | |
79 | bhi 1b | |
80 | #endif | |
81 | mov pc, lr | |
82 | ||
83 | /* | |
84 | * cpu_arm926_switch_mm(pgd_phys, tsk) | |
85 | * | |
86 | * Set the translation table base pointer to be pgd_phys | |
87 | * | |
88 | * - pgd_phys - physical address of new TTB | |
89 | * | |
90 | * It is assumed that: | |
91 | * - we are not using split page tables | |
92 | */ | |
93 | ENTRY(cpu_v6_switch_mm) | |
d090ddda | 94 | #ifdef CONFIG_MMU |
1da177e4 LT |
95 | mov r2, #0 |
96 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
f00ec48f RK |
97 | ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) |
98 | ALT_UP(orr r0, r0, #TTB_FLAGS_UP) | |
d93742f5 | 99 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
1da177e4 LT |
100 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer |
101 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
102 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | |
d090ddda | 103 | #endif |
1da177e4 LT |
104 | mov pc, lr |
105 | ||
1da177e4 | 106 | /* |
ad1ae2fe | 107 | * cpu_v6_set_pte_ext(ptep, pte, ext) |
1da177e4 LT |
108 | * |
109 | * Set a level 2 translation table entry. | |
110 | * | |
111 | * - ptep - pointer to level 2 translation table entry | |
112 | * (hardware version is stored at -1024 bytes) | |
113 | * - pte - PTE value to store | |
ad1ae2fe | 114 | * - ext - value for extended PTE bits |
1da177e4 | 115 | */ |
639b0ae7 RK |
116 | armv6_mt_table cpu_v6 |
117 | ||
ad1ae2fe | 118 | ENTRY(cpu_v6_set_pte_ext) |
d090ddda | 119 | #ifdef CONFIG_MMU |
639b0ae7 | 120 | armv6_set_pte_ext cpu_v6 |
d090ddda | 121 | #endif |
1da177e4 LT |
122 | mov pc, lr |
123 | ||
124 | ||
125 | ||
edabd38e | 126 | .type cpu_v6_name, #object |
1da177e4 | 127 | cpu_v6_name: |
94b1e96d | 128 | .asciz "ARMv6-compatible processor" |
edabd38e SB |
129 | .size cpu_v6_name, . - cpu_v6_name |
130 | ||
131 | .type cpu_pj4_name, #object | |
132 | cpu_pj4_name: | |
133 | .asciz "Marvell PJ4 processor" | |
134 | .size cpu_pj4_name, . - cpu_pj4_name | |
135 | ||
1da177e4 LT |
136 | .align |
137 | ||
991da17e | 138 | __INIT |
1da177e4 LT |
139 | |
140 | /* | |
141 | * __v6_setup | |
142 | * | |
143 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
144 | * on. Return in r0 the new CP15 C1 control register setting. | |
145 | * | |
146 | * We automatically detect if we have a Harvard cache, and use the | |
147 | * Harvard cache control instructions insead of the unified cache | |
148 | * control instructions. | |
149 | * | |
150 | * This should be able to cover all ARMv6 cores. | |
151 | * | |
152 | * It is assumed that: | |
153 | * - cache type register is implemented | |
154 | */ | |
155 | __v6_setup: | |
862184fe | 156 | #ifdef CONFIG_SMP |
f00ec48f RK |
157 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode |
158 | ALT_UP(nop) | |
862184fe | 159 | orr r0, r0, #0x20 |
f00ec48f RK |
160 | ALT_SMP(mcr p15, 0, r0, c1, c0, 1) |
161 | ALT_UP(nop) | |
862184fe RK |
162 | #endif |
163 | ||
1da177e4 LT |
164 | mov r0, #0 |
165 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | |
166 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
167 | mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache | |
168 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
d090ddda | 169 | #ifdef CONFIG_MMU |
1da177e4 LT |
170 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs |
171 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register | |
f00ec48f RK |
172 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) |
173 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | |
1da177e4 | 174 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
d090ddda | 175 | #endif /* CONFIG_MMU */ |
22b19086 RK |
176 | adr r5, v6_crval |
177 | ldmia r5, {r5, r6} | |
26584853 CM |
178 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
179 | orr r6, r6, #1 << 25 @ big-endian page tables | |
180 | #endif | |
1da177e4 | 181 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
1da177e4 | 182 | bic r0, r0, r5 @ clear bits them |
22b19086 | 183 | orr r0, r0, r6 @ set them |
1da177e4 LT |
184 | mov pc, lr @ return to head.S:__ret |
185 | ||
186 | /* | |
187 | * V X F I D LR | |
188 | * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM | |
189 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
190 | * 0 110 0011 1.00 .111 1101 < we want | |
191 | */ | |
22b19086 RK |
192 | .type v6_crval, #object |
193 | v6_crval: | |
194 | crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c | |
1da177e4 LT |
195 | |
196 | .type v6_processor_functions, #object | |
197 | ENTRY(v6_processor_functions) | |
198 | .word v6_early_abort | |
4fb28474 | 199 | .word v6_pabort |
1da177e4 LT |
200 | .word cpu_v6_proc_init |
201 | .word cpu_v6_proc_fin | |
202 | .word cpu_v6_reset | |
203 | .word cpu_v6_do_idle | |
204 | .word cpu_v6_dcache_clean_area | |
205 | .word cpu_v6_switch_mm | |
ad1ae2fe | 206 | .word cpu_v6_set_pte_ext |
1da177e4 LT |
207 | .size v6_processor_functions, . - v6_processor_functions |
208 | ||
209 | .type cpu_arch_name, #object | |
210 | cpu_arch_name: | |
211 | .asciz "armv6" | |
212 | .size cpu_arch_name, . - cpu_arch_name | |
213 | ||
214 | .type cpu_elf_name, #object | |
215 | cpu_elf_name: | |
216 | .asciz "v6" | |
217 | .size cpu_elf_name, . - cpu_elf_name | |
218 | .align | |
219 | ||
02b7dd12 | 220 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
221 | |
222 | /* | |
223 | * Match any ARMv6 processor core. | |
224 | */ | |
225 | .type __v6_proc_info, #object | |
226 | __v6_proc_info: | |
227 | .long 0x0007b000 | |
228 | .long 0x0007f000 | |
f00ec48f RK |
229 | ALT_SMP(.long \ |
230 | PMD_TYPE_SECT | \ | |
231 | PMD_SECT_AP_WRITE | \ | |
232 | PMD_SECT_AP_READ | \ | |
233 | PMD_FLAGS_SMP) | |
234 | ALT_UP(.long \ | |
235 | PMD_TYPE_SECT | \ | |
1da177e4 | 236 | PMD_SECT_AP_WRITE | \ |
4b46d641 | 237 | PMD_SECT_AP_READ | \ |
f00ec48f | 238 | PMD_FLAGS_UP) |
8799ee9f RK |
239 | .long PMD_TYPE_SECT | \ |
240 | PMD_SECT_XN | \ | |
241 | PMD_SECT_AP_WRITE | \ | |
242 | PMD_SECT_AP_READ | |
1da177e4 LT |
243 | b __v6_setup |
244 | .long cpu_arch_name | |
245 | .long cpu_elf_name | |
f159f4ed TL |
246 | /* See also feat_v6_fixup() for HWCAP_TLS */ |
247 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS | |
1da177e4 LT |
248 | .long cpu_v6_name |
249 | .long v6_processor_functions | |
250 | .long v6wbi_tlb_fns | |
251 | .long v6_user_fns | |
252 | .long v6_cache_fns | |
253 | .size __v6_proc_info, . - __v6_proc_info | |
edabd38e SB |
254 | |
255 | .type __pj4_v6_proc_info, #object | |
256 | __pj4_v6_proc_info: | |
257 | .long 0x560f5810 | |
258 | .long 0xff0ffff0 | |
f00ec48f RK |
259 | ALT_SMP(.long \ |
260 | PMD_TYPE_SECT | \ | |
261 | PMD_SECT_AP_WRITE | \ | |
262 | PMD_SECT_AP_READ | \ | |
263 | PMD_FLAGS_SMP) | |
264 | ALT_UP(.long \ | |
265 | PMD_TYPE_SECT | \ | |
edabd38e | 266 | PMD_SECT_AP_WRITE | \ |
f0e5d2c9 | 267 | PMD_SECT_AP_READ | \ |
f00ec48f | 268 | PMD_FLAGS_UP) |
edabd38e SB |
269 | .long PMD_TYPE_SECT | \ |
270 | PMD_SECT_XN | \ | |
271 | PMD_SECT_AP_WRITE | \ | |
272 | PMD_SECT_AP_READ | |
273 | b __v6_setup | |
274 | .long cpu_arch_name | |
275 | .long cpu_elf_name | |
f159f4ed | 276 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS |
edabd38e SB |
277 | .long cpu_pj4_name |
278 | .long v6_processor_functions | |
279 | .long v6wbi_tlb_fns | |
280 | .long v6_user_fns | |
281 | .long v6_cache_fns | |
282 | .size __pj4_v6_proc_info, . - __pj4_v6_proc_info |