[net-next-2.6.git] / arch / arm / mm / proc-arm940.S

/*
 *  linux/arch/arm/mm/arm940.S: utility functions for ARM940T
 *
 *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/elf.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
#define CACHE_DLINESIZE	16
#define CACHE_DSEGMENTS	4
#define CACHE_DENTRIES	64

	.text
/*
 * cpu_arm940_proc_init()
 * cpu_arm940_switch_mm()
 *
 * These are not required.
 */
ENTRY(cpu_arm940_proc_init)
ENTRY(cpu_arm940_switch_mm)
	mov	pc, lr

/*
 * cpu_arm940_proc_fin()
 */
ENTRY(cpu_arm940_proc_fin)
	stmfd	sp!, {lr}
	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	msr	cpsr_c, ip
	bl	arm940_flush_kern_cache_all
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x00001000		@ i-cache
	bic	r0, r0, #0x00000004		@ d-cache
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldmfd	sp!, {pc}

/*
 * cpu_arm940_reset(loc)
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
ENTRY(cpu_arm940_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0		@ flush I cache
	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x00000005		@ .............c.p
	bic	ip, ip, #0x00001000		@ i-cache
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm940_do_idle()
 */
	.align	5
ENTRY(cpu_arm940_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr

/*
 *	flush_user_cache_all()
 */
ENTRY(arm940_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm940_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	/* FALLTHROUGH */

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	There is no efficient way to flush a range of cache entries
 *	in the specified address range. Thus, flushes all.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm940_flush_user_cache_range)
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
#else
	mov	r1, #(CACHE_DSEGMENTS - 1) << 4	@ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 4
	bcs	1b				@ segments 3 to 0
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm940_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm940_coherent_user_range)
	/* FALLTHROUGH */

/*
 *	flush_kern_dcache_page(void *page)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- page aligned address
 */
ENTRY(arm940_flush_kern_dcache_page)
	mov	ip, #0
	mov	r1, #(CACHE_DSEGMENTS - 1) << 4	@ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 4
	bcs	1b				@ segments 7 to 0
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	There is no efficient way to invalidate a specifid virtual
 *	address range. Thus, invalidates all.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm940_dma_inv_range)
	mov	ip, #0
	mov	r1, #(CACHE_DSEGMENTS - 1) << 4	@ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c6, 2		@ flush D entry
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 4
	bcs	1b				@ segments 7 to 0
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	There is no efficient way to clean a specifid virtual
 *	address range. Thus, cleans all.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm940_dma_clean_range)
ENTRY(cpu_arm940_dcache_clean_area)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r1, #(CACHE_DSEGMENTS - 1) << 4	@ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c10, 2		@ clean D entry
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 4
	bcs	1b				@ segments 7 to 0
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	There is no efficient way to clean and invalidate a specifid
 *	virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm940_dma_flush_range)
	mov	ip, #0
	mov	r1, #(CACHE_DSEGMENTS - 1) << 4	@ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D entry
#else
	mcr	p15, 0, r3, c7, c6, 2		@ invalidate D entry
#endif
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 4
	bcs	1b				@ segments 7 to 0
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

ENTRY(arm940_cache_fns)
	.long	arm940_flush_kern_cache_all
	.long	arm940_flush_user_cache_all
	.long	arm940_flush_user_cache_range
	.long	arm940_coherent_kern_range
	.long	arm940_coherent_user_range
	.long	arm940_flush_kern_dcache_page
	.long	arm940_dma_inv_range
	.long	arm940_dma_clean_range
	.long	arm940_dma_flush_range

	__INIT

	.type	__arm940_setup, #function
__arm940_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c6, 0		@ invalidate D cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c6, c3, 0		@ disable data area 3~7
	mcr	p15, 0, r0, c6, c4, 0
	mcr	p15, 0, r0, c6, c5, 0
	mcr	p15, 0, r0, c6, c6, 0
	mcr	p15, 0, r0, c6, c7, 0

	mcr	p15, 0, r0, c6, c3, 1		@ disable instruction area 3~7
	mcr	p15, 0, r0, c6, c4, 1
	mcr	p15, 0, r0, c6, c5, 1
	mcr	p15, 0, r0, c6, c6, 1
	mcr	p15, 0, r0, c6, c7, 1

	mov	r0, #0x0000003F			@ base = 0, size = 4GB
	mcr	p15, 0, r0, c6,	c0, 0		@ set area 0, default
	mcr	p15, 0, r0, c6,	c0, 1

	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	ldr	r1, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)
	mov	r2, #10				@ 11 is the minimum (4KB)
1:	add	r2, r2, #1			@ area size *= 2
	mov	r1, r1, lsr #1
	bne	1b				@ count not zero r-shift
	orr	r0, r0, r2, lsl #1		@ the area register value
	orr	r0, r0, #1			@ set enable bit
	mcr	p15, 0, r0, c6,	c1, 0		@ set area 1, RAM
	mcr	p15, 0, r0, c6,	c1, 1

	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	ldr	r1, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)
	mov	r2, #10				@ 11 is the minimum (4KB)
1:	add	r2, r2, #1			@ area size *= 2
	mov	r1, r1, lsr #1
	bne	1b				@ count not zero r-shift
	orr	r0, r0, r2, lsl #1		@ the area register value
	orr	r0, r0, #1			@ set enable bit
	mcr	p15, 0, r0, c6,	c2, 0		@ set area 2, ROM/FLASH
	mcr	p15, 0, r0, c6,	c2, 1

	mov	r0, #0x06
	mcr	p15, 0, r0, c2, c0, 0		@ Region 1&2 cacheable
	mcr	p15, 0, r0, c2, c0, 1
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #0x00			@ disable whole write buffer
#else
	mov	r0, #0x02			@ Region 1 write bufferred
#endif
	mcr	p15, 0, r0, c3, c0, 0

	mov	r0, #0x10000
	sub	r0, r0, #1			@ r0 = 0xffff
	mcr	p15, 0, r0, c5, c0, 0		@ all read/write access
	mcr	p15, 0, r0, c5, c0, 1

	mrc	p15, 0, r0, c1, c0		@ get control register
	orr	r0, r0, #0x00001000		@ I-cache
	orr	r0, r0, #0x00000005		@ MPU/D-cache

	mov	pc, lr

	.size	__arm940_setup, . - __arm940_setup

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm940_processor_functions, #object
ENTRY(arm940_processor_functions)
	.word	nommu_early_abort
	.word	pabort_noifar
	.word	cpu_arm940_proc_init
	.word	cpu_arm940_proc_fin
	.word	cpu_arm940_reset
	.word   cpu_arm940_do_idle
	.word	cpu_arm940_dcache_clean_area
	.word	cpu_arm940_switch_mm
	.word	0		@ cpu_*_set_pte
	.size	arm940_processor_functions, . - arm940_processor_functions

	.section ".rodata"

.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv4t"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v4"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm940_name, #object
cpu_arm940_name:
	.ascii	"ARM940T"
	.size	cpu_arm940_name, . - cpu_arm940_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm940_proc_info,#object
__arm940_proc_info:
	.long	0x41009400
	.long	0xff00fff0
	.long	0
	b	__arm940_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm940_name
	.long	arm940_processor_functions
	.long	0
	.long	0
	.long	arm940_cache_fns
	.size	__arm940_proc_info, . - __arm940_proc_info
Commit	Line	Data
d60674eb HC	1	/*
	2	* linux/arch/arm/mm/arm940.S: utility functions for ARM940T
	3	*
	4	* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11	#include <linux/linkage.h>
	12	#include <linux/init.h>
	13	#include <asm/assembler.h>
ee90dabc	14	#include <asm/elf.h>
d60674eb HC	15	#include <asm/pgtable-hwdef.h>
d60674eb HC	16	#include <asm/pgtable.h>
d60674eb	17	#include <asm/ptrace.h>
8a5544c8	18	#include "proc-macros.S"
d60674eb HC	19
	20	/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
	21	#define CACHE_DLINESIZE 16
	22	#define CACHE_DSEGMENTS 4
	23	#define CACHE_DENTRIES 64
	24
	25	.text
	26	/*
	27	* cpu_arm940_proc_init()
	28	* cpu_arm940_switch_mm()
	29	*
	30	* These are not required.
	31	*/
	32	ENTRY(cpu_arm940_proc_init)
	33	ENTRY(cpu_arm940_switch_mm)
	34	mov pc, lr
	35
	36	/*
	37	* cpu_arm940_proc_fin()
	38	*/
	39	ENTRY(cpu_arm940_proc_fin)
	40	stmfd sp!, {lr}
	41	mov ip, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
	42	msr cpsr_c, ip
	43	bl arm940_flush_kern_cache_all
	44	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	45	bic r0, r0, #0x00001000 @ i-cache
	46	bic r0, r0, #0x00000004 @ d-cache
	47	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	48	ldmfd sp!, {pc}
	49
	50	/*
	51	* cpu_arm940_reset(loc)
	52	* Params : r0 = address to jump to
	53	* Notes : This sets up everything for a reset
	54	*/
	55	ENTRY(cpu_arm940_reset)
	56	mov ip, #0
	57	mcr p15, 0, ip, c7, c5, 0 @ flush I cache
	58	mcr p15, 0, ip, c7, c6, 0 @ flush D cache
	59	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	60	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	61	bic ip, ip, #0x00000005 @ .............c.p
	62	bic ip, ip, #0x00001000 @ i-cache
	63	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	64	mov pc, r0
	65
	66	/*
	67	* cpu_arm940_do_idle()
	68	*/
	69	.align 5
	70	ENTRY(cpu_arm940_do_idle)
	71	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	72	mov pc, lr
	73
	74	/*
	75	* flush_user_cache_all()
	76	*/
	77	ENTRY(arm940_flush_user_cache_all)
	78	/* FALLTHROUGH */
	79
	80	/*
	81	* flush_kern_cache_all()
	82	*
83	* Clean and invalidate the entire cache.
84	*/
85	ENTRY(arm940_flush_kern_cache_all)
86	mov r2, #VM_EXEC
87	/* FALLTHROUGH */
88
89	/*
90	* flush_user_cache_range(start, end, flags)
91	*
92	* There is no efficient way to flush a range of cache entries
93	* in the specified address range. Thus, flushes all.
94	*
95	* - start - start address (inclusive)
96	* - end - end address (exclusive)
97	* - flags - vm_flags describing address space
98	*/
99	ENTRY(arm940_flush_user_cache_range)
100	mov ip, #0
101	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
102	mcr p15, 0, ip, c7, c6, 0 @ flush D cache
103	#else
104	mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
105	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
106	2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
107	subs r3, r3, #1 << 26
108	bcs 2b @ entries 63 to 0
109	subs r1, r1, #1 << 4
110	bcs 1b @ segments 3 to 0
111	#endif
112	tst r2, #VM_EXEC
113	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
114	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
115	mov pc, lr
116
117	/*
118	* coherent_kern_range(start, end)
119	*
120	* Ensure coherency between the Icache and the Dcache in the
121	* region described by start, end. If you have non-snooping
122	* Harvard caches, you need to implement this function.
123	*
124	* - start - virtual start address
125	* - end - virtual end address
126	*/
127	ENTRY(arm940_coherent_kern_range)
128	/* FALLTHROUGH */
129
130	/*
131	* coherent_user_range(start, end)
132	*
133	* Ensure coherency between the Icache and the Dcache in the
134	* region described by start, end. If you have non-snooping
135	* Harvard caches, you need to implement this function.
136	*
137	* - start - virtual start address
138	* - end - virtual end address
139	*/
140	ENTRY(arm940_coherent_user_range)
141	/* FALLTHROUGH */
142
143	/*
144	* flush_kern_dcache_page(void *page)
145	*
146	* Ensure no D cache aliasing occurs, either with itself or
147	* the I cache
148	*
149	* - addr - page aligned address
150	*/
151	ENTRY(arm940_flush_kern_dcache_page)
152	mov ip, #0
153	mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
154	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
155	2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
156	subs r3, r3, #1 << 26
157	bcs 2b @ entries 63 to 0
158	subs r1, r1, #1 << 4
159	bcs 1b @ segments 7 to 0
160	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
161	mcr p15, 0, ip, c7, c10, 4 @ drain WB
162	mov pc, lr
163
164	/*
165	* dma_inv_range(start, end)
166	*
167	* There is no efficient way to invalidate a specifid virtual
168	* address range. Thus, invalidates all.
169	*
170	* - start - virtual start address
171	* - end - virtual end address
172	*/
173	ENTRY(arm940_dma_inv_range)
174	mov ip, #0
175	mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
176	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
177	2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
178	subs r3, r3, #1 << 26
179	bcs 2b @ entries 63 to 0
180	subs r1, r1, #1 << 4
181	bcs 1b @ segments 7 to 0
182	mcr p15, 0, ip, c7, c10, 4 @ drain WB
183	mov pc, lr
184
185	/*
186	* dma_clean_range(start, end)
187	*
188	* There is no efficient way to clean a specifid virtual
189	* address range. Thus, cleans all.
190	*
191	* - start - virtual start address
192	* - end - virtual end address
193	*/
194	ENTRY(arm940_dma_clean_range)
195	ENTRY(cpu_arm940_dcache_clean_area)
196	mov ip, #0
197	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
198	mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
199	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
200	2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
201	subs r3, r3, #1 << 26
202	bcs 2b @ entries 63 to 0
203	subs r1, r1, #1 << 4
204	bcs 1b @ segments 7 to 0
205	#endif
206	mcr p15, 0, ip, c7, c10, 4 @ drain WB
207	mov pc, lr
208
209	/*
210	* dma_flush_range(start, end)
211	*
212	* There is no efficient way to clean and invalidate a specifid
213	* virtual address range.
214	*
215	* - start - virtual start address
216	* - end - virtual end address
217	*/
218	ENTRY(arm940_dma_flush_range)
219	mov ip, #0
220	mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
221	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
222	2:
223	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
224	mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
225	#else
b3a8b751	226	mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
d60674eb HC	227	#endif
	228	subs r3, r3, #1 << 26
	229	bcs 2b @ entries 63 to 0
	230	subs r1, r1, #1 << 4
	231	bcs 1b @ segments 7 to 0
	232	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	233	mov pc, lr
	234
	235	ENTRY(arm940_cache_fns)
	236	.long arm940_flush_kern_cache_all
	237	.long arm940_flush_user_cache_all
	238	.long arm940_flush_user_cache_range
	239	.long arm940_coherent_kern_range
	240	.long arm940_coherent_user_range
	241	.long arm940_flush_kern_dcache_page
	242	.long arm940_dma_inv_range
	243	.long arm940_dma_clean_range
	244	.long arm940_dma_flush_range
	245
	246	__INIT
	247
	248	.type __arm940_setup, #function
	249	__arm940_setup:
	250	mov r0, #0
	251	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	252	mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
	253	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	254
	255	mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
	256	mcr p15, 0, r0, c6, c4, 0
	257	mcr p15, 0, r0, c6, c5, 0
	258	mcr p15, 0, r0, c6, c6, 0
	259	mcr p15, 0, r0, c6, c7, 0
	260
	261	mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
	262	mcr p15, 0, r0, c6, c4, 1
	263	mcr p15, 0, r0, c6, c5, 1
	264	mcr p15, 0, r0, c6, c6, 1
	265	mcr p15, 0, r0, c6, c7, 1
	266
	267	mov r0, #0x0000003F @ base = 0, size = 4GB
	268	mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
	269	mcr p15, 0, r0, c6, c0, 1
	270
	271	ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	272	ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
	273	mov r2, #10 @ 11 is the minimum (4KB)
	274	1: add r2, r2, #1 @ area size *= 2
	275	mov r1, r1, lsr #1
	276	bne 1b @ count not zero r-shift
	277	orr r0, r0, r2, lsl #1 @ the area register value
	278	orr r0, r0, #1 @ set enable bit
	279	mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
	280	mcr p15, 0, r0, c6, c1, 1
	281
	282	ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	283	ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
	284	mov r2, #10 @ 11 is the minimum (4KB)
	285	1: add r2, r2, #1 @ area size *= 2
	286	mov r1, r1, lsr #1
	287	bne 1b @ count not zero r-shift
	288	orr r0, r0, r2, lsl #1 @ the area register value
	289	orr r0, r0, #1 @ set enable bit
	290	mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
291	mcr p15, 0, r0, c6, c2, 1
292
293	mov r0, #0x06
294	mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
295	mcr p15, 0, r0, c2, c0, 1
296	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
297	mov r0, #0x00 @ disable whole write buffer
298	#else
299	mov r0, #0x02 @ Region 1 write bufferred
300	#endif
301	mcr p15, 0, r0, c3, c0, 0
302
303	mov r0, #0x10000
304	sub r0, r0, #1 @ r0 = 0xffff
305	mcr p15, 0, r0, c5, c0, 0 @ all read/write access
306	mcr p15, 0, r0, c5, c0, 1
307
308	mrc p15, 0, r0, c1, c0 @ get control register
309	orr r0, r0, #0x00001000 @ I-cache
310	orr r0, r0, #0x00000005 @ MPU/D-cache
311
312	mov pc, lr
313
314	.size __arm940_setup, . - __arm940_setup
315
316	__INITDATA
317
318	/*
319	* Purpose : Function pointers used to access above functions - all calls
320	* come through these
321	*/
322	.type arm940_processor_functions, #object
323	ENTRY(arm940_processor_functions)
0f45d7f3	324	.word nommu_early_abort
4a1fd556	325	.word pabort_noifar
d60674eb HC	326	.word cpu_arm940_proc_init
	327	.word cpu_arm940_proc_fin
	328	.word cpu_arm940_reset
	329	.word cpu_arm940_do_idle
	330	.word cpu_arm940_dcache_clean_area
	331	.word cpu_arm940_switch_mm
	332	.word 0 @ cpu_*_set_pte
	333	.size arm940_processor_functions, . - arm940_processor_functions
	334
	335	.section ".rodata"
	336
	337	.type cpu_arch_name, #object
	338	cpu_arch_name:
	339	.asciz "armv4t"
	340	.size cpu_arch_name, . - cpu_arch_name
	341
	342	.type cpu_elf_name, #object
	343	cpu_elf_name:
	344	.asciz "v4"
	345	.size cpu_elf_name, . - cpu_elf_name
	346
	347	.type cpu_arm940_name, #object
	348	cpu_arm940_name:
	349	.ascii "ARM940T"
	350	.size cpu_arm940_name, . - cpu_arm940_name
	351
	352	.align
	353
	354	.section ".proc.info.init", #alloc, #execinstr
	355
	356	.type __arm940_proc_info,#object
	357	__arm940_proc_info:
	358	.long 0x41009400
	359	.long 0xff00fff0
	360	.long 0
	361	b __arm940_setup
	362	.long cpu_arch_name
	363	.long cpu_elf_name
	364	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	365	.long cpu_arm940_name
	366	.long arm940_processor_functions
	367	.long 0
	368	.long 0
	369	.long arm940_cache_fns
	370	.size __arm940_proc_info, . - __arm940_proc_info
	371