[net-next-2.6.git] / arch / arm / mm / proc-arm1020e.S

/*
 *  linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
 *
 *  Copyright (C) 2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm1020e.
 *
 *  CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE	32768

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	16

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintainence instructions.
 */
#define CACHE_DLIMIT	32768

	.text
/*
 * cpu_arm1020e_proc_init()
 */
ENTRY(cpu_arm1020e_proc_init)
	mov	pc, lr

/*
 * cpu_arm1020e_proc_fin()
 */
ENTRY(cpu_arm1020e_proc_fin)
	stmfd	sp!, {lr}
	mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
	msr	cpsr_c, ip
	bl	arm1020e_flush_kern_cache_all
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000 		@ ...i............
	bic	r0, r0, #0x000e 		@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldmfd	sp!, {pc}

/*
 * cpu_arm1020e_reset(loc)
 *
 * Perform a soft reset of the system.	Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm1020e_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f 		@ ............wcam
	bic	ip, ip, #0x1100 		@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm1020e_do_idle()
 */
	.align	5
ENTRY(cpu_arm1020e_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr

/* ================================= CACHE ================================ */

	.align	5
/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
ENTRY(arm1020e_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm1020e_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 15 to 0
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags for this space
 */
ENTRY(arm1020e_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

#ifndef CONFIG_CPU_DCACHE_DISABLE
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020e_coherent_kern_range)
	/* FALLTHROUGH */
/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020e_coherent_user_range)
	mov	ip, #0
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm1020e_flush_kern_dcache_area)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020e_dma_inv_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020e_dma_clean_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020e_dma_flush_range)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1020e_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm1020e_dma_clean_range
	bcs	arm1020e_dma_inv_range
	b	arm1020e_dma_flush_range
ENDPROC(arm1020e_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1020e_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm1020e_dma_unmap_area)

ENTRY(arm1020e_cache_fns)
	.long	arm1020e_flush_kern_cache_all
	.long	arm1020e_flush_user_cache_all
	.long	arm1020e_flush_user_cache_range
	.long	arm1020e_coherent_kern_range
	.long	arm1020e_coherent_user_range
	.long	arm1020e_flush_kern_dcache_area
	.long	arm1020e_dma_map_area
	.long	arm1020e_dma_unmap_area
	.long	arm1020e_dma_flush_range

	.align	5
ENTRY(cpu_arm1020e_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	ip, #0
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm1020e_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm1020e_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r3, c7, c10, 4
	mov	r1, #0xF			@ 16 segments
1:	mov	r3, #0x3F			@ 64 entries
2:	mov	ip, r3, LSL #26 		@ shift up entry
	orr	ip, ip, r1, LSL #5		@ shift in/up index
	mcr	p15, 0, ip, c7, c14, 2		@ Clean & Inval DCache entry
	mov	ip, #0
	subs	r3, r3, #1
	cmp	r3, #0
	bge	2b				@ entries 3F to 0
	subs	r1, r1, #1
	cmp	r1, #0
	bge	1b				@ segments 15 to 0

#endif
	mov	r1, #0
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
#endif
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr
        
/*
 * cpu_arm1020e_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm1020e_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
#endif /* CONFIG_MMU */
	mov	pc, lr

	__INIT

	.type	__arm1020e_setup, #function
__arm1020e_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif
	adr	r5, arm1020e_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm1020e_setup, . - __arm1020e_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 1001 ..11 0101
	 */
	.type	arm1020e_crval, #object
arm1020e_crval:
	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm1020e_processor_functions, #object
arm1020e_processor_functions:
	.word	v4t_early_abort
	.word	legacy_pabort
	.word	cpu_arm1020e_proc_init
	.word	cpu_arm1020e_proc_fin
	.word	cpu_arm1020e_reset
	.word	cpu_arm1020e_do_idle
	.word	cpu_arm1020e_dcache_clean_area
	.word	cpu_arm1020e_switch_mm
	.word	cpu_arm1020e_set_pte_ext
	.size	arm1020e_processor_functions, . - arm1020e_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5te"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm1020e_name, #object
cpu_arm1020e_name:
	.asciz	"ARM1020E"
	.size	cpu_arm1020e_name, . - cpu_arm1020e_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm1020e_proc_info,#object
__arm1020e_proc_info:
	.long	0x4105a200			@ ARM 1020TE (Architecture v5TE)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm1020e_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
	.long	cpu_arm1020e_name
	.long	arm1020e_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm1020e_cache_fns
	.size	__arm1020e_proc_info, . - __arm1020e_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
	3	*
	4	* Copyright (C) 2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*
	23	* These are the low level assembler for performing cache and TLB
	24	* functions on the arm1020e.
	25	*
	26	* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
	27	*/
	28	#include <linux/linkage.h>
1da177e4 LT	29	#include <linux/init.h>
1da177e4 LT	30	#include <asm/assembler.h>
e6ae744d	31	#include <asm/asm-offsets.h>
5ec9407d	32	#include <asm/hwcap.h>
74945c86	33	#include <asm/pgtable-hwdef.h>
1da177e4	34	#include <asm/pgtable.h>
1da177e4	35	#include <asm/ptrace.h>
1da177e4	36
00eb0f6b RK	37	#include "proc-macros.S"
00eb0f6b RK	38
1da177e4 LT	39	/*
	40	* This is the maximum size of an area which will be invalidated
	41	* using the single invalidate entry instructions. Anything larger
	42	* than this, and we go for the whole cache.
	43	*
	44	* This value should be chosen such that we choose the cheapest
	45	* alternative.
	46	*/
	47	#define MAX_AREA_SIZE 32768
	48
	49	/*
	50	* The size of one data cache line.
	51	*/
	52	#define CACHE_DLINESIZE 32
	53
	54	/*
	55	* The number of data cache segments.
	56	*/
	57	#define CACHE_DSEGMENTS 16
	58
	59	/*
	60	* The number of lines in a cache segment.
	61	*/
	62	#define CACHE_DENTRIES 64
	63
	64	/*
	65	* This is the size at which it becomes more efficient to
	66	* clean the whole cache, rather than using the individual
	67	* cache line maintainence instructions.
	68	*/
	69	#define CACHE_DLIMIT 32768
	70
	71	.text
	72	/*
	73	* cpu_arm1020e_proc_init()
	74	*/
	75	ENTRY(cpu_arm1020e_proc_init)
	76	mov pc, lr
	77
	78	/*
	79	* cpu_arm1020e_proc_fin()
	80	*/
	81	ENTRY(cpu_arm1020e_proc_fin)
	82	stmfd sp!, {lr}
	83	mov ip, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
	84	msr cpsr_c, ip
	85	bl arm1020e_flush_kern_cache_all
	86	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	87	bic r0, r0, #0x1000 @ ...i............
	88	bic r0, r0, #0x000e @ ............wca.
	89	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	90	ldmfd sp!, {pc}
	91
	92	/*
	93	* cpu_arm1020e_reset(loc)
	94	*
	95	* Perform a soft reset of the system. Put the CPU into the
	96	* same state as it would be if it had been reset, and branch
	97	* to what would be the reset vector.
	98	*
	99	* loc: location to jump to for soft reset
	100	*/
	101	.align 5
	102	ENTRY(cpu_arm1020e_reset)
103	mov ip, #0
104	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	106	#ifdef CONFIG_MMU
1da177e4	107	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	108	#endif
1da177e4 LT	109	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	110	bic ip, ip, #0x000f @ ............wcam
	111	bic ip, ip, #0x1100 @ ...i...s........
	112	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	113	mov pc, r0
	114
	115	/*
	116	* cpu_arm1020e_do_idle()
	117	*/
	118	.align 5
	119	ENTRY(cpu_arm1020e_do_idle)
	120	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	121	mov pc, lr
	122
	123	/* ================================= CACHE ================================ */
	124
	125	.align 5
	126	/*
	127	* flush_user_cache_all()
	128	*
	129	* Invalidate all cache entries in a particular address
	130	* space.
	131	*/
	132	ENTRY(arm1020e_flush_user_cache_all)
	133	/* FALLTHROUGH */
	134	/*
	135	* flush_kern_cache_all()
	136	*
	137	* Clean and invalidate the entire cache.
	138	*/
	139	ENTRY(arm1020e_flush_kern_cache_all)
	140	mov r2, #VM_EXEC
	141	mov ip, #0
	142	__flush_whole_cache:
	143	#ifndef CONFIG_CPU_DCACHE_DISABLE
	144	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	145	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
	146	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	147	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	148	subs r3, r3, #1 << 26
	149	bcs 2b @ entries 63 to 0
	150	subs r1, r1, #1 << 5
	151	bcs 1b @ segments 15 to 0
	152	#endif
	153	tst r2, #VM_EXEC
	154	#ifndef CONFIG_CPU_ICACHE_DISABLE
	155	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	156	#endif
	157	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	158	mov pc, lr
	159
	160	/*
	161	* flush_user_cache_range(start, end, flags)
	162	*
	163	* Invalidate a range of cache entries in the specified
	164	* address space.
	165	*
	166	* - start - start address (inclusive)
	167	* - end - end address (exclusive)
	168	* - flags - vm_flags for this space
	169	*/
	170	ENTRY(arm1020e_flush_user_cache_range)
	171	mov ip, #0
	172	sub r3, r1, r0 @ calculate total size
173	cmp r3, #CACHE_DLIMIT
174	bhs __flush_whole_cache
175
176	#ifndef CONFIG_CPU_DCACHE_DISABLE
177	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
178	add r0, r0, #CACHE_DLINESIZE
179	cmp r0, r1
180	blo 1b
181	#endif
182	tst r2, #VM_EXEC
183	#ifndef CONFIG_CPU_ICACHE_DISABLE
184	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
185	#endif
186	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
187	mov pc, lr
188
189	/*
190	* coherent_kern_range(start, end)
191	*
192	* Ensure coherency between the Icache and the Dcache in the
193	* region described by start. If you have non-snooping
194	* Harvard caches, you need to implement this function.
195	*
196	* - start - virtual start address
197	* - end - virtual end address
198	*/
199	ENTRY(arm1020e_coherent_kern_range)
200	/* FALLTHROUGH */
201	/*
202	* coherent_user_range(start, end)
203	*
204	* Ensure coherency between the Icache and the Dcache in the
205	* region described by start. If you have non-snooping
206	* Harvard caches, you need to implement this function.
207	*
208	* - start - virtual start address
209	* - end - virtual end address
210	*/
211	ENTRY(arm1020e_coherent_user_range)
212	mov ip, #0
213	bic r0, r0, #CACHE_DLINESIZE - 1
214	1:
215	#ifndef CONFIG_CPU_DCACHE_DISABLE
216	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
217	#endif
218	#ifndef CONFIG_CPU_ICACHE_DISABLE
219	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220	#endif
221	add r0, r0, #CACHE_DLINESIZE
222	cmp r0, r1
223	blo 1b
224	mcr p15, 0, ip, c7, c10, 4 @ drain WB
225	mov pc, lr
226
227	/*
2c9b9c84	228	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	229	*
	230	* Ensure no D cache aliasing occurs, either with itself or
	231	* the I cache
	232	*
2c9b9c84 RK	233	* - addr - kernel address
2c9b9c84 RK	234	* - size - region size
1da177e4	235	*/
2c9b9c84	236	ENTRY(arm1020e_flush_kern_dcache_area)
1da177e4 LT	237	mov ip, #0
1da177e4 LT	238	#ifndef CONFIG_CPU_DCACHE_DISABLE
2c9b9c84	239	add r1, r0, r1
1da177e4 LT	240	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	241	add r0, r0, #CACHE_DLINESIZE
	242	cmp r0, r1
	243	blo 1b
	244	#endif
	245	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	246	mov pc, lr
	247
	248	/*
	249	* dma_inv_range(start, end)
	250	*
	251	* Invalidate (discard) the specified virtual address range.
	252	* May not write back any entries. If 'start' or 'end'
	253	* are not cache line aligned, those lines must be written
	254	* back.
	255	*
	256	* - start - virtual start address
	257	* - end - virtual end address
	258	*
	259	* (same as v4wb)
	260	*/
702b94bf	261	arm1020e_dma_inv_range:
1da177e4 LT	262	mov ip, #0
	263	#ifndef CONFIG_CPU_DCACHE_DISABLE
	264	tst r0, #CACHE_DLINESIZE - 1
	265	bic r0, r0, #CACHE_DLINESIZE - 1
	266	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	267	tst r1, #CACHE_DLINESIZE - 1
	268	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	269	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	270	add r0, r0, #CACHE_DLINESIZE
	271	cmp r0, r1
	272	blo 1b
	273	#endif
	274	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	275	mov pc, lr
	276
	277	/*
	278	* dma_clean_range(start, end)
	279	*
	280	* Clean the specified virtual address range.
	281	*
	282	* - start - virtual start address
	283	* - end - virtual end address
	284	*
	285	* (same as v4wb)
	286	*/
702b94bf	287	arm1020e_dma_clean_range:
1da177e4 LT	288	mov ip, #0
	289	#ifndef CONFIG_CPU_DCACHE_DISABLE
	290	bic r0, r0, #CACHE_DLINESIZE - 1
	291	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	292	add r0, r0, #CACHE_DLINESIZE
	293	cmp r0, r1
	294	blo 1b
	295	#endif
	296	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	297	mov pc, lr
	298
	299	/*
	300	* dma_flush_range(start, end)
	301	*
	302	* Clean and invalidate the specified virtual address range.
	303	*
	304	* - start - virtual start address
	305	* - end - virtual end address
	306	*/
	307	ENTRY(arm1020e_dma_flush_range)
	308	mov ip, #0
	309	#ifndef CONFIG_CPU_DCACHE_DISABLE
	310	bic r0, r0, #CACHE_DLINESIZE - 1
	311	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	312	add r0, r0, #CACHE_DLINESIZE
	313	cmp r0, r1
	314	blo 1b
	315	#endif
	316	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	317	mov pc, lr
	318
a9c9147e RK	319	/*
	320	* dma_map_area(start, size, dir)
	321	* - start - kernel virtual start address
	322	* - size - size of region
	323	* - dir - DMA direction
	324	*/
	325	ENTRY(arm1020e_dma_map_area)
	326	add r1, r1, r0
	327	cmp r2, #DMA_TO_DEVICE
	328	beq arm1020e_dma_clean_range
	329	bcs arm1020e_dma_inv_range
	330	b arm1020e_dma_flush_range
	331	ENDPROC(arm1020e_dma_map_area)
	332
	333	/*
	334	* dma_unmap_area(start, size, dir)
	335	* - start - kernel virtual start address
	336	* - size - size of region
	337	* - dir - DMA direction
	338	*/
	339	ENTRY(arm1020e_dma_unmap_area)
	340	mov pc, lr
	341	ENDPROC(arm1020e_dma_unmap_area)
	342
1da177e4 LT	343	ENTRY(arm1020e_cache_fns)
	344	.long arm1020e_flush_kern_cache_all
	345	.long arm1020e_flush_user_cache_all
	346	.long arm1020e_flush_user_cache_range
	347	.long arm1020e_coherent_kern_range
	348	.long arm1020e_coherent_user_range
2c9b9c84	349	.long arm1020e_flush_kern_dcache_area
a9c9147e RK	350	.long arm1020e_dma_map_area
a9c9147e RK	351	.long arm1020e_dma_unmap_area
1da177e4 LT	352	.long arm1020e_dma_flush_range
	353
	354	.align 5
	355	ENTRY(cpu_arm1020e_dcache_clean_area)
	356	#ifndef CONFIG_CPU_DCACHE_DISABLE
	357	mov ip, #0
	358	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	359	add r0, r0, #CACHE_DLINESIZE
	360	subs r1, r1, #CACHE_DLINESIZE
	361	bhi 1b
	362	#endif
	363	mov pc, lr
	364
	365	/* =============================== PageTable ============================== */
	366
	367	/*
	368	* cpu_arm1020e_switch_mm(pgd)
	369	*
	370	* Set the translation base pointer to be as described by pgd.
	371	*
	372	* pgd: new page tables
	373	*/
	374	.align 5
	375	ENTRY(cpu_arm1020e_switch_mm)
d090ddda	376	#ifdef CONFIG_MMU
1da177e4 LT	377	#ifndef CONFIG_CPU_DCACHE_DISABLE
	378	mcr p15, 0, r3, c7, c10, 4
	379	mov r1, #0xF @ 16 segments
	380	1: mov r3, #0x3F @ 64 entries
	381	2: mov ip, r3, LSL #26 @ shift up entry
	382	orr ip, ip, r1, LSL #5 @ shift in/up index
	383	mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
	384	mov ip, #0
	385	subs r3, r3, #1
	386	cmp r3, #0
	387	bge 2b @ entries 3F to 0
	388	subs r1, r1, #1
	389	cmp r1, #0
	390	bge 1b @ segments 15 to 0
	391
	392	#endif
	393	mov r1, #0
	394	#ifndef CONFIG_CPU_ICACHE_DISABLE
	395	mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
	396	#endif
	397	mcr p15, 0, r1, c7, c10, 4 @ drain WB
	398	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	399	mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	400	#endif
1da177e4 LT	401	mov pc, lr
	402
	403	/*
	404	* cpu_arm1020e_set_pte(ptep, pte)
	405	*
	406	* Set a PTE and flush it out
	407	*/
	408	.align 5
ad1ae2fe	409	ENTRY(cpu_arm1020e_set_pte_ext)
d090ddda	410	#ifdef CONFIG_MMU
da091653	411	armv3_set_pte_ext
1da177e4 LT	412	mov r0, r0
	413	#ifndef CONFIG_CPU_DCACHE_DISABLE
	414	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	415	#endif
d090ddda	416	#endif /* CONFIG_MMU */
1da177e4 LT	417	mov pc, lr
	418
	419	__INIT
	420
	421	.type __arm1020e_setup, #function
	422	__arm1020e_setup:
	423	mov r0, #0
	424	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	425	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	426	#ifdef CONFIG_MMU
1da177e4	427	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	428	#endif
22b19086 RK	429	adr r5, arm1020e_crval
22b19086 RK	430	ldmia r5, {r5, r6}
1da177e4	431	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	432	bic r0, r0, r5
22b19086	433	orr r0, r0, r6
1da177e4 LT	434	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	435	orr r0, r0, #0x4000 @ .R.. .... .... ....
	436	#endif
	437	mov pc, lr
	438	.size __arm1020e_setup, . - __arm1020e_setup
	439
	440	/*
	441	* R
	442	* .RVI ZFRS BLDP WCAM
abaf48a0	443	* .011 1001 ..11 0101
1da177e4	444	*/
22b19086 RK	445	.type arm1020e_crval, #object
	446	arm1020e_crval:
	447	crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
1da177e4 LT	448
	449	__INITDATA
	450
	451	/*
	452	* Purpose : Function pointers used to access above functions - all calls
	453	* come through these
	454	*/
	455	.type arm1020e_processor_functions, #object
	456	arm1020e_processor_functions:
	457	.word v4t_early_abort
4fb28474	458	.word legacy_pabort
1da177e4 LT	459	.word cpu_arm1020e_proc_init
	460	.word cpu_arm1020e_proc_fin
	461	.word cpu_arm1020e_reset
	462	.word cpu_arm1020e_do_idle
	463	.word cpu_arm1020e_dcache_clean_area
	464	.word cpu_arm1020e_switch_mm
ad1ae2fe	465	.word cpu_arm1020e_set_pte_ext
1da177e4 LT	466	.size arm1020e_processor_functions, . - arm1020e_processor_functions
	467
	468	.section ".rodata"
	469
	470	.type cpu_arch_name, #object
	471	cpu_arch_name:
	472	.asciz "armv5te"
	473	.size cpu_arch_name, . - cpu_arch_name
	474
	475	.type cpu_elf_name, #object
	476	cpu_elf_name:
	477	.asciz "v5"
	478	.size cpu_elf_name, . - cpu_elf_name
	479
	480	.type cpu_arm1020e_name, #object
	481	cpu_arm1020e_name:
264edb35	482	.asciz "ARM1020E"
1da177e4 LT	483	.size cpu_arm1020e_name, . - cpu_arm1020e_name
	484
	485	.align
	486
02b7dd12	487	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	488
	489	.type __arm1020e_proc_info,#object
	490	__arm1020e_proc_info:
	491	.long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
	492	.long 0xff0ffff0
8799ee9f RK	493	.long PMD_TYPE_SECT \| \
	494	PMD_BIT4 \| \
	495	PMD_SECT_AP_WRITE \| \
	496	PMD_SECT_AP_READ
1da177e4 LT	497	.long PMD_TYPE_SECT \| \
	498	PMD_BIT4 \| \
	499	PMD_SECT_AP_WRITE \| \
	500	PMD_SECT_AP_READ
	501	b __arm1020e_setup
	502	.long cpu_arch_name
	503	.long cpu_elf_name
	504	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB \| HWCAP_EDSP
	505	.long cpu_arm1020e_name
	506	.long arm1020e_processor_functions
	507	.long v4wbi_tlb_fns
	508	.long v4wb_user_fns
	509	.long arm1020e_cache_fns
	510	.size __arm1020e_proc_info, . - __arm1020e_proc_info