[net-next-2.6.git] / arch / arm / mm / proc-arm1020e.S

/*
 *  linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
 *
 *  Copyright (C) 2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm1020e.
 *
 *  CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE	32768

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	16

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintainence instructions.
 */
#define CACHE_DLIMIT	32768

	.text
/*
 * cpu_arm1020e_proc_init()
 */
ENTRY(cpu_arm1020e_proc_init)
	mov	pc, lr

/*
 * cpu_arm1020e_proc_fin()
 */
ENTRY(cpu_arm1020e_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000 		@ ...i............
	bic	r0, r0, #0x000e 		@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm1020e_reset(loc)
 *
 * Perform a soft reset of the system.	Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm1020e_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f 		@ ............wcam
	bic	ip, ip, #0x1100 		@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm1020e_do_idle()
 */
	.align	5
ENTRY(cpu_arm1020e_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr

/* ================================= CACHE ================================ */

	.align	5

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm1020e_flush_icache_all)
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
#endif
	mov	pc, lr
ENDPROC(arm1020e_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
ENTRY(arm1020e_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm1020e_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 15 to 0
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags for this space
 */
ENTRY(arm1020e_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

#ifndef CONFIG_CPU_DCACHE_DISABLE
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020e_coherent_kern_range)
	/* FALLTHROUGH */
/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020e_coherent_user_range)
	mov	ip, #0
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm1020e_flush_kern_dcache_area)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020e_dma_inv_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020e_dma_clean_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020e_dma_flush_range)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1020e_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm1020e_dma_clean_range
	bcs	arm1020e_dma_inv_range
	b	arm1020e_dma_flush_range
ENDPROC(arm1020e_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1020e_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm1020e_dma_unmap_area)

ENTRY(arm1020e_cache_fns)
	.long	arm1020e_flush_icache_all
	.long	arm1020e_flush_kern_cache_all
	.long	arm1020e_flush_user_cache_all
	.long	arm1020e_flush_user_cache_range
	.long	arm1020e_coherent_kern_range
	.long	arm1020e_coherent_user_range
	.long	arm1020e_flush_kern_dcache_area
	.long	arm1020e_dma_map_area
	.long	arm1020e_dma_unmap_area
	.long	arm1020e_dma_flush_range

	.align	5
ENTRY(cpu_arm1020e_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	ip, #0
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm1020e_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm1020e_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r3, c7, c10, 4
	mov	r1, #0xF			@ 16 segments
1:	mov	r3, #0x3F			@ 64 entries
2:	mov	ip, r3, LSL #26 		@ shift up entry
	orr	ip, ip, r1, LSL #5		@ shift in/up index
	mcr	p15, 0, ip, c7, c14, 2		@ Clean & Inval DCache entry
	mov	ip, #0
	subs	r3, r3, #1
	cmp	r3, #0
	bge	2b				@ entries 3F to 0
	subs	r1, r1, #1
	cmp	r1, #0
	bge	1b				@ segments 15 to 0

#endif
	mov	r1, #0
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
#endif
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mov	pc, lr
        
/*
 * cpu_arm1020e_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm1020e_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
#endif /* CONFIG_MMU */
	mov	pc, lr

	__CPUINIT

	.type	__arm1020e_setup, #function
__arm1020e_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif
	adr	r5, arm1020e_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm1020e_setup, . - __arm1020e_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 1001 ..11 0101
	 */
	.type	arm1020e_crval, #object
arm1020e_crval:
	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm1020e_processor_functions, #object
arm1020e_processor_functions:
	.word	v4t_early_abort
	.word	legacy_pabort
	.word	cpu_arm1020e_proc_init
	.word	cpu_arm1020e_proc_fin
	.word	cpu_arm1020e_reset
	.word	cpu_arm1020e_do_idle
	.word	cpu_arm1020e_dcache_clean_area
	.word	cpu_arm1020e_switch_mm
	.word	cpu_arm1020e_set_pte_ext
	.size	arm1020e_processor_functions, . - arm1020e_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5te"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_arm1020e_name, #object
cpu_arm1020e_name:
	.asciz	"ARM1020E"
	.size	cpu_arm1020e_name, . - cpu_arm1020e_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm1020e_proc_info,#object
__arm1020e_proc_info:
	.long	0x4105a200			@ ARM 1020TE (Architecture v5TE)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm1020e_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
	.long	cpu_arm1020e_name
	.long	arm1020e_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm1020e_cache_fns
	.size	__arm1020e_proc_info, . - __arm1020e_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
	3	*
	4	* Copyright (C) 2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*
	23	* These are the low level assembler for performing cache and TLB
	24	* functions on the arm1020e.
	25	*
	26	* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
	27	*/
	28	#include <linux/linkage.h>
1da177e4 LT	29	#include <linux/init.h>
1da177e4 LT	30	#include <asm/assembler.h>
e6ae744d	31	#include <asm/asm-offsets.h>
5ec9407d	32	#include <asm/hwcap.h>
74945c86	33	#include <asm/pgtable-hwdef.h>
1da177e4	34	#include <asm/pgtable.h>
1da177e4	35	#include <asm/ptrace.h>
1da177e4	36
00eb0f6b RK	37	#include "proc-macros.S"
00eb0f6b RK	38
1da177e4 LT	39	/*
	40	* This is the maximum size of an area which will be invalidated
	41	* using the single invalidate entry instructions. Anything larger
	42	* than this, and we go for the whole cache.
	43	*
	44	* This value should be chosen such that we choose the cheapest
	45	* alternative.
	46	*/
	47	#define MAX_AREA_SIZE 32768
	48
	49	/*
	50	* The size of one data cache line.
	51	*/
	52	#define CACHE_DLINESIZE 32
	53
	54	/*
	55	* The number of data cache segments.
	56	*/
	57	#define CACHE_DSEGMENTS 16
	58
	59	/*
	60	* The number of lines in a cache segment.
	61	*/
	62	#define CACHE_DENTRIES 64
	63
	64	/*
	65	* This is the size at which it becomes more efficient to
	66	* clean the whole cache, rather than using the individual
	67	* cache line maintainence instructions.
	68	*/
	69	#define CACHE_DLIMIT 32768
	70
	71	.text
	72	/*
	73	* cpu_arm1020e_proc_init()
	74	*/
	75	ENTRY(cpu_arm1020e_proc_init)
	76	mov pc, lr
	77
	78	/*
	79	* cpu_arm1020e_proc_fin()
	80	*/
	81	ENTRY(cpu_arm1020e_proc_fin)
1da177e4 LT	82	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	83	bic r0, r0, #0x1000 @ ...i............
	84	bic r0, r0, #0x000e @ ............wca.
	85	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	86	mov pc, lr
1da177e4 LT	87
	88	/*
	89	* cpu_arm1020e_reset(loc)
	90	*
	91	* Perform a soft reset of the system. Put the CPU into the
	92	* same state as it would be if it had been reset, and branch
	93	* to what would be the reset vector.
	94	*
	95	* loc: location to jump to for soft reset
	96	*/
	97	.align 5
	98	ENTRY(cpu_arm1020e_reset)
	99	mov ip, #0
	100	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	101	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	102	#ifdef CONFIG_MMU
1da177e4	103	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	104	#endif
1da177e4 LT	105	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	106	bic ip, ip, #0x000f @ ............wcam
	107	bic ip, ip, #0x1100 @ ...i...s........
	108	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	109	mov pc, r0
	110
	111	/*
	112	* cpu_arm1020e_do_idle()
	113	*/
	114	.align 5
	115	ENTRY(cpu_arm1020e_do_idle)
	116	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	117	mov pc, lr
	118
	119	/* ================================= CACHE ================================ */
	120
	121	.align 5
c8c90860 MW	122
	123	/*
	124	* flush_icache_all()
	125	*
	126	* Unconditionally clean and invalidate the entire icache.
	127	*/
	128	ENTRY(arm1020e_flush_icache_all)
	129	#ifndef CONFIG_CPU_ICACHE_DISABLE
	130	mov r0, #0
	131	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	132	#endif
	133	mov pc, lr
	134	ENDPROC(arm1020e_flush_icache_all)
	135
1da177e4 LT	136	/*
	137	* flush_user_cache_all()
	138	*
	139	* Invalidate all cache entries in a particular address
	140	* space.
	141	*/
	142	ENTRY(arm1020e_flush_user_cache_all)
	143	/* FALLTHROUGH */
	144	/*
	145	* flush_kern_cache_all()
	146	*
	147	* Clean and invalidate the entire cache.
	148	*/
	149	ENTRY(arm1020e_flush_kern_cache_all)
	150	mov r2, #VM_EXEC
	151	mov ip, #0
	152	__flush_whole_cache:
	153	#ifndef CONFIG_CPU_DCACHE_DISABLE
	154	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	155	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
	156	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	157	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	158	subs r3, r3, #1 << 26
	159	bcs 2b @ entries 63 to 0
	160	subs r1, r1, #1 << 5
	161	bcs 1b @ segments 15 to 0
	162	#endif
	163	tst r2, #VM_EXEC
	164	#ifndef CONFIG_CPU_ICACHE_DISABLE
	165	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	166	#endif
	167	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	168	mov pc, lr
	169
	170	/*
	171	* flush_user_cache_range(start, end, flags)
	172	*
	173	* Invalidate a range of cache entries in the specified
	174	* address space.
	175	*
	176	* - start - start address (inclusive)
	177	* - end - end address (exclusive)
	178	* - flags - vm_flags for this space
	179	*/
	180	ENTRY(arm1020e_flush_user_cache_range)
	181	mov ip, #0
	182	sub r3, r1, r0 @ calculate total size
	183	cmp r3, #CACHE_DLIMIT
	184	bhs __flush_whole_cache
	185
	186	#ifndef CONFIG_CPU_DCACHE_DISABLE
	187	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	188	add r0, r0, #CACHE_DLINESIZE
	189	cmp r0, r1
	190	blo 1b
	191	#endif
	192	tst r2, #VM_EXEC
	193	#ifndef CONFIG_CPU_ICACHE_DISABLE
	194	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	195	#endif
	196	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	197	mov pc, lr
	198
	199	/*
200	* coherent_kern_range(start, end)
201	*
202	* Ensure coherency between the Icache and the Dcache in the
203	* region described by start. If you have non-snooping
204	* Harvard caches, you need to implement this function.
205	*
206	* - start - virtual start address
207	* - end - virtual end address
208	*/
209	ENTRY(arm1020e_coherent_kern_range)
210	/* FALLTHROUGH */
211	/*
212	* coherent_user_range(start, end)
213	*
214	* Ensure coherency between the Icache and the Dcache in the
215	* region described by start. If you have non-snooping
216	* Harvard caches, you need to implement this function.
217	*
218	* - start - virtual start address
219	* - end - virtual end address
220	*/
221	ENTRY(arm1020e_coherent_user_range)
222	mov ip, #0
223	bic r0, r0, #CACHE_DLINESIZE - 1
224	1:
225	#ifndef CONFIG_CPU_DCACHE_DISABLE
226	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
227	#endif
228	#ifndef CONFIG_CPU_ICACHE_DISABLE
229	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
230	#endif
231	add r0, r0, #CACHE_DLINESIZE
232	cmp r0, r1
233	blo 1b
234	mcr p15, 0, ip, c7, c10, 4 @ drain WB
235	mov pc, lr
236
237	/*
2c9b9c84	238	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	239	*
	240	* Ensure no D cache aliasing occurs, either with itself or
	241	* the I cache
	242	*
2c9b9c84 RK	243	* - addr - kernel address
2c9b9c84 RK	244	* - size - region size
1da177e4	245	*/
2c9b9c84	246	ENTRY(arm1020e_flush_kern_dcache_area)
1da177e4 LT	247	mov ip, #0
1da177e4 LT	248	#ifndef CONFIG_CPU_DCACHE_DISABLE
2c9b9c84	249	add r1, r0, r1
1da177e4 LT	250	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	251	add r0, r0, #CACHE_DLINESIZE
	252	cmp r0, r1
	253	blo 1b
	254	#endif
	255	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	256	mov pc, lr
	257
	258	/*
	259	* dma_inv_range(start, end)
	260	*
	261	* Invalidate (discard) the specified virtual address range.
	262	* May not write back any entries. If 'start' or 'end'
	263	* are not cache line aligned, those lines must be written
	264	* back.
	265	*
	266	* - start - virtual start address
	267	* - end - virtual end address
	268	*
	269	* (same as v4wb)
	270	*/
702b94bf	271	arm1020e_dma_inv_range:
1da177e4 LT	272	mov ip, #0
	273	#ifndef CONFIG_CPU_DCACHE_DISABLE
	274	tst r0, #CACHE_DLINESIZE - 1
	275	bic r0, r0, #CACHE_DLINESIZE - 1
	276	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	277	tst r1, #CACHE_DLINESIZE - 1
	278	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	279	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	280	add r0, r0, #CACHE_DLINESIZE
	281	cmp r0, r1
	282	blo 1b
	283	#endif
	284	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	285	mov pc, lr
	286
	287	/*
	288	* dma_clean_range(start, end)
	289	*
	290	* Clean the specified virtual address range.
	291	*
	292	* - start - virtual start address
	293	* - end - virtual end address
	294	*
	295	* (same as v4wb)
	296	*/
702b94bf	297	arm1020e_dma_clean_range:
1da177e4 LT	298	mov ip, #0
	299	#ifndef CONFIG_CPU_DCACHE_DISABLE
	300	bic r0, r0, #CACHE_DLINESIZE - 1
	301	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	302	add r0, r0, #CACHE_DLINESIZE
	303	cmp r0, r1
	304	blo 1b
	305	#endif
	306	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	307	mov pc, lr
	308
	309	/*
	310	* dma_flush_range(start, end)
	311	*
	312	* Clean and invalidate the specified virtual address range.
	313	*
	314	* - start - virtual start address
	315	* - end - virtual end address
	316	*/
	317	ENTRY(arm1020e_dma_flush_range)
	318	mov ip, #0
	319	#ifndef CONFIG_CPU_DCACHE_DISABLE
	320	bic r0, r0, #CACHE_DLINESIZE - 1
	321	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	322	add r0, r0, #CACHE_DLINESIZE
	323	cmp r0, r1
	324	blo 1b
	325	#endif
	326	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	327	mov pc, lr
	328
a9c9147e RK	329	/*
	330	* dma_map_area(start, size, dir)
	331	* - start - kernel virtual start address
	332	* - size - size of region
	333	* - dir - DMA direction
	334	*/
	335	ENTRY(arm1020e_dma_map_area)
	336	add r1, r1, r0
	337	cmp r2, #DMA_TO_DEVICE
	338	beq arm1020e_dma_clean_range
	339	bcs arm1020e_dma_inv_range
	340	b arm1020e_dma_flush_range
	341	ENDPROC(arm1020e_dma_map_area)
	342
	343	/*
	344	* dma_unmap_area(start, size, dir)
	345	* - start - kernel virtual start address
	346	* - size - size of region
	347	* - dir - DMA direction
	348	*/
	349	ENTRY(arm1020e_dma_unmap_area)
	350	mov pc, lr
	351	ENDPROC(arm1020e_dma_unmap_area)
	352
1da177e4	353	ENTRY(arm1020e_cache_fns)
c8c90860	354	.long arm1020e_flush_icache_all
1da177e4 LT	355	.long arm1020e_flush_kern_cache_all
	356	.long arm1020e_flush_user_cache_all
	357	.long arm1020e_flush_user_cache_range
	358	.long arm1020e_coherent_kern_range
	359	.long arm1020e_coherent_user_range
2c9b9c84	360	.long arm1020e_flush_kern_dcache_area
a9c9147e RK	361	.long arm1020e_dma_map_area
a9c9147e RK	362	.long arm1020e_dma_unmap_area
1da177e4 LT	363	.long arm1020e_dma_flush_range
	364
	365	.align 5
	366	ENTRY(cpu_arm1020e_dcache_clean_area)
	367	#ifndef CONFIG_CPU_DCACHE_DISABLE
	368	mov ip, #0
	369	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	370	add r0, r0, #CACHE_DLINESIZE
	371	subs r1, r1, #CACHE_DLINESIZE
	372	bhi 1b
	373	#endif
	374	mov pc, lr
	375
	376	/* =============================== PageTable ============================== */
	377
	378	/*
	379	* cpu_arm1020e_switch_mm(pgd)
	380	*
	381	* Set the translation base pointer to be as described by pgd.
	382	*
	383	* pgd: new page tables
	384	*/
	385	.align 5
	386	ENTRY(cpu_arm1020e_switch_mm)
d090ddda	387	#ifdef CONFIG_MMU
1da177e4 LT	388	#ifndef CONFIG_CPU_DCACHE_DISABLE
	389	mcr p15, 0, r3, c7, c10, 4
	390	mov r1, #0xF @ 16 segments
	391	1: mov r3, #0x3F @ 64 entries
	392	2: mov ip, r3, LSL #26 @ shift up entry
	393	orr ip, ip, r1, LSL #5 @ shift in/up index
	394	mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
	395	mov ip, #0
	396	subs r3, r3, #1
	397	cmp r3, #0
	398	bge 2b @ entries 3F to 0
	399	subs r1, r1, #1
	400	cmp r1, #0
	401	bge 1b @ segments 15 to 0
	402
	403	#endif
	404	mov r1, #0
	405	#ifndef CONFIG_CPU_ICACHE_DISABLE
	406	mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
	407	#endif
	408	mcr p15, 0, r1, c7, c10, 4 @ drain WB
	409	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	410	mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	411	#endif
1da177e4 LT	412	mov pc, lr
	413
	414	/*
	415	* cpu_arm1020e_set_pte(ptep, pte)
	416	*
	417	* Set a PTE and flush it out
	418	*/
	419	.align 5
ad1ae2fe	420	ENTRY(cpu_arm1020e_set_pte_ext)
d090ddda	421	#ifdef CONFIG_MMU
da091653	422	armv3_set_pte_ext
1da177e4 LT	423	mov r0, r0
	424	#ifndef CONFIG_CPU_DCACHE_DISABLE
	425	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	426	#endif
d090ddda	427	#endif /* CONFIG_MMU */
1da177e4 LT	428	mov pc, lr
1da177e4 LT	429
5085f3ff	430	__CPUINIT
1da177e4 LT	431
	432	.type __arm1020e_setup, #function
	433	__arm1020e_setup:
	434	mov r0, #0
	435	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	436	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	437	#ifdef CONFIG_MMU
1da177e4	438	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	439	#endif
22b19086 RK	440	adr r5, arm1020e_crval
22b19086 RK	441	ldmia r5, {r5, r6}
1da177e4	442	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	443	bic r0, r0, r5
22b19086	444	orr r0, r0, r6
1da177e4 LT	445	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	446	orr r0, r0, #0x4000 @ .R.. .... .... ....
	447	#endif
	448	mov pc, lr
	449	.size __arm1020e_setup, . - __arm1020e_setup
	450
	451	/*
	452	* R
	453	* .RVI ZFRS BLDP WCAM
abaf48a0	454	* .011 1001 ..11 0101
1da177e4	455	*/
22b19086 RK	456	.type arm1020e_crval, #object
	457	arm1020e_crval:
	458	crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
1da177e4 LT	459
	460	__INITDATA
	461
	462	/*
	463	* Purpose : Function pointers used to access above functions - all calls
	464	* come through these
	465	*/
	466	.type arm1020e_processor_functions, #object
	467	arm1020e_processor_functions:
	468	.word v4t_early_abort
4fb28474	469	.word legacy_pabort
1da177e4 LT	470	.word cpu_arm1020e_proc_init
	471	.word cpu_arm1020e_proc_fin
	472	.word cpu_arm1020e_reset
	473	.word cpu_arm1020e_do_idle
	474	.word cpu_arm1020e_dcache_clean_area
	475	.word cpu_arm1020e_switch_mm
ad1ae2fe	476	.word cpu_arm1020e_set_pte_ext
1da177e4 LT	477	.size arm1020e_processor_functions, . - arm1020e_processor_functions
	478
	479	.section ".rodata"
	480
	481	.type cpu_arch_name, #object
	482	cpu_arch_name:
	483	.asciz "armv5te"
	484	.size cpu_arch_name, . - cpu_arch_name
	485
	486	.type cpu_elf_name, #object
	487	cpu_elf_name:
	488	.asciz "v5"
	489	.size cpu_elf_name, . - cpu_elf_name
	490
	491	.type cpu_arm1020e_name, #object
	492	cpu_arm1020e_name:
264edb35	493	.asciz "ARM1020E"
1da177e4 LT	494	.size cpu_arm1020e_name, . - cpu_arm1020e_name
	495
	496	.align
	497
02b7dd12	498	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	499
	500	.type __arm1020e_proc_info,#object
	501	__arm1020e_proc_info:
	502	.long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
	503	.long 0xff0ffff0
8799ee9f RK	504	.long PMD_TYPE_SECT \| \
	505	PMD_BIT4 \| \
	506	PMD_SECT_AP_WRITE \| \
	507	PMD_SECT_AP_READ
1da177e4 LT	508	.long PMD_TYPE_SECT \| \
	509	PMD_BIT4 \| \
	510	PMD_SECT_AP_WRITE \| \
	511	PMD_SECT_AP_READ
	512	b __arm1020e_setup
	513	.long cpu_arch_name
	514	.long cpu_elf_name
	515	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB \| HWCAP_EDSP
	516	.long cpu_arm1020e_name
	517	.long arm1020e_processor_functions
	518	.long v4wbi_tlb_fns
	519	.long v4wb_user_fns
	520	.long arm1020e_cache_fns
	521	.size __arm1020e_proc_info, . - __arm1020e_proc_info