[net-next-2.6.git] / arch / arm / mm / cache-v4.S

/*
 *  linux/arch/arm/mm/cache-v4.S
 *
 *  Copyright (C) 1997-2002 Russell king
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/page.h>
#include "proc-macros.S"

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 *
 *	- mm	- mm_struct describing address space
 */
ENTRY(v4_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(v4_flush_kern_cache_all)
#ifdef CONFIG_CPU_CP15
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
	mov	pc, lr
#else
	/* FALLTHROUGH */
#endif

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start - start address (may not be aligned)
 *	- end	- end address (exclusive, may not be aligned)
 *	- flags	- vma_area_struct flags describing address space
 */
ENTRY(v4_flush_user_cache_range)
#ifdef CONFIG_CPU_CP15
	mov	ip, #0
	mcreq	p15, 0, ip, c7, c7, 0		@ flush ID cache
	mov	pc, lr
#else
	/* FALLTHROUGH */
#endif

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_coherent_user_range)
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(v4_flush_kern_dcache_area)
	/* FALLTHROUGH */

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_dma_flush_range)
#ifdef CONFIG_CPU_CP15
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
#endif
	mov	pc, lr

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v4_dma_unmap_area)
	teq	r2, #DMA_TO_DEVICE
	bne	v4_dma_flush_range
	/* FALLTHROUGH */

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v4_dma_map_area)
	mov	pc, lr
ENDPROC(v4_dma_unmap_area)
ENDPROC(v4_dma_map_area)

	__INITDATA

	.type	v4_cache_fns, #object
ENTRY(v4_cache_fns)
	.long	v4_flush_kern_cache_all
	.long	v4_flush_user_cache_all
	.long	v4_flush_user_cache_range
	.long	v4_coherent_kern_range
	.long	v4_coherent_user_range
	.long	v4_flush_kern_dcache_area
	.long	v4_dma_map_area
	.long	v4_dma_unmap_area
	.long	v4_dma_flush_range
	.size	v4_cache_fns, . - v4_cache_fns
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/cache-v4.S
	3	*
	4	* Copyright (C) 1997-2002 Russell king
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/linkage.h>
	11	#include <linux/init.h>
1da177e4 LT	12	#include <asm/page.h>
	13	#include "proc-macros.S"
	14
	15	/*
	16	* flush_user_cache_all()
	17	*
	18	* Invalidate all cache entries in a particular address
	19	* space.
	20	*
	21	* - mm - mm_struct describing address space
	22	*/
	23	ENTRY(v4_flush_user_cache_all)
	24	/* FALLTHROUGH */
	25	/*
	26	* flush_kern_cache_all()
	27	*
	28	* Clean and invalidate the entire cache.
	29	*/
	30	ENTRY(v4_flush_kern_cache_all)
e4d2a598	31	#ifdef CONFIG_CPU_CP15
1da177e4 LT	32	mov r0, #0
	33	mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
	34	mov pc, lr
f12d0d7c HC	35	#else
	36	/* FALLTHROUGH */
	37	#endif
1da177e4 LT	38
	39	/*
	40	* flush_user_cache_range(start, end, flags)
	41	*
	42	* Invalidate a range of cache entries in the specified
	43	* address space.
	44	*
	45	* - start - start address (may not be aligned)
	46	* - end - end address (exclusive, may not be aligned)
	47	* - flags - vma_area_struct flags describing address space
	48	*/
	49	ENTRY(v4_flush_user_cache_range)
e4d2a598	50	#ifdef CONFIG_CPU_CP15
1da177e4 LT	51	mov ip, #0
	52	mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
	53	mov pc, lr
f12d0d7c HC	54	#else
	55	/* FALLTHROUGH */
	56	#endif
1da177e4 LT	57
	58	/*
	59	* coherent_kern_range(start, end)
	60	*
	61	* Ensure coherency between the Icache and the Dcache in the
	62	* region described by start. If you have non-snooping
	63	* Harvard caches, you need to implement this function.
	64	*
	65	* - start - virtual start address
	66	* - end - virtual end address
	67	*/
	68	ENTRY(v4_coherent_kern_range)
	69	/* FALLTHROUGH */
	70
	71	/*
	72	* coherent_user_range(start, end)
	73	*
	74	* Ensure coherency between the Icache and the Dcache in the
	75	* region described by start. If you have non-snooping
	76	* Harvard caches, you need to implement this function.
	77	*
	78	* - start - virtual start address
	79	* - end - virtual end address
	80	*/
	81	ENTRY(v4_coherent_user_range)
	82	mov pc, lr
	83
	84	/*
2c9b9c84	85	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	86	*
	87	* Ensure no D cache aliasing occurs, either with itself or
	88	* the I cache
	89	*
2c9b9c84 RK	90	* - addr - kernel address
2c9b9c84 RK	91	* - size - region size
1da177e4	92	*/
2c9b9c84	93	ENTRY(v4_flush_kern_dcache_area)
1da177e4 LT	94	/* FALLTHROUGH */
1da177e4 LT	95
1da177e4 LT	96	/*
	97	* dma_flush_range(start, end)
	98	*
	99	* Clean and invalidate the specified virtual address range.
	100	*
	101	* - start - virtual start address
	102	* - end - virtual end address
	103	*/
	104	ENTRY(v4_dma_flush_range)
e4d2a598	105	#ifdef CONFIG_CPU_CP15
1da177e4 LT	106	mov r0, #0
1da177e4 LT	107	mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
f12d0d7c	108	#endif
1da177e4 LT	109	mov pc, lr
1da177e4 LT	110
a9c9147e RK	111	/*
	112	* dma_unmap_area(start, size, dir)
	113	* - start - kernel virtual start address
	114	* - size - size of region
	115	* - dir - DMA direction
	116	*/
	117	ENTRY(v4_dma_unmap_area)
	118	teq r2, #DMA_TO_DEVICE
702b94bf	119	bne v4_dma_flush_range
a9c9147e RK	120	/* FALLTHROUGH */
	121
	122	/*
	123	* dma_map_area(start, size, dir)
	124	* - start - kernel virtual start address
	125	* - size - size of region
	126	* - dir - DMA direction
	127	*/
	128	ENTRY(v4_dma_map_area)
	129	mov pc, lr
	130	ENDPROC(v4_dma_unmap_area)
	131	ENDPROC(v4_dma_map_area)
	132
1da177e4 LT	133	__INITDATA
	134
	135	.type v4_cache_fns, #object
	136	ENTRY(v4_cache_fns)
	137	.long v4_flush_kern_cache_all
	138	.long v4_flush_user_cache_all
	139	.long v4_flush_user_cache_range
	140	.long v4_coherent_kern_range
	141	.long v4_coherent_user_range
2c9b9c84	142	.long v4_flush_kern_dcache_area
a9c9147e RK	143	.long v4_dma_map_area
a9c9147e RK	144	.long v4_dma_unmap_area
1da177e4 LT	145	.long v4_dma_flush_range
1da177e4 LT	146	.size v4_cache_fns, . - v4_cache_fns