[net-next-2.6.git] / arch / arm / mm / cache-v4.S

/*
 *  linux/arch/arm/mm/cache-v4.S
 *
 *  Copyright (C) 1997-2002 Russell king
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/page.h>
#include "proc-macros.S"

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(v4_flush_icache_all)
	mov	pc, lr
ENDPROC(v4_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 *
 *	- mm	- mm_struct describing address space
 */
ENTRY(v4_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(v4_flush_kern_cache_all)
#ifdef CONFIG_CPU_CP15
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
	mov	pc, lr
#else
	/* FALLTHROUGH */
#endif

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start - start address (may not be aligned)
 *	- end	- end address (exclusive, may not be aligned)
 *	- flags	- vma_area_struct flags describing address space
 */
ENTRY(v4_flush_user_cache_range)
#ifdef CONFIG_CPU_CP15
	mov	ip, #0
	mcreq	p15, 0, ip, c7, c7, 0		@ flush ID cache
	mov	pc, lr
#else
	/* FALLTHROUGH */
#endif

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_coherent_user_range)
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(v4_flush_kern_dcache_area)
	/* FALLTHROUGH */

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(v4_dma_flush_range)
#ifdef CONFIG_CPU_CP15
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
#endif
	mov	pc, lr

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v4_dma_unmap_area)
	teq	r2, #DMA_TO_DEVICE
	bne	v4_dma_flush_range
	/* FALLTHROUGH */

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(v4_dma_map_area)
	mov	pc, lr
ENDPROC(v4_dma_unmap_area)
ENDPROC(v4_dma_map_area)

	__INITDATA

	.type	v4_cache_fns, #object
ENTRY(v4_cache_fns)
	.long	v4_flush_icache_all
	.long	v4_flush_kern_cache_all
	.long	v4_flush_user_cache_all
	.long	v4_flush_user_cache_range
	.long	v4_coherent_kern_range
	.long	v4_coherent_user_range
	.long	v4_flush_kern_dcache_area
	.long	v4_dma_map_area
	.long	v4_dma_unmap_area
	.long	v4_dma_flush_range
	.size	v4_cache_fns, . - v4_cache_fns
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/cache-v4.S
	3	*
	4	* Copyright (C) 1997-2002 Russell king
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#include <linux/linkage.h>
	11	#include <linux/init.h>
1da177e4 LT	12	#include <asm/page.h>
	13	#include "proc-macros.S"
	14
c8c90860 MW	15	/*
	16	* flush_icache_all()
	17	*
	18	* Unconditionally clean and invalidate the entire icache.
	19	*/
	20	ENTRY(v4_flush_icache_all)
	21	mov pc, lr
	22	ENDPROC(v4_flush_icache_all)
	23
1da177e4 LT	24	/*
	25	* flush_user_cache_all()
	26	*
	27	* Invalidate all cache entries in a particular address
	28	* space.
	29	*
	30	* - mm - mm_struct describing address space
	31	*/
	32	ENTRY(v4_flush_user_cache_all)
	33	/* FALLTHROUGH */
	34	/*
	35	* flush_kern_cache_all()
	36	*
	37	* Clean and invalidate the entire cache.
	38	*/
	39	ENTRY(v4_flush_kern_cache_all)
e4d2a598	40	#ifdef CONFIG_CPU_CP15
1da177e4 LT	41	mov r0, #0
	42	mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
	43	mov pc, lr
f12d0d7c HC	44	#else
	45	/* FALLTHROUGH */
	46	#endif
1da177e4 LT	47
	48	/*
	49	* flush_user_cache_range(start, end, flags)
	50	*
	51	* Invalidate a range of cache entries in the specified
	52	* address space.
	53	*
	54	* - start - start address (may not be aligned)
	55	* - end - end address (exclusive, may not be aligned)
	56	* - flags - vma_area_struct flags describing address space
	57	*/
	58	ENTRY(v4_flush_user_cache_range)
e4d2a598	59	#ifdef CONFIG_CPU_CP15
1da177e4 LT	60	mov ip, #0
	61	mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
	62	mov pc, lr
f12d0d7c HC	63	#else
	64	/* FALLTHROUGH */
	65	#endif
1da177e4 LT	66
	67	/*
	68	* coherent_kern_range(start, end)
	69	*
	70	* Ensure coherency between the Icache and the Dcache in the
	71	* region described by start. If you have non-snooping
	72	* Harvard caches, you need to implement this function.
	73	*
	74	* - start - virtual start address
	75	* - end - virtual end address
	76	*/
	77	ENTRY(v4_coherent_kern_range)
	78	/* FALLTHROUGH */
	79
	80	/*
	81	* coherent_user_range(start, end)
	82	*
	83	* Ensure coherency between the Icache and the Dcache in the
	84	* region described by start. If you have non-snooping
	85	* Harvard caches, you need to implement this function.
	86	*
	87	* - start - virtual start address
	88	* - end - virtual end address
	89	*/
	90	ENTRY(v4_coherent_user_range)
	91	mov pc, lr
	92
	93	/*
2c9b9c84	94	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	95	*
	96	* Ensure no D cache aliasing occurs, either with itself or
	97	* the I cache
	98	*
2c9b9c84 RK	99	* - addr - kernel address
2c9b9c84 RK	100	* - size - region size
1da177e4	101	*/
2c9b9c84	102	ENTRY(v4_flush_kern_dcache_area)
1da177e4 LT	103	/* FALLTHROUGH */
1da177e4 LT	104
1da177e4 LT	105	/*
	106	* dma_flush_range(start, end)
	107	*
	108	* Clean and invalidate the specified virtual address range.
	109	*
	110	* - start - virtual start address
	111	* - end - virtual end address
	112	*/
	113	ENTRY(v4_dma_flush_range)
e4d2a598	114	#ifdef CONFIG_CPU_CP15
1da177e4 LT	115	mov r0, #0
1da177e4 LT	116	mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
f12d0d7c	117	#endif
1da177e4 LT	118	mov pc, lr
1da177e4 LT	119
a9c9147e RK	120	/*
	121	* dma_unmap_area(start, size, dir)
	122	* - start - kernel virtual start address
	123	* - size - size of region
	124	* - dir - DMA direction
	125	*/
	126	ENTRY(v4_dma_unmap_area)
	127	teq r2, #DMA_TO_DEVICE
702b94bf	128	bne v4_dma_flush_range
a9c9147e RK	129	/* FALLTHROUGH */
	130
	131	/*
	132	* dma_map_area(start, size, dir)
	133	* - start - kernel virtual start address
	134	* - size - size of region
	135	* - dir - DMA direction
	136	*/
	137	ENTRY(v4_dma_map_area)
	138	mov pc, lr
	139	ENDPROC(v4_dma_unmap_area)
	140	ENDPROC(v4_dma_map_area)
	141
1da177e4 LT	142	__INITDATA
	143
	144	.type v4_cache_fns, #object
	145	ENTRY(v4_cache_fns)
c8c90860	146	.long v4_flush_icache_all
1da177e4 LT	147	.long v4_flush_kern_cache_all
	148	.long v4_flush_user_cache_all
	149	.long v4_flush_user_cache_range
	150	.long v4_coherent_kern_range
	151	.long v4_coherent_user_range
2c9b9c84	152	.long v4_flush_kern_dcache_area
a9c9147e RK	153	.long v4_dma_map_area
a9c9147e RK	154	.long v4_dma_unmap_area
1da177e4 LT	155	.long v4_dma_flush_range
1da177e4 LT	156	.size v4_cache_fns, . - v4_cache_fns