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Commit | Line | Data |
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1da177e4 LT |
1 | comment "Processor Type" |
2 | ||
3 | config CPU_32 | |
4 | bool | |
5 | default y | |
6 | ||
7 | # Select CPU types depending on the architecture selected. This selects | |
8 | # which CPUs we support in the kernel image, and the compiler instruction | |
9 | # optimiser behaviour. | |
10 | ||
11 | # ARM610 | |
12 | config CPU_ARM610 | |
13 | bool "Support ARM610 processor" | |
14 | depends on ARCH_RPC | |
15 | select CPU_32v3 | |
16 | select CPU_CACHE_V3 | |
17 | select CPU_CACHE_VIVT | |
fefdaa06 | 18 | select CPU_CP15_MMU |
f9c21a6e HC |
19 | select CPU_COPY_V3 if MMU |
20 | select CPU_TLB_V3 if MMU | |
48d7927b | 21 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
22 | help |
23 | The ARM610 is the successor to the ARM3 processor | |
24 | and was produced by VLSI Technology Inc. | |
25 | ||
26 | Say Y if you want support for the ARM610 processor. | |
27 | Otherwise, say N. | |
28 | ||
07e0da78 HC |
29 | # ARM7TDMI |
30 | config CPU_ARM7TDMI | |
31 | bool "Support ARM7TDMI processor" | |
6b237a35 | 32 | depends on !MMU |
07e0da78 HC |
33 | select CPU_32v4T |
34 | select CPU_ABRT_LV4T | |
4a1fd556 | 35 | select CPU_PABRT_NOIFAR |
07e0da78 HC |
36 | select CPU_CACHE_V4 |
37 | help | |
38 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
39 | which has no memory control unit and cache. | |
40 | ||
41 | Say Y if you want support for the ARM7TDMI processor. | |
42 | Otherwise, say N. | |
43 | ||
1da177e4 LT |
44 | # ARM710 |
45 | config CPU_ARM710 | |
46 | bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC | |
47 | default y if ARCH_CLPS7500 | |
48 | select CPU_32v3 | |
49 | select CPU_CACHE_V3 | |
50 | select CPU_CACHE_VIVT | |
fefdaa06 | 51 | select CPU_CP15_MMU |
f9c21a6e HC |
52 | select CPU_COPY_V3 if MMU |
53 | select CPU_TLB_V3 if MMU | |
48d7927b | 54 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
55 | help |
56 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
57 | designed by Advanced RISC Machines Ltd. The ARM710 is the | |
58 | successor to the ARM610 processor. It was released in | |
59 | July 1994 by VLSI Technology Inc. | |
60 | ||
61 | Say Y if you want support for the ARM710 processor. | |
62 | Otherwise, say N. | |
63 | ||
64 | # ARM720T | |
65 | config CPU_ARM720T | |
66 | bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR | |
67 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X | |
260e98ed | 68 | select CPU_32v4T |
1da177e4 | 69 | select CPU_ABRT_LV4T |
48d7927b | 70 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
71 | select CPU_CACHE_V4 |
72 | select CPU_CACHE_VIVT | |
fefdaa06 | 73 | select CPU_CP15_MMU |
f9c21a6e HC |
74 | select CPU_COPY_V4WT if MMU |
75 | select CPU_TLB_V4WT if MMU | |
1da177e4 LT |
76 | help |
77 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | |
78 | MMU built around an ARM7TDMI core. | |
79 | ||
80 | Say Y if you want support for the ARM720T processor. | |
81 | Otherwise, say N. | |
82 | ||
b731c311 HC |
83 | # ARM740T |
84 | config CPU_ARM740T | |
85 | bool "Support ARM740T processor" if ARCH_INTEGRATOR | |
6b237a35 | 86 | depends on !MMU |
b731c311 HC |
87 | select CPU_32v4T |
88 | select CPU_ABRT_LV4T | |
4a1fd556 | 89 | select CPU_PABRT_NOIFAR |
b731c311 HC |
90 | select CPU_CACHE_V3 # although the core is v4t |
91 | select CPU_CP15_MPU | |
92 | help | |
93 | A 32-bit RISC processor with 8KB cache or 4KB variants, | |
94 | write buffer and MPU(Protection Unit) built around | |
95 | an ARM7TDMI core. | |
96 | ||
97 | Say Y if you want support for the ARM740T processor. | |
98 | Otherwise, say N. | |
99 | ||
43f5f014 HC |
100 | # ARM9TDMI |
101 | config CPU_ARM9TDMI | |
102 | bool "Support ARM9TDMI processor" | |
6b237a35 | 103 | depends on !MMU |
43f5f014 | 104 | select CPU_32v4T |
0f45d7f3 | 105 | select CPU_ABRT_NOMMU |
4a1fd556 | 106 | select CPU_PABRT_NOIFAR |
43f5f014 HC |
107 | select CPU_CACHE_V4 |
108 | help | |
109 | A 32-bit RISC microprocessor based on the ARM9 processor core | |
110 | which has no memory control unit and cache. | |
111 | ||
112 | Say Y if you want support for the ARM9TDMI processor. | |
113 | Otherwise, say N. | |
114 | ||
1da177e4 LT |
115 | # ARM920T |
116 | config CPU_ARM920T | |
3434d9d9 BD |
117 | bool "Support ARM920T processor" |
118 | depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 | |
119 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 | |
260e98ed | 120 | select CPU_32v4T |
1da177e4 | 121 | select CPU_ABRT_EV4T |
48d7927b | 122 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
123 | select CPU_CACHE_V4WT |
124 | select CPU_CACHE_VIVT | |
fefdaa06 | 125 | select CPU_CP15_MMU |
f9c21a6e HC |
126 | select CPU_COPY_V4WB if MMU |
127 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
128 | help |
129 | The ARM920T is licensed to be produced by numerous vendors, | |
130 | and is used in the Maverick EP9312 and the Samsung S3C2410. | |
131 | ||
132 | More information on the Maverick EP9312 at | |
133 | <http://linuxdevices.com/products/PD2382866068.html>. | |
134 | ||
135 | Say Y if you want support for the ARM920T processor. | |
136 | Otherwise, say N. | |
137 | ||
138 | # ARM922T | |
139 | config CPU_ARM922T | |
140 | bool "Support ARM922T processor" if ARCH_INTEGRATOR | |
c53c9cf6 AV |
141 | depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695 |
142 | default y if ARCH_LH7A40X || ARCH_KS8695 | |
260e98ed | 143 | select CPU_32v4T |
1da177e4 | 144 | select CPU_ABRT_EV4T |
48d7927b | 145 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
146 | select CPU_CACHE_V4WT |
147 | select CPU_CACHE_VIVT | |
fefdaa06 | 148 | select CPU_CP15_MMU |
f9c21a6e HC |
149 | select CPU_COPY_V4WB if MMU |
150 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
151 | help |
152 | The ARM922T is a version of the ARM920T, but with smaller | |
153 | instruction and data caches. It is used in Altera's | |
c53c9cf6 | 154 | Excalibur XA device family and Micrel's KS8695 Centaur. |
1da177e4 LT |
155 | |
156 | Say Y if you want support for the ARM922T processor. | |
157 | Otherwise, say N. | |
158 | ||
159 | # ARM925T | |
160 | config CPU_ARM925T | |
b288f75f | 161 | bool "Support ARM925T processor" if ARCH_OMAP1 |
3179a019 TL |
162 | depends on ARCH_OMAP15XX |
163 | default y if ARCH_OMAP15XX | |
260e98ed | 164 | select CPU_32v4T |
1da177e4 | 165 | select CPU_ABRT_EV4T |
48d7927b | 166 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
167 | select CPU_CACHE_V4WT |
168 | select CPU_CACHE_VIVT | |
fefdaa06 | 169 | select CPU_CP15_MMU |
f9c21a6e HC |
170 | select CPU_COPY_V4WB if MMU |
171 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
172 | help |
173 | The ARM925T is a mix between the ARM920T and ARM926T, but with | |
174 | different instruction and data caches. It is used in TI's OMAP | |
175 | device family. | |
176 | ||
177 | Say Y if you want support for the ARM925T processor. | |
178 | Otherwise, say N. | |
179 | ||
180 | # ARM926T | |
181 | config CPU_ARM926T | |
8ad68bbf | 182 | bool "Support ARM926T processor" |
2b3b3516 AV |
183 | depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI |
184 | default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI | |
1da177e4 LT |
185 | select CPU_32v5 |
186 | select CPU_ABRT_EV5TJ | |
48d7927b | 187 | select CPU_PABRT_NOIFAR |
1da177e4 | 188 | select CPU_CACHE_VIVT |
fefdaa06 | 189 | select CPU_CP15_MMU |
f9c21a6e HC |
190 | select CPU_COPY_V4WB if MMU |
191 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
192 | help |
193 | This is a variant of the ARM920. It has slightly different | |
194 | instruction sequences for cache and TLB operations. Curiously, | |
195 | there is no documentation on it at the ARM corporate website. | |
196 | ||
197 | Say Y if you want support for the ARM926T processor. | |
198 | Otherwise, say N. | |
199 | ||
d60674eb HC |
200 | # ARM940T |
201 | config CPU_ARM940T | |
202 | bool "Support ARM940T processor" if ARCH_INTEGRATOR | |
6b237a35 | 203 | depends on !MMU |
d60674eb | 204 | select CPU_32v4T |
0f45d7f3 | 205 | select CPU_ABRT_NOMMU |
4a1fd556 | 206 | select CPU_PABRT_NOIFAR |
d60674eb HC |
207 | select CPU_CACHE_VIVT |
208 | select CPU_CP15_MPU | |
209 | help | |
210 | ARM940T is a member of the ARM9TDMI family of general- | |
3cb2fccc | 211 | purpose microprocessors with MPU and separate 4KB |
d60674eb HC |
212 | instruction and 4KB data cases, each with a 4-word line |
213 | length. | |
214 | ||
215 | Say Y if you want support for the ARM940T processor. | |
216 | Otherwise, say N. | |
217 | ||
f37f46eb HC |
218 | # ARM946E-S |
219 | config CPU_ARM946E | |
220 | bool "Support ARM946E-S processor" if ARCH_INTEGRATOR | |
6b237a35 | 221 | depends on !MMU |
f37f46eb | 222 | select CPU_32v5 |
0f45d7f3 | 223 | select CPU_ABRT_NOMMU |
4a1fd556 | 224 | select CPU_PABRT_NOIFAR |
f37f46eb HC |
225 | select CPU_CACHE_VIVT |
226 | select CPU_CP15_MPU | |
227 | help | |
228 | ARM946E-S is a member of the ARM9E-S family of high- | |
229 | performance, 32-bit system-on-chip processor solutions. | |
230 | The TCM and ARMv5TE 32-bit instruction set is supported. | |
231 | ||
232 | Say Y if you want support for the ARM946E-S processor. | |
233 | Otherwise, say N. | |
234 | ||
1da177e4 LT |
235 | # ARM1020 - needs validating |
236 | config CPU_ARM1020 | |
237 | bool "Support ARM1020T (rev 0) processor" | |
238 | depends on ARCH_INTEGRATOR | |
239 | select CPU_32v5 | |
240 | select CPU_ABRT_EV4T | |
48d7927b | 241 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
242 | select CPU_CACHE_V4WT |
243 | select CPU_CACHE_VIVT | |
fefdaa06 | 244 | select CPU_CP15_MMU |
f9c21a6e HC |
245 | select CPU_COPY_V4WB if MMU |
246 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
247 | help |
248 | The ARM1020 is the 32K cached version of the ARM10 processor, | |
249 | with an addition of a floating-point unit. | |
250 | ||
251 | Say Y if you want support for the ARM1020 processor. | |
252 | Otherwise, say N. | |
253 | ||
254 | # ARM1020E - needs validating | |
255 | config CPU_ARM1020E | |
256 | bool "Support ARM1020E processor" | |
257 | depends on ARCH_INTEGRATOR | |
258 | select CPU_32v5 | |
259 | select CPU_ABRT_EV4T | |
48d7927b | 260 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
261 | select CPU_CACHE_V4WT |
262 | select CPU_CACHE_VIVT | |
fefdaa06 | 263 | select CPU_CP15_MMU |
f9c21a6e HC |
264 | select CPU_COPY_V4WB if MMU |
265 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
266 | depends on n |
267 | ||
268 | # ARM1022E | |
269 | config CPU_ARM1022 | |
270 | bool "Support ARM1022E processor" | |
271 | depends on ARCH_INTEGRATOR | |
272 | select CPU_32v5 | |
273 | select CPU_ABRT_EV4T | |
48d7927b | 274 | select CPU_PABRT_NOIFAR |
1da177e4 | 275 | select CPU_CACHE_VIVT |
fefdaa06 | 276 | select CPU_CP15_MMU |
f9c21a6e HC |
277 | select CPU_COPY_V4WB if MMU # can probably do better |
278 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
279 | help |
280 | The ARM1022E is an implementation of the ARMv5TE architecture | |
281 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, | |
282 | embedded trace macrocell, and a floating-point unit. | |
283 | ||
284 | Say Y if you want support for the ARM1022E processor. | |
285 | Otherwise, say N. | |
286 | ||
287 | # ARM1026EJ-S | |
288 | config CPU_ARM1026 | |
289 | bool "Support ARM1026EJ-S processor" | |
290 | depends on ARCH_INTEGRATOR | |
291 | select CPU_32v5 | |
292 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | |
48d7927b | 293 | select CPU_PABRT_NOIFAR |
1da177e4 | 294 | select CPU_CACHE_VIVT |
fefdaa06 | 295 | select CPU_CP15_MMU |
f9c21a6e HC |
296 | select CPU_COPY_V4WB if MMU # can probably do better |
297 | select CPU_TLB_V4WBI if MMU | |
1da177e4 LT |
298 | help |
299 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | |
300 | based upon the ARM10 integer core. | |
301 | ||
302 | Say Y if you want support for the ARM1026EJ-S processor. | |
303 | Otherwise, say N. | |
304 | ||
305 | # SA110 | |
306 | config CPU_SA110 | |
307 | bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC | |
308 | default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI | |
309 | select CPU_32v3 if ARCH_RPC | |
310 | select CPU_32v4 if !ARCH_RPC | |
311 | select CPU_ABRT_EV4 | |
48d7927b | 312 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
313 | select CPU_CACHE_V4WB |
314 | select CPU_CACHE_VIVT | |
fefdaa06 | 315 | select CPU_CP15_MMU |
f9c21a6e HC |
316 | select CPU_COPY_V4WB if MMU |
317 | select CPU_TLB_V4WB if MMU | |
1da177e4 LT |
318 | help |
319 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | |
320 | is available at five speeds ranging from 100 MHz to 233 MHz. | |
321 | More information is available at | |
322 | <http://developer.intel.com/design/strong/sa110.htm>. | |
323 | ||
324 | Say Y if you want support for the SA-110 processor. | |
325 | Otherwise, say N. | |
326 | ||
327 | # SA1100 | |
328 | config CPU_SA1100 | |
329 | bool | |
330 | depends on ARCH_SA1100 | |
331 | default y | |
332 | select CPU_32v4 | |
333 | select CPU_ABRT_EV4 | |
48d7927b | 334 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
335 | select CPU_CACHE_V4WB |
336 | select CPU_CACHE_VIVT | |
fefdaa06 | 337 | select CPU_CP15_MMU |
f9c21a6e | 338 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
339 | |
340 | # XScale | |
341 | config CPU_XSCALE | |
342 | bool | |
fa0b6251 | 343 | depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000 |
1da177e4 LT |
344 | default y |
345 | select CPU_32v5 | |
346 | select CPU_ABRT_EV5T | |
48d7927b | 347 | select CPU_PABRT_NOIFAR |
1da177e4 | 348 | select CPU_CACHE_VIVT |
fefdaa06 | 349 | select CPU_CP15_MMU |
f9c21a6e | 350 | select CPU_TLB_V4WBI if MMU |
1da177e4 | 351 | |
23bdf86a LB |
352 | # XScale Core Version 3 |
353 | config CPU_XSC3 | |
354 | bool | |
2c8086a5 | 355 | depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx |
23bdf86a LB |
356 | default y |
357 | select CPU_32v5 | |
358 | select CPU_ABRT_EV5T | |
4a1fd556 | 359 | select CPU_PABRT_NOIFAR |
23bdf86a | 360 | select CPU_CACHE_VIVT |
fefdaa06 | 361 | select CPU_CP15_MMU |
f9c21a6e | 362 | select CPU_TLB_V4WBI if MMU |
23bdf86a LB |
363 | select IO_36 |
364 | ||
e50d6409 AH |
365 | # Feroceon |
366 | config CPU_FEROCEON | |
367 | bool | |
651c74c7 | 368 | depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD |
e50d6409 AH |
369 | default y |
370 | select CPU_32v5 | |
371 | select CPU_ABRT_EV5T | |
48d7927b | 372 | select CPU_PABRT_NOIFAR |
e50d6409 AH |
373 | select CPU_CACHE_VIVT |
374 | select CPU_CP15_MMU | |
0ed15071 | 375 | select CPU_COPY_FEROCEON if MMU |
99c6dc11 | 376 | select CPU_TLB_FEROCEON if MMU |
e50d6409 | 377 | |
d910a0aa TP |
378 | config CPU_FEROCEON_OLD_ID |
379 | bool "Accept early Feroceon cores with an ARM926 ID" | |
380 | depends on CPU_FEROCEON && !CPU_ARM926T | |
381 | default y | |
382 | help | |
383 | This enables the usage of some old Feroceon cores | |
384 | for which the CPU ID is equal to the ARM926 ID. | |
385 | Relevant for Feroceon-1850 and early Feroceon-2850. | |
386 | ||
1da177e4 LT |
387 | # ARMv6 |
388 | config CPU_V6 | |
389 | bool "Support ARM V6 processor" | |
bc02c58b | 390 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 |
52c543f9 | 391 | default y if ARCH_MX3 |
3042102a | 392 | default y if ARCH_MSM7X00A |
1da177e4 LT |
393 | select CPU_32v6 |
394 | select CPU_ABRT_EV6 | |
48d7927b | 395 | select CPU_PABRT_NOIFAR |
1da177e4 LT |
396 | select CPU_CACHE_V6 |
397 | select CPU_CACHE_VIPT | |
fefdaa06 | 398 | select CPU_CP15_MMU |
7b4c965a | 399 | select CPU_HAS_ASID if MMU |
f9c21a6e HC |
400 | select CPU_COPY_V6 if MMU |
401 | select CPU_TLB_V6 if MMU | |
1da177e4 | 402 | |
4a5f79e7 RK |
403 | # ARMv6k |
404 | config CPU_32v6K | |
405 | bool "Support ARM V6K processor extensions" if !SMP | |
406 | depends on CPU_V6 | |
52c543f9 | 407 | default y if SMP && !ARCH_MX3 |
4a5f79e7 RK |
408 | help |
409 | Say Y here if your ARMv6 processor supports the 'K' extension. | |
410 | This enables the kernel to use some instructions not present | |
411 | on previous processors, and as such a kernel build with this | |
412 | enabled will not boot on processors with do not support these | |
413 | instructions. | |
414 | ||
23688e99 CM |
415 | # ARMv7 |
416 | config CPU_V7 | |
417 | bool "Support ARM V7 processor" | |
41267e20 | 418 | depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB |
23688e99 CM |
419 | select CPU_32v6K |
420 | select CPU_32v7 | |
421 | select CPU_ABRT_EV7 | |
48d7927b | 422 | select CPU_PABRT_IFAR |
23688e99 CM |
423 | select CPU_CACHE_V7 |
424 | select CPU_CACHE_VIPT | |
425 | select CPU_CP15_MMU | |
2eb8c82b | 426 | select CPU_HAS_ASID if MMU |
23688e99 | 427 | select CPU_COPY_V6 if MMU |
2ccdd1e7 | 428 | select CPU_TLB_V7 if MMU |
23688e99 | 429 | |
1da177e4 LT |
430 | # Figure out what processor architecture version we should be using. |
431 | # This defines the compiler instruction set which depends on the machine type. | |
432 | config CPU_32v3 | |
433 | bool | |
60b6cf68 | 434 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 435 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 LT |
436 | |
437 | config CPU_32v4 | |
438 | bool | |
60b6cf68 | 439 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 440 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 | 441 | |
260e98ed LB |
442 | config CPU_32v4T |
443 | bool | |
444 | select TLS_REG_EMUL if SMP || !MMU | |
445 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | |
446 | ||
1da177e4 LT |
447 | config CPU_32v5 |
448 | bool | |
60b6cf68 | 449 | select TLS_REG_EMUL if SMP || !MMU |
48fa14f7 | 450 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
1da177e4 LT |
451 | |
452 | config CPU_32v6 | |
453 | bool | |
367afaf8 | 454 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
1da177e4 | 455 | |
23688e99 CM |
456 | config CPU_32v7 |
457 | bool | |
458 | ||
1da177e4 | 459 | # The abort model |
0f45d7f3 HC |
460 | config CPU_ABRT_NOMMU |
461 | bool | |
462 | ||
1da177e4 LT |
463 | config CPU_ABRT_EV4 |
464 | bool | |
465 | ||
466 | config CPU_ABRT_EV4T | |
467 | bool | |
468 | ||
469 | config CPU_ABRT_LV4T | |
470 | bool | |
471 | ||
472 | config CPU_ABRT_EV5T | |
473 | bool | |
474 | ||
475 | config CPU_ABRT_EV5TJ | |
476 | bool | |
477 | ||
478 | config CPU_ABRT_EV6 | |
479 | bool | |
480 | ||
23688e99 CM |
481 | config CPU_ABRT_EV7 |
482 | bool | |
483 | ||
48d7927b PB |
484 | config CPU_PABRT_IFAR |
485 | bool | |
486 | ||
487 | config CPU_PABRT_NOIFAR | |
488 | bool | |
489 | ||
1da177e4 LT |
490 | # The cache model |
491 | config CPU_CACHE_V3 | |
492 | bool | |
493 | ||
494 | config CPU_CACHE_V4 | |
495 | bool | |
496 | ||
497 | config CPU_CACHE_V4WT | |
498 | bool | |
499 | ||
500 | config CPU_CACHE_V4WB | |
501 | bool | |
502 | ||
503 | config CPU_CACHE_V6 | |
504 | bool | |
505 | ||
23688e99 CM |
506 | config CPU_CACHE_V7 |
507 | bool | |
508 | ||
1da177e4 LT |
509 | config CPU_CACHE_VIVT |
510 | bool | |
511 | ||
512 | config CPU_CACHE_VIPT | |
513 | bool | |
514 | ||
f9c21a6e | 515 | if MMU |
1da177e4 LT |
516 | # The copy-page model |
517 | config CPU_COPY_V3 | |
518 | bool | |
519 | ||
520 | config CPU_COPY_V4WT | |
521 | bool | |
522 | ||
523 | config CPU_COPY_V4WB | |
524 | bool | |
525 | ||
0ed15071 LB |
526 | config CPU_COPY_FEROCEON |
527 | bool | |
528 | ||
1da177e4 LT |
529 | config CPU_COPY_V6 |
530 | bool | |
531 | ||
532 | # This selects the TLB model | |
533 | config CPU_TLB_V3 | |
534 | bool | |
535 | help | |
536 | ARM Architecture Version 3 TLB. | |
537 | ||
538 | config CPU_TLB_V4WT | |
539 | bool | |
540 | help | |
541 | ARM Architecture Version 4 TLB with writethrough cache. | |
542 | ||
543 | config CPU_TLB_V4WB | |
544 | bool | |
545 | help | |
546 | ARM Architecture Version 4 TLB with writeback cache. | |
547 | ||
548 | config CPU_TLB_V4WBI | |
549 | bool | |
550 | help | |
551 | ARM Architecture Version 4 TLB with writeback cache and invalidate | |
552 | instruction cache entry. | |
553 | ||
99c6dc11 LB |
554 | config CPU_TLB_FEROCEON |
555 | bool | |
556 | help | |
557 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). | |
558 | ||
1da177e4 LT |
559 | config CPU_TLB_V6 |
560 | bool | |
561 | ||
2ccdd1e7 CM |
562 | config CPU_TLB_V7 |
563 | bool | |
564 | ||
f9c21a6e HC |
565 | endif |
566 | ||
516793c6 RK |
567 | config CPU_HAS_ASID |
568 | bool | |
569 | help | |
570 | This indicates whether the CPU has the ASID register; used to | |
571 | tag TLB and possibly cache entries. | |
572 | ||
fefdaa06 HC |
573 | config CPU_CP15 |
574 | bool | |
575 | help | |
576 | Processor has the CP15 register. | |
577 | ||
578 | config CPU_CP15_MMU | |
579 | bool | |
580 | select CPU_CP15 | |
581 | help | |
582 | Processor has the CP15 register, which has MMU related registers. | |
583 | ||
584 | config CPU_CP15_MPU | |
585 | bool | |
586 | select CPU_CP15 | |
587 | help | |
588 | Processor has the CP15 register, which has MPU related registers. | |
589 | ||
23bdf86a LB |
590 | # |
591 | # CPU supports 36-bit I/O | |
592 | # | |
593 | config IO_36 | |
594 | bool | |
595 | ||
1da177e4 LT |
596 | comment "Processor Features" |
597 | ||
598 | config ARM_THUMB | |
599 | bool "Support Thumb user binaries" | |
e50d6409 | 600 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
601 | default y |
602 | help | |
603 | Say Y if you want to include kernel support for running user space | |
604 | Thumb binaries. | |
605 | ||
606 | The Thumb instruction set is a compressed form of the standard ARM | |
607 | instruction set resulting in smaller binaries at the expense of | |
608 | slightly less efficient code. | |
609 | ||
610 | If you don't know what this all is, saying Y is a safe choice. | |
611 | ||
d7f864be CM |
612 | config ARM_THUMBEE |
613 | bool "Enable ThumbEE CPU extension" | |
614 | depends on CPU_V7 | |
615 | help | |
616 | Say Y here if you have a CPU with the ThumbEE extension and code to | |
617 | make use of it. Say N for code that can run on CPUs without ThumbEE. | |
618 | ||
1da177e4 LT |
619 | config CPU_BIG_ENDIAN |
620 | bool "Build big-endian kernel" | |
621 | depends on ARCH_SUPPORTS_BIG_ENDIAN | |
622 | help | |
623 | Say Y if you plan on running a kernel in big-endian mode. | |
624 | Note that your board must be properly built and your board | |
625 | port must properly enable any big-endian related features | |
626 | of your chipset/board/processor. | |
627 | ||
6afd6fae | 628 | config CPU_HIGH_VECTOR |
6340aa61 | 629 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
6afd6fae HC |
630 | bool "Select the High exception vector" |
631 | default n | |
632 | help | |
633 | Say Y here to select high exception vector(0xFFFF0000~). | |
634 | The exception vector can be vary depending on the platform | |
635 | design in nommu mode. If your platform needs to select | |
636 | high exception vector, say Y. | |
637 | Otherwise or if you are unsure, say N, and the low exception | |
638 | vector (0x00000000~) will be used. | |
639 | ||
1da177e4 | 640 | config CPU_ICACHE_DISABLE |
f12d0d7c HC |
641 | bool "Disable I-Cache (I-bit)" |
642 | depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) | |
1da177e4 LT |
643 | help |
644 | Say Y here to disable the processor instruction cache. Unless | |
645 | you have a reason not to or are unsure, say N. | |
646 | ||
647 | config CPU_DCACHE_DISABLE | |
f12d0d7c HC |
648 | bool "Disable D-Cache (C-bit)" |
649 | depends on CPU_CP15 | |
1da177e4 LT |
650 | help |
651 | Say Y here to disable the processor data cache. Unless | |
652 | you have a reason not to or are unsure, say N. | |
653 | ||
f37f46eb HC |
654 | config CPU_DCACHE_SIZE |
655 | hex | |
656 | depends on CPU_ARM740T || CPU_ARM946E | |
657 | default 0x00001000 if CPU_ARM740T | |
658 | default 0x00002000 # default size for ARM946E-S | |
659 | help | |
660 | Some cores are synthesizable to have various sized cache. For | |
661 | ARM946E-S case, it can vary from 0KB to 1MB. | |
662 | To support such cache operations, it is efficient to know the size | |
663 | before compile time. | |
664 | If your SoC is configured to have a different size, define the value | |
665 | here with proper conditions. | |
666 | ||
1da177e4 LT |
667 | config CPU_DCACHE_WRITETHROUGH |
668 | bool "Force write through D-cache" | |
a7039bd6 | 669 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE |
1da177e4 LT |
670 | default y if CPU_ARM925T |
671 | help | |
672 | Say Y here to use the data cache in writethrough mode. Unless you | |
673 | specifically require this or are unsure, say N. | |
674 | ||
675 | config CPU_CACHE_ROUND_ROBIN | |
676 | bool "Round robin I and D cache replacement algorithm" | |
f37f46eb | 677 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
1da177e4 LT |
678 | help |
679 | Say Y here to use the predictable round-robin cache replacement | |
680 | policy. Unless you specifically require this or are unsure, say N. | |
681 | ||
682 | config CPU_BPREDICT_DISABLE | |
683 | bool "Disable branch prediction" | |
23688e99 | 684 | depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 |
1da177e4 LT |
685 | help |
686 | Say Y here to disable branch prediction. If unsure, say N. | |
2d2669b6 | 687 | |
4b0e07a5 NP |
688 | config TLS_REG_EMUL |
689 | bool | |
4b0e07a5 | 690 | help |
70489c88 NP |
691 | An SMP system using a pre-ARMv6 processor (there are apparently |
692 | a few prototypes like that in existence) and therefore access to | |
693 | that required register must be emulated. | |
4b0e07a5 | 694 | |
2d2669b6 NP |
695 | config HAS_TLS_REG |
696 | bool | |
70489c88 NP |
697 | depends on !TLS_REG_EMUL |
698 | default y if SMP || CPU_32v7 | |
2d2669b6 NP |
699 | help |
700 | This selects support for the CP15 thread register. | |
70489c88 NP |
701 | It is defined to be available on some ARMv6 processors (including |
702 | all SMP capable ARMv6's) or later processors. User space may | |
703 | assume directly accessing that register and always obtain the | |
704 | expected value only on ARMv7 and above. | |
2d2669b6 | 705 | |
dcef1f63 NP |
706 | config NEEDS_SYSCALL_FOR_CMPXCHG |
707 | bool | |
dcef1f63 NP |
708 | help |
709 | SMP on a pre-ARMv6 processor? Well OK then. | |
710 | Forget about fast user space cmpxchg support. | |
711 | It is just not possible. | |
712 | ||
953233dc CM |
713 | config OUTER_CACHE |
714 | bool | |
715 | default n | |
382266ad | 716 | |
99c6dc11 LB |
717 | config CACHE_FEROCEON_L2 |
718 | bool "Enable the Feroceon L2 cache controller" | |
651c74c7 | 719 | depends on ARCH_KIRKWOOD |
99c6dc11 LB |
720 | default y |
721 | select OUTER_CACHE | |
722 | help | |
723 | This option enables the Feroceon L2 cache controller. | |
724 | ||
382266ad | 725 | config CACHE_L2X0 |
ba927951 CM |
726 | bool "Enable the L2x0 outer cache controller" |
727 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 | |
728 | default y | |
382266ad | 729 | select OUTER_CACHE |
ba927951 CM |
730 | help |
731 | This option enables the L2x0 PrimeCell. |