[net-next-2.6.git] / arch / arm / mach-w90x900 / cpu.c

/*
 * linux/arch/arm/mach-w90x900/cpu.c
 *
 * Copyright (c) 2009 Nuvoton corporation.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
 * NUC900 series cpu common support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation;version 2 of the License.
 *
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/serial_8250.h>
#include <linux/delay.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>

#include <mach/hardware.h>
#include <mach/regs-serial.h>
#include <mach/regs-clock.h>
#include <mach/regs-ebi.h>

#include "cpu.h"
#include "clock.h"

/* Initial IO mappings */

static struct map_desc nuc900_iodesc[] __initdata = {
	IODESC_ENT(IRQ),
	IODESC_ENT(GCR),
	IODESC_ENT(UART),
	IODESC_ENT(TIMER),
	IODESC_ENT(EBI),
	IODESC_ENT(GPIO),
};

/* Initial clock declarations. */
static DEFINE_CLK(lcd, 0);
static DEFINE_CLK(audio, 1);
static DEFINE_CLK(fmi, 4);
static DEFINE_SUBCLK(ms, 0);
static DEFINE_SUBCLK(sd, 1);
static DEFINE_CLK(dmac, 5);
static DEFINE_CLK(atapi, 6);
static DEFINE_CLK(emc, 7);
static DEFINE_SUBCLK(rmii, 2);
static DEFINE_CLK(usbd, 8);
static DEFINE_CLK(usbh, 9);
static DEFINE_CLK(g2d, 10);;
static DEFINE_CLK(pwm, 18);
static DEFINE_CLK(ps2, 24);
static DEFINE_CLK(kpi, 25);
static DEFINE_CLK(wdt, 26);
static DEFINE_CLK(gdma, 27);
static DEFINE_CLK(adc, 28);
static DEFINE_CLK(usi, 29);
static DEFINE_CLK(ext, 0);
static DEFINE_CLK(timer0, 19);
static DEFINE_CLK(timer1, 20);
static DEFINE_CLK(timer2, 21);
static DEFINE_CLK(timer3, 22);
static DEFINE_CLK(timer4, 23);

static struct clk_lookup nuc900_clkregs[] = {
	DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
	DEF_CLKLOOK(&clk_audio, "nuc900-audio", NULL),
	DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL),
	DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"),
	DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"),
	DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL),
	DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL),
	DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL),
	DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"),
	DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL),
	DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL),
	DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL),
	DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL),
	DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL),
	DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
	DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
	DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
	DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
	DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
	DEF_CLKLOOK(&clk_ext, NULL, "ext"),
	DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
	DEF_CLKLOOK(&clk_timer1, NULL, "timer1"),
	DEF_CLKLOOK(&clk_timer2, NULL, "timer2"),
	DEF_CLKLOOK(&clk_timer3, NULL, "timer3"),
	DEF_CLKLOOK(&clk_timer4, NULL, "timer4"),
};

/* Initial serial platform data */

struct plat_serial8250_port nuc900_uart_data[] = {
	NUC900_8250PORT(UART0),
	{},
};

struct platform_device nuc900_serial_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= nuc900_uart_data,
	},
};

/*Set NUC900 series cpu frequence*/
static int __init nuc900_set_clkval(unsigned int cpufreq)
{
	unsigned int pllclk, ahbclk, apbclk, val;

	pllclk = 0;
	ahbclk = 0;
	apbclk = 0;

	switch (cpufreq) {
	case 66:
		pllclk = PLL_66MHZ;
		ahbclk = AHB_CPUCLK_1_1;
		apbclk = APB_AHB_1_2;
		break;

	case 100:
		pllclk = PLL_100MHZ;
		ahbclk = AHB_CPUCLK_1_1;
		apbclk = APB_AHB_1_2;
		break;

	case 120:
		pllclk = PLL_120MHZ;
		ahbclk = AHB_CPUCLK_1_2;
		apbclk = APB_AHB_1_2;
		break;

	case 166:
		pllclk = PLL_166MHZ;
		ahbclk = AHB_CPUCLK_1_2;
		apbclk = APB_AHB_1_2;
		break;

	case 200:
		pllclk = PLL_200MHZ;
		ahbclk = AHB_CPUCLK_1_2;
		apbclk = APB_AHB_1_2;
		break;
	}

	__raw_writel(pllclk, REG_PLLCON0);

	val = __raw_readl(REG_CLKDIV);
	val &= ~(0x03 << 24 | 0x03 << 26);
	val |= (ahbclk << 24 | apbclk << 26);
	__raw_writel(val, REG_CLKDIV);

	return 	0;
}
static int __init nuc900_set_cpufreq(char *str)
{
	unsigned long cpufreq, val;

	if (!*str)
		return 0;

	strict_strtoul(str, 0, &cpufreq);

	nuc900_clock_source(NULL, "ext");

	nuc900_set_clkval(cpufreq);

	mdelay(1);

	val = __raw_readl(REG_CKSKEW);
	val &= ~0xff;
	val |= DEFAULTSKEW;
	__raw_writel(val, REG_CKSKEW);

	nuc900_clock_source(NULL, "pll0");

	return 1;
}

__setup("cpufreq=", nuc900_set_cpufreq);

/*Init NUC900 evb io*/

void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
{
	unsigned long idcode = 0x0;

	iotable_init(mach_desc, mach_size);
	iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc));

	idcode = __raw_readl(NUC900PDID);
	if (idcode == NUC910_CPUID)
		printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
	else if (idcode == NUC920_CPUID)
		printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode);
	else if (idcode == NUC950_CPUID)
		printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode);
	else if (idcode == NUC960_CPUID)
		printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode);
}

/*Init NUC900 clock*/

void __init nuc900_init_clocks(void)
{
	clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
}
Commit	Line	Data
7ec80ddf	1	/*
35c9221a	2	* linux/arch/arm/mach-w90x900/cpu.c
7ec80ddf	3	*
35c9221a	4	* Copyright (c) 2009 Nuvoton corporation.
7ec80ddf	5	*
	6	* Wan ZongShun <mcuos.com@gmail.com>
	7	*
35c9221a	8	* NUC900 series cpu common support
7ec80ddf	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
604f766f	12	* the Free Software Foundation;version 2 of the License.
7ec80ddf	13	*
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/types.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/list.h>
	20	#include <linux/timer.h>
	21	#include <linux/init.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/io.h>
17198f2d	24	#include <linux/serial_8250.h>
ae45b1c6	25	#include <linux/delay.h>
7ec80ddf	26
	27	#include <asm/mach/arch.h>
	28	#include <asm/mach/map.h>
	29	#include <asm/mach/irq.h>
	30	#include <asm/irq.h>
	31
	32	#include <mach/hardware.h>
	33	#include <mach/regs-serial.h>
ae45b1c6	34	#include <mach/regs-clock.h>
ae45b1c6	35	#include <mach/regs-ebi.h>
7ec80ddf	36
7ec80ddf	37	#include "cpu.h"
0e4a34bb	38	#include "clock.h"
7ec80ddf	39
7ec80ddf	40	/* Initial IO mappings */
7ec80ddf	41
35c9221a	42	static struct map_desc nuc900_iodesc[] __initdata = {
7ec80ddf	43	IODESC_ENT(IRQ),
	44	IODESC_ENT(GCR),
	45	IODESC_ENT(UART),
	46	IODESC_ENT(TIMER),
	47	IODESC_ENT(EBI),
6d636c68	48	IODESC_ENT(GPIO),
7ec80ddf	49	};
7ec80ddf	50
0e4a34bb	51	/* Initial clock declarations. */
	52	static DEFINE_CLK(lcd, 0);
	53	static DEFINE_CLK(audio, 1);
	54	static DEFINE_CLK(fmi, 4);
db58e90f	55	static DEFINE_SUBCLK(ms, 0);
db58e90f	56	static DEFINE_SUBCLK(sd, 1);
0e4a34bb	57	static DEFINE_CLK(dmac, 5);
	58	static DEFINE_CLK(atapi, 6);
	59	static DEFINE_CLK(emc, 7);
db58e90f	60	static DEFINE_SUBCLK(rmii, 2);
0e4a34bb	61	static DEFINE_CLK(usbd, 8);
	62	static DEFINE_CLK(usbh, 9);
	63	static DEFINE_CLK(g2d, 10);;
	64	static DEFINE_CLK(pwm, 18);
	65	static DEFINE_CLK(ps2, 24);
	66	static DEFINE_CLK(kpi, 25);
	67	static DEFINE_CLK(wdt, 26);
	68	static DEFINE_CLK(gdma, 27);
	69	static DEFINE_CLK(adc, 28);
	70	static DEFINE_CLK(usi, 29);
58b5369e	71	static DEFINE_CLK(ext, 0);
ce746e47	72	static DEFINE_CLK(timer0, 19);
	73	static DEFINE_CLK(timer1, 20);
	74	static DEFINE_CLK(timer2, 21);
	75	static DEFINE_CLK(timer3, 22);
	76	static DEFINE_CLK(timer4, 23);
0e4a34bb	77
35c9221a	78	static struct clk_lookup nuc900_clkregs[] = {
	79	DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
	80	DEF_CLKLOOK(&clk_audio, "nuc900-audio", NULL),
	81	DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL),
	82	DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"),
	83	DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"),
	84	DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL),
	85	DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL),
	86	DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL),
	87	DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"),
	88	DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL),
	89	DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL),
	90	DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL),
	91	DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL),
	92	DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL),
	93	DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
	94	DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
	95	DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
a7029c82	96	DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
35c9221a	97	DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
58b5369e	98	DEF_CLKLOOK(&clk_ext, NULL, "ext"),
ce746e47	99	DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
	100	DEF_CLKLOOK(&clk_timer1, NULL, "timer1"),
	101	DEF_CLKLOOK(&clk_timer2, NULL, "timer2"),
	102	DEF_CLKLOOK(&clk_timer3, NULL, "timer3"),
	103	DEF_CLKLOOK(&clk_timer4, NULL, "timer4"),
0e4a34bb	104	};
0e4a34bb	105
17198f2d	106	/* Initial serial platform data */
7ec80ddf	107
35c9221a	108	struct plat_serial8250_port nuc900_uart_data[] = {
35c9221a	109	NUC900_8250PORT(UART0),
db93dd1a	110	{},
17198f2d	111	};
7ec80ddf	112
35c9221a	113	struct platform_device nuc900_serial_device = {
17198f2d	114	.name = "serial8250",
	115	.id = PLAT8250_DEV_PLATFORM,
	116	.dev = {
35c9221a	117	.platform_data = nuc900_uart_data,
17198f2d	118	},
17198f2d	119	};
7ec80ddf	120
35c9221a	121	/Set NUC900 series cpu frequence/
35c9221a	122	static int __init nuc900_set_clkval(unsigned int cpufreq)
ae45b1c6	123	{
	124	unsigned int pllclk, ahbclk, apbclk, val;
	125
	126	pllclk = 0;
	127	ahbclk = 0;
	128	apbclk = 0;
	129
	130	switch (cpufreq) {
	131	case 66:
	132	pllclk = PLL_66MHZ;
	133	ahbclk = AHB_CPUCLK_1_1;
	134	apbclk = APB_AHB_1_2;
	135	break;
	136
	137	case 100:
	138	pllclk = PLL_100MHZ;
	139	ahbclk = AHB_CPUCLK_1_1;
	140	apbclk = APB_AHB_1_2;
	141	break;
	142
	143	case 120:
	144	pllclk = PLL_120MHZ;
	145	ahbclk = AHB_CPUCLK_1_2;
	146	apbclk = APB_AHB_1_2;
	147	break;
	148
	149	case 166:
	150	pllclk = PLL_166MHZ;
	151	ahbclk = AHB_CPUCLK_1_2;
	152	apbclk = APB_AHB_1_2;
	153	break;
	154
	155	case 200:
	156	pllclk = PLL_200MHZ;
	157	ahbclk = AHB_CPUCLK_1_2;
	158	apbclk = APB_AHB_1_2;
	159	break;
	160	}
	161
	162	__raw_writel(pllclk, REG_PLLCON0);
	163
	164	val = __raw_readl(REG_CLKDIV);
	165	val &= ~(0x03 << 24 \| 0x03 << 26);
	166	val \|= (ahbclk << 24 \| apbclk << 26);
	167	__raw_writel(val, REG_CLKDIV);
	168
	169	return 0;
	170	}
35c9221a	171	static int __init nuc900_set_cpufreq(char *str)
ae45b1c6	172	{
	173	unsigned long cpufreq, val;
	174
	175	if (!*str)
	176	return 0;
	177
	178	strict_strtoul(str, 0, &cpufreq);
	179
35c9221a	180	nuc900_clock_source(NULL, "ext");
ae45b1c6	181
35c9221a	182	nuc900_set_clkval(cpufreq);
ae45b1c6	183
	184	mdelay(1);
	185
	186	val = __raw_readl(REG_CKSKEW);
	187	val &= ~0xff;
	188	val \|= DEFAULTSKEW;
	189	__raw_writel(val, REG_CKSKEW);
	190
35c9221a	191	nuc900_clock_source(NULL, "pll0");
ae45b1c6	192
	193	return 1;
	194	}
	195
35c9221a	196	__setup("cpufreq=", nuc900_set_cpufreq);
ae45b1c6	197
35c9221a	198	/Init NUC900 evb io/
7ec80ddf	199
35c9221a	200	void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
7ec80ddf	201	{
35c9221a	202	unsigned long idcode = 0x0;
7ec80ddf	203
35c9221a	204	iotable_init(mach_desc, mach_size);
	205	iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc));
	206
	207	idcode = __raw_readl(NUC900PDID);
	208	if (idcode == NUC910_CPUID)
	209	printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
	210	else if (idcode == NUC920_CPUID)
	211	printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode);
	212	else if (idcode == NUC950_CPUID)
	213	printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode);
	214	else if (idcode == NUC960_CPUID)
	215	printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode);
7ec80ddf	216	}
7ec80ddf	217
35c9221a	218	/Init NUC900 clock/
	219
	220	void __init nuc900_init_clocks(void)
7ec80ddf	221	{
0a0300dc	222	clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
7ec80ddf	223	}
35c9221a	224