[net-next-2.6.git] / arch / arm / mach-vexpress / ct-ca9x4.c

/*
 * Versatile Express Core Tile Cortex A9x4 Support
 */
#include <linux/init.h>
#include <linux/gfp.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>

#include <asm/clkdev.h>
#include <asm/pgtable.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/pmu.h>
#include <asm/smp_twd.h>

#include <mach/clkdev.h>
#include <mach/ct-ca9x4.h>

#include <plat/timer-sp.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "core.h"

#include <mach/motherboard.h>

#define V2M_PA_CS7	0x10000000

static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	{
		.virtual	= __MMIO_P2V(CT_CA9X4_MPIC),
		.pfn		= __phys_to_pfn(CT_CA9X4_MPIC),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
		.pfn		= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= __MMIO_P2V(CT_CA9X4_L2CC),
		.pfn		= __phys_to_pfn(CT_CA9X4_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static void __init ct_ca9x4_map_io(void)
{
#ifdef CONFIG_LOCAL_TIMERS
	twd_base = MMIO_P2V(A9_MPCORE_TWD);
#endif
	v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}

void __iomem *gic_cpu_base_addr;

static void __init ct_ca9x4_init_irq(void)
{
	gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
	gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
	gic_cpu_init(0, gic_cpu_base_addr);
}

#if 0
static void __init ct_ca9x4_timer_init(void)
{
	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);

	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
}

static struct sys_timer ct_ca9x4_timer = {
	.init	= ct_ca9x4_timer_init,
};
#endif

static struct clcd_panel xvga_panel = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15384,
		.left_margin	= 168,
		.right_margin	= 8,
		.upper_margin	= 29,
		.lower_margin	= 3,
		.hsync_len	= 144,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
	v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
}

static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize = 1024 * 768 * 2;
	dma_addr_t dma;

	fb->panel = &xvga_panel;

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
				&dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map frame buffer\n");
		return -ENOMEM;
	}
	fb->fb.fix.smem_start = dma;
	fb->fb.fix.smem_len = framesize;

	return 0;
}

static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
		fb->fb.fix.smem_start, fb->fb.fix.smem_len);
}

static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
		fb->fb.screen_base, fb->fb.fix.smem_start);
}

static struct clcd_board ct_ca9x4_clcd_data = {
	.name		= "CT-CA9X4",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= ct_ca9x4_clcd_enable,
	.setup		= ct_ca9x4_clcd_setup,
	.mmap		= ct_ca9x4_clcd_mmap,
	.remove		= ct_ca9x4_clcd_remove,
};

static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);

static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
	&clcd_device,
	&dmc_device,
	&smc_device,
	&gpio_device,
};


static long ct_round(struct clk *clk, unsigned long rate)
{
	return rate;
}

static int ct_set(struct clk *clk, unsigned long rate)
{
	return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
}

static const struct clk_ops osc1_clk_ops = {
	.round	= ct_round,
	.set	= ct_set,
};

static struct clk osc1_clk = {
	.ops	= &osc1_clk_ops,
	.rate	= 24000000,
};

static struct clk_lookup lookups[] = {
	{	/* CLCD */
		.dev_id		= "ct:clcd",
		.clk		= &osc1_clk,
	},
};

static struct resource pmu_resources[] = {
	[0] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU0,
		.end	= IRQ_CT_CA9X4_PMU_CPU0,
		.flags	= IORESOURCE_IRQ,
	},
	[1] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU1,
		.end	= IRQ_CT_CA9X4_PMU_CPU1,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU2,
		.end	= IRQ_CT_CA9X4_PMU_CPU2,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		.start	= IRQ_CT_CA9X4_PMU_CPU3,
		.end	= IRQ_CT_CA9X4_PMU_CPU3,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device pmu_device = {
	.name		= "arm-pmu",
	.id		= ARM_PMU_DEVICE_CPU,
	.num_resources	= ARRAY_SIZE(pmu_resources),
	.resource	= pmu_resources,
};

static void __init ct_ca9x4_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);

	/* set RAM latencies to 1 cycle for this core tile. */
	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);

	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
#endif

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
		amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);

	platform_device_register(&pmu_device);
}

MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
	.boot_params	= PHYS_OFFSET + 0x00000100,
	.map_io		= ct_ca9x4_map_io,
	.init_irq	= ct_ca9x4_init_irq,
#if 0
	.timer		= &ct_ca9x4_timer,
#else
	.timer		= &v2m_timer,
#endif
	.init_machine	= ct_ca9x4_init,
MACHINE_END
Commit	Line	Data
fef88f10 RK	1	/*
	2	* Versatile Express Core Tile Cortex A9x4 Support
	3	*/
	4	#include <linux/init.h>
68aaae9e	5	#include <linux/gfp.h>
fef88f10 RK	6	#include <linux/device.h>
fef88f10 RK	7	#include <linux/dma-mapping.h>
f417cbad	8	#include <linux/platform_device.h>
fef88f10 RK	9	#include <linux/amba/bus.h>
	10	#include <linux/amba/clcd.h>
	11
	12	#include <asm/clkdev.h>
cf0bb91b	13	#include <asm/pgtable.h>
fef88f10 RK	14	#include <asm/hardware/arm_timer.h>
	15	#include <asm/hardware/cache-l2x0.h>
	16	#include <asm/hardware/gic.h>
	17	#include <asm/mach-types.h>
f417cbad	18	#include <asm/pmu.h>
bde28b84	19	#include <asm/smp_twd.h>
fef88f10 RK	20
	21	#include <mach/clkdev.h>
	22	#include <mach/ct-ca9x4.h>
	23
	24	#include <plat/timer-sp.h>
	25
	26	#include <asm/mach/arch.h>
	27	#include <asm/mach/map.h>
	28	#include <asm/mach/time.h>
	29
	30	#include "core.h"
	31
	32	#include <mach/motherboard.h>
	33
	34	#define V2M_PA_CS7 0x10000000
	35
	36	static struct map_desc ct_ca9x4_io_desc[] __initdata = {
	37	{
	38	.virtual = __MMIO_P2V(CT_CA9X4_MPIC),
	39	.pfn = __phys_to_pfn(CT_CA9X4_MPIC),
	40	.length = SZ_16K,
	41	.type = MT_DEVICE,
	42	}, {
	43	.virtual = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
	44	.pfn = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
	45	.length = SZ_4K,
	46	.type = MT_DEVICE,
	47	}, {
	48	.virtual = __MMIO_P2V(CT_CA9X4_L2CC),
	49	.pfn = __phys_to_pfn(CT_CA9X4_L2CC),
	50	.length = SZ_4K,
	51	.type = MT_DEVICE,
	52	},
	53	};
	54
	55	static void __init ct_ca9x4_map_io(void)
	56	{
e56c010f	57	#ifdef CONFIG_LOCAL_TIMERS
bde28b84	58	twd_base = MMIO_P2V(A9_MPCORE_TWD);
e56c010f	59	#endif
fef88f10 RK	60	v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
	61	}
	62
	63	void __iomem *gic_cpu_base_addr;
	64
	65	static void __init ct_ca9x4_init_irq(void)
	66	{
	67	gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
	68	gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
	69	gic_cpu_init(0, gic_cpu_base_addr);
	70	}
	71
	72	#if 0
cdaf9a2f	73	static void __init ct_ca9x4_timer_init(void)
fef88f10 RK	74	{
	75	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
	76	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
	77
	78	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
	79	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
	80	}
	81
	82	static struct sys_timer ct_ca9x4_timer = {
	83	.init = ct_ca9x4_timer_init,
	84	};
	85	#endif
	86
	87	static struct clcd_panel xvga_panel = {
	88	.mode = {
	89	.name = "XVGA",
	90	.refresh = 60,
	91	.xres = 1024,
	92	.yres = 768,
	93	.pixclock = 15384,
	94	.left_margin = 168,
	95	.right_margin = 8,
	96	.upper_margin = 29,
	97	.lower_margin = 3,
	98	.hsync_len = 144,
	99	.vsync_len = 6,
	100	.sync = 0,
	101	.vmode = FB_VMODE_NONINTERLACED,
	102	},
	103	.width = -1,
	104	.height = -1,
	105	.tim2 = TIM2_BCD \| TIM2_IPC,
	106	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
	107	.bpp = 16,
	108	};
	109
	110	static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
	111	{
	112	v2m_cfg_write(SYS_CFG_MUXFPGA \| SYS_CFG_SITE_DB1, 0);
	113	v2m_cfg_write(SYS_CFG_DVIMODE \| SYS_CFG_SITE_DB1, 2);
	114	}
	115
	116	static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
	117	{
	118	unsigned long framesize = 1024 * 768 * 2;
	119	dma_addr_t dma;
	120
	121	fb->panel = &xvga_panel;
	122
	123	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	124	&dma, GFP_KERNEL);
	125	if (!fb->fb.screen_base) {
	126	printk(KERN_ERR "CLCD: unable to map frame buffer\n");
	127	return -ENOMEM;
	128	}
	129	fb->fb.fix.smem_start = dma;
	130	fb->fb.fix.smem_len = framesize;
	131
	132	return 0;
	133	}
	134
	135	static int ct_ca9x4_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	136	{
	137	return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
138	fb->fb.fix.smem_start, fb->fb.fix.smem_len);
139	}
140
141	static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
142	{
143	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
144	fb->fb.screen_base, fb->fb.fix.smem_start);
145	}
146
147	static struct clcd_board ct_ca9x4_clcd_data = {
148	.name = "CT-CA9X4",
149	.check = clcdfb_check,
150	.decode = clcdfb_decode,
151	.enable = ct_ca9x4_clcd_enable,
152	.setup = ct_ca9x4_clcd_setup,
153	.mmap = ct_ca9x4_clcd_mmap,
154	.remove = ct_ca9x4_clcd_remove,
155	};
156
157	static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
158	static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
159	static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
160	static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
161
162	static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
163	&clcd_device,
164	&dmc_device,
165	&smc_device,
166	&gpio_device,
167	};
168
169
170	static long ct_round(struct clk *clk, unsigned long rate)
171	{
172	return rate;
173	}
174
175	static int ct_set(struct clk *clk, unsigned long rate)
176	{
177	return v2m_cfg_write(SYS_CFG_OSC \| SYS_CFG_SITE_DB1 \| 1, rate);
178	}
179
180	static const struct clk_ops osc1_clk_ops = {
181	.round = ct_round,
182	.set = ct_set,
183	};
184
185	static struct clk osc1_clk = {
186	.ops = &osc1_clk_ops,
187	.rate = 24000000,
188	};
189
190	static struct clk_lookup lookups[] = {
191	{ /* CLCD */
192	.dev_id = "ct:clcd",
193	.clk = &osc1_clk,
194	},
195	};
196
f417cbad WD	197	static struct resource pmu_resources[] = {
	198	[0] = {
	199	.start = IRQ_CT_CA9X4_PMU_CPU0,
	200	.end = IRQ_CT_CA9X4_PMU_CPU0,
	201	.flags = IORESOURCE_IRQ,
	202	},
	203	[1] = {
	204	.start = IRQ_CT_CA9X4_PMU_CPU1,
	205	.end = IRQ_CT_CA9X4_PMU_CPU1,
	206	.flags = IORESOURCE_IRQ,
	207	},
	208	[2] = {
	209	.start = IRQ_CT_CA9X4_PMU_CPU2,
	210	.end = IRQ_CT_CA9X4_PMU_CPU2,
	211	.flags = IORESOURCE_IRQ,
	212	},
	213	[3] = {
	214	.start = IRQ_CT_CA9X4_PMU_CPU3,
	215	.end = IRQ_CT_CA9X4_PMU_CPU3,
	216	.flags = IORESOURCE_IRQ,
	217	},
	218	};
	219
	220	static struct platform_device pmu_device = {
	221	.name = "arm-pmu",
	222	.id = ARM_PMU_DEVICE_CPU,
	223	.num_resources = ARRAY_SIZE(pmu_resources),
	224	.resource = pmu_resources,
	225	};
	226
cdaf9a2f	227	static void __init ct_ca9x4_init(void)
fef88f10 RK	228	{
	229	int i;
	230
	231	#ifdef CONFIG_CACHE_L2X0
2de59fea WD	232	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
	233
	234	/* set RAM latencies to 1 cycle for this core tile. */
	235	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
	236	writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
	237
	238	l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
fef88f10 RK	239	#endif
	240
	241	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	242
	243	for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
	244	amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
f417cbad WD	245
f417cbad WD	246	platform_device_register(&pmu_device);
fef88f10 RK	247	}
	248
	249	MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
fef88f10 RK	250	.boot_params = PHYS_OFFSET + 0x00000100,
	251	.map_io = ct_ca9x4_map_io,
	252	.init_irq = ct_ca9x4_init_irq,
	253	#if 0
	254	.timer = &ct_ca9x4_timer,
	255	#else
	256	.timer = &v2m_timer,
	257	#endif
	258	.init_machine = ct_ca9x4_init,
	259	MACHINE_END