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ARM: Realview/Versatile: separate out common sched_clock()
[net-next-2.6.git] / arch / arm / mach-versatile / core.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
1da177e4
LT		 21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/dma-mapping.h>
d052d1be 24#include <linux/platform_device.h>
1da177e4
LT		 25#include <linux/sysdev.h>
26#include <linux/interrupt.h>
a62c80e5
RK		 27#include <linux/amba/bus.h>
28#include <linux/amba/clcd.h>
bbeddc43 29#include <linux/amba/pl061.h>
6ef297f8 30#include <linux/amba/mmci.h>
fced80c7 31#include <linux/io.h>
1da177e4 32
71a06da0 33#include <asm/clkdev.h>
1da177e4 34#include <asm/system.h>
1da177e4
LT		 35#include <asm/irq.h>
36#include <asm/leds.h>
b720f732 37#include <asm/hardware/arm_timer.h>
c5a0adb5 38#include <asm/hardware/icst.h>
fa0fe48f 39#include <asm/hardware/vic.h>
dc5bc8f1 40#include <asm/mach-types.h>
1da177e4
LT		 41
42#include <asm/mach/arch.h>
43#include <asm/mach/flash.h>
44#include <asm/mach/irq.h>
45#include <asm/mach/time.h>
46#include <asm/mach/map.h>
f4b8b319 47#include <mach/clkdev.h>
a285edcf
RK		 48#include <mach/hardware.h>
49#include <mach/platform.h>
e3887714 50#include <plat/timer-sp.h>
1da177e4
LT		 51
52#include "core.h"
1da177e4
LT		 53
54/*
55 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
56 * is the (PA >> 12).
57 *
58 * Setup a VA for the Versatile Vectored Interrupt Controller.
59 */
2ad4f86b
AV		 60#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
61#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
1da177e4 62
1da177e4
LT		 63static void sic_mask_irq(unsigned int irq)
64{
65 irq -= IRQ_SIC_START;
66 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
67}
68
69static void sic_unmask_irq(unsigned int irq)
70{
71 irq -= IRQ_SIC_START;
72 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
73}
74
38c677cb
DB		 75static struct irq_chip sic_chip = {
76 .name = "SIC",
1da177e4
LT		 77 .ack = sic_mask_irq,
78 .mask = sic_mask_irq,
79 .unmask = sic_unmask_irq,
80};
81
82static void
10dd5ce2 83sic_handle_irq(unsigned int irq, struct irq_desc *desc)
1da177e4
LT		 84{
85 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
86
87 if (status == 0) {
0cd61b68 88 do_bad_IRQ(irq, desc);
1da177e4
LT		 89 return;
90 }
91
92 do {
93 irq = ffs(status) - 1;
94 status &= ~(1 << irq);
95
96 irq += IRQ_SIC_START;
97
d8aa0251 98 generic_handle_irq(irq);
1da177e4
LT		 99 } while (status);
100}
101
102#if 1
103#define IRQ_MMCI0A IRQ_VICSOURCE22
104#define IRQ_AACI IRQ_VICSOURCE24
105#define IRQ_ETH IRQ_VICSOURCE25
106#define PIC_MASK 0xFFD00000
107#else
108#define IRQ_MMCI0A IRQ_SIC_MMCI0A
109#define IRQ_AACI IRQ_SIC_AACI
110#define IRQ_ETH IRQ_SIC_ETH
111#define PIC_MASK 0
112#endif
113
114void __init versatile_init_irq(void)
115{
fa0fe48f 116 unsigned int i;
1da177e4 117
c07f87f2 118 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
1da177e4 119
56f1319e 120 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
1da177e4
LT		 121
122 /* Do second interrupt controller */
123 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
124
125 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
126 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
127 set_irq_chip(i, &sic_chip);
10dd5ce2 128 set_irq_handler(i, handle_level_irq);
1da177e4
LT		 129 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
130 }
131 }
132
133 /*
134 * Interrupts on secondary controller from 0 to 8 are routed to
135 * source 31 on PIC.
136 * Interrupts from 21 to 31 are routed directly to the VIC on
137 * the corresponding number on primary controller. This is controlled
138 * by setting PIC_ENABLEx.
139 */
140 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
141}
142
143static struct map_desc versatile_io_desc[] __initdata = {
1311521f
DS		 144 {
145 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
146 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
147 .length = SZ_4K,
148 .type = MT_DEVICE
149 }, {
150 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
151 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
152 .length = SZ_4K,
153 .type = MT_DEVICE
154 }, {
155 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
156 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
157 .length = SZ_4K,
158 .type = MT_DEVICE
159 }, {
160 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
161 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
162 .length = SZ_4K * 9,
163 .type = MT_DEVICE
164 },
1da177e4 165#ifdef CONFIG_MACH_VERSATILE_AB
1311521f
DS		 166 {
167 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
168 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
169 .length = SZ_4K,
170 .type = MT_DEVICE
171 }, {
172 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
173 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
174 .length = SZ_64M,
175 .type = MT_DEVICE
176 },
1da177e4
LT		 177#endif
178#ifdef CONFIG_DEBUG_LL
1311521f
DS		 179 {
180 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
181 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
182 .length = SZ_4K,
183 .type = MT_DEVICE
184 },
1da177e4 185#endif
c0da085a 186#ifdef CONFIG_PCI
1311521f
DS		 187 {
188 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
189 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
190 .length = SZ_4K,
191 .type = MT_DEVICE
192 }, {
399ad77b 193 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
1311521f
DS		 194 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
195 .length = VERSATILE_PCI_BASE_SIZE,
196 .type = MT_DEVICE
197 }, {
399ad77b 198 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
1311521f
DS		 199 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
200 .length = VERSATILE_PCI_CFG_BASE_SIZE,
201 .type = MT_DEVICE
202 },
c0da085a 203#if 0
1311521f
DS		 204 {
205 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
206 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
207 .length = SZ_16M,
208 .type = MT_DEVICE
209 }, {
210 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
211 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
212 .length = SZ_16M,
213 .type = MT_DEVICE
214 }, {
215 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
216 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
217 .length = SZ_16M,
218 .type = MT_DEVICE
219 },
c0da085a 220#endif
1da177e4
LT		 221#endif
222};
223
224void __init versatile_map_io(void)
225{
226 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
227}
228
1da177e4 229
2ad4f86b 230#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
1da177e4
LT		 231
232static int versatile_flash_init(void)
233{
234 u32 val;
235
236 val = __raw_readl(VERSATILE_FLASHCTRL);
237 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
238 __raw_writel(val, VERSATILE_FLASHCTRL);
239
240 return 0;
241}
242
243static void versatile_flash_exit(void)
244{
245 u32 val;
246
247 val = __raw_readl(VERSATILE_FLASHCTRL);
248 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
249 __raw_writel(val, VERSATILE_FLASHCTRL);
250}
251
252static void versatile_flash_set_vpp(int on)
253{
254 u32 val;
255
256 val = __raw_readl(VERSATILE_FLASHCTRL);
257 if (on)
258 val |= VERSATILE_FLASHPROG_FLVPPEN;
259 else
260 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
261 __raw_writel(val, VERSATILE_FLASHCTRL);
262}
263
264static struct flash_platform_data versatile_flash_data = {
265 .map_name = "cfi_probe",
266 .width = 4,
267 .init = versatile_flash_init,
268 .exit = versatile_flash_exit,
269 .set_vpp = versatile_flash_set_vpp,
270};
271
272static struct resource versatile_flash_resource = {
273 .start = VERSATILE_FLASH_BASE,
a0c5a645 274 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
1da177e4
LT		 275 .flags = IORESOURCE_MEM,
276};
277
278static struct platform_device versatile_flash_device = {
279 .name = "armflash",
280 .id = 0,
281 .dev = {
282 .platform_data = &versatile_flash_data,
283 },
284 .num_resources = 1,
285 .resource = &versatile_flash_resource,
286};
287
288static struct resource smc91x_resources[] = {
289 [0] = {
290 .start = VERSATILE_ETH_BASE,
291 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = IRQ_ETH,
296 .end = IRQ_ETH,
297 .flags = IORESOURCE_IRQ,
298 },
299};
300
301static struct platform_device smc91x_device = {
302 .name = "smc91x",
303 .id = 0,
304 .num_resources = ARRAY_SIZE(smc91x_resources),
305 .resource = smc91x_resources,
306};
307
6b65cd74
RK		 308static struct resource versatile_i2c_resource = {
309 .start = VERSATILE_I2C_BASE,
310 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
311 .flags = IORESOURCE_MEM,
312};
313
314static struct platform_device versatile_i2c_device = {
315 .name = "versatile-i2c",
533ad5e6 316 .id = 0,
6b65cd74
RK		 317 .num_resources = 1,
318 .resource = &versatile_i2c_resource,
319};
320
533ad5e6
CM		 321static struct i2c_board_info versatile_i2c_board_info[] = {
322 {
64e8be6e 323 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6
CM		 324 },
325};
326
327static int __init versatile_i2c_init(void)
328{
329 return i2c_register_board_info(0, versatile_i2c_board_info,
330 ARRAY_SIZE(versatile_i2c_board_info));
331}
332arch_initcall(versatile_i2c_init);
333
2ad4f86b 334#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
1da177e4
LT		 335
336unsigned int mmc_status(struct device *dev)
337{
338 struct amba_device *adev = container_of(dev, struct amba_device, dev);
339 u32 mask;
340
341 if (adev->res.start == VERSATILE_MMCI0_BASE)
342 mask = 1;
343 else
344 mask = 2;
345
346 return readl(VERSATILE_SYSMCI) & mask;
347}
348
6ef297f8 349static struct mmci_platform_data mmc0_plat_data = {
1da177e4
LT		 350 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
351 .status = mmc_status,
7fb2bbf4
RK		 352 .gpio_wp = -1,
353 .gpio_cd = -1,
1da177e4
LT		 354};
355
356/*
357 * Clock handling
358 */
39c0cb02 359static const struct icst_params versatile_oscvco_params = {
64fceb1d 360 .ref = 24000000,
4de2edbd 361 .vco_max = ICST307_VCO_MAX,
e73a46a3 362 .vco_min = ICST307_VCO_MIN,
1da177e4
LT		 363 .vd_min = 4 + 8,
364 .vd_max = 511 + 8,
365 .rd_min = 1 + 2,
366 .rd_max = 127 + 2,
232eaf7f
RK		 367 .s2div = icst307_s2div,
368 .idx2s = icst307_idx2s,
1da177e4
LT		 369};
370
39c0cb02 371static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
1da177e4 372{
71a06da0
RK		 373 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
374 void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
1da177e4
LT		 375 u32 val;
376
71a06da0 377 val = readl(sys + clk->oscoff) & ~0x7ffff;
1da177e4
LT		 378 val |= vco.v | (vco.r << 9) | (vco.s << 16);
379
380 writel(0xa05f, sys_lock);
71a06da0 381 writel(val, sys + clk->oscoff);
1da177e4
LT		 382 writel(0, sys_lock);
383}
384
71a06da0 385static struct clk osc4_clk = {
1da177e4 386 .params = &versatile_oscvco_params,
71a06da0
RK		 387 .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
388 .setvco = versatile_oscvco_set,
389};
390
391/*
392 * These are fixed clocks.
393 */
394static struct clk ref24_clk = {
395 .rate = 24000000,
396};
397
982db663 398static struct clk_lookup lookups[] = {
71a06da0
RK		 399 { /* UART0 */
400 .dev_id = "dev:f1",
401 .clk = &ref24_clk,
402 }, { /* UART1 */
403 .dev_id = "dev:f2",
404 .clk = &ref24_clk,
405 }, { /* UART2 */
406 .dev_id = "dev:f3",
407 .clk = &ref24_clk,
408 }, { /* UART3 */
409 .dev_id = "fpga:09",
410 .clk = &ref24_clk,
411 }, { /* KMI0 */
412 .dev_id = "fpga:06",
413 .clk = &ref24_clk,
414 }, { /* KMI1 */
415 .dev_id = "fpga:07",
416 .clk = &ref24_clk,
417 }, { /* MMC0 */
418 .dev_id = "fpga:05",
419 .clk = &ref24_clk,
420 }, { /* MMC1 */
421 .dev_id = "fpga:0b",
422 .clk = &ref24_clk,
423 }, { /* CLCD */
424 .dev_id = "dev:20",
425 .clk = &osc4_clk,
426 }
1da177e4
LT		 427};
428
429/*
430 * CLCD support.
431 */
432#define SYS_CLCD_MODE_MASK (3 << 0)
433#define SYS_CLCD_MODE_888 (0 << 0)
434#define SYS_CLCD_MODE_5551 (1 << 0)
435#define SYS_CLCD_MODE_565_RLSB (2 << 0)
436#define SYS_CLCD_MODE_565_BLSB (3 << 0)
437#define SYS_CLCD_NLCDIOON (1 << 2)
438#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
439#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
440#define SYS_CLCD_ID_MASK (0x1f << 8)
441#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
442#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
443#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
444#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
445#define SYS_CLCD_ID_VGA (0x1f << 8)
446
447static struct clcd_panel vga = {
448 .mode = {
449 .name = "VGA",
450 .refresh = 60,
451 .xres = 640,
452 .yres = 480,
453 .pixclock = 39721,
454 .left_margin = 40,
455 .right_margin = 24,
456 .upper_margin = 32,
457 .lower_margin = 11,
458 .hsync_len = 96,
459 .vsync_len = 2,
460 .sync = 0,
461 .vmode = FB_VMODE_NONINTERLACED,
462 },
463 .width = -1,
464 .height = -1,
465 .tim2 = TIM2_BCD | TIM2_IPC,
466 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
467 .bpp = 16,
468};
469
470static struct clcd_panel sanyo_3_8_in = {
471 .mode = {
472 .name = "Sanyo QVGA",
473 .refresh = 116,
474 .xres = 320,
475 .yres = 240,
476 .pixclock = 100000,
477 .left_margin = 6,
478 .right_margin = 6,
479 .upper_margin = 5,
480 .lower_margin = 5,
481 .hsync_len = 6,
482 .vsync_len = 6,
483 .sync = 0,
484 .vmode = FB_VMODE_NONINTERLACED,
485 },
486 .width = -1,
487 .height = -1,
488 .tim2 = TIM2_BCD,
489 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
490 .bpp = 16,
491};
492
493static struct clcd_panel sanyo_2_5_in = {
494 .mode = {
495 .name = "Sanyo QVGA Portrait",
496 .refresh = 116,
497 .xres = 240,
498 .yres = 320,
499 .pixclock = 100000,
500 .left_margin = 20,
501 .right_margin = 10,
502 .upper_margin = 2,
503 .lower_margin = 2,
504 .hsync_len = 10,
505 .vsync_len = 2,
506 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
507 .vmode = FB_VMODE_NONINTERLACED,
508 },
509 .width = -1,
510 .height = -1,
511 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
512 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
513 .bpp = 16,
514};
515
516static struct clcd_panel epson_2_2_in = {
517 .mode = {
518 .name = "Epson QCIF",
519 .refresh = 390,
520 .xres = 176,
521 .yres = 220,
522 .pixclock = 62500,
523 .left_margin = 3,
524 .right_margin = 2,
525 .upper_margin = 1,
526 .lower_margin = 0,
527 .hsync_len = 3,
528 .vsync_len = 2,
529 .sync = 0,
530 .vmode = FB_VMODE_NONINTERLACED,
531 },
532 .width = -1,
533 .height = -1,
534 .tim2 = TIM2_BCD | TIM2_IPC,
535 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
536 .bpp = 16,
537};
538
539/*
540 * Detect which LCD panel is connected, and return the appropriate
541 * clcd_panel structure. Note: we do not have any information on
542 * the required timings for the 8.4in panel, so we presently assume
543 * VGA timings.
544 */
545static struct clcd_panel *versatile_clcd_panel(void)
546{
2ad4f86b 547 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 548 struct clcd_panel *panel = &vga;
549 u32 val;
550
551 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
552 if (val == SYS_CLCD_ID_SANYO_3_8)
553 panel = &sanyo_3_8_in;
554 else if (val == SYS_CLCD_ID_SANYO_2_5)
555 panel = &sanyo_2_5_in;
556 else if (val == SYS_CLCD_ID_EPSON_2_2)
557 panel = &epson_2_2_in;
558 else if (val == SYS_CLCD_ID_VGA)
559 panel = &vga;
560 else {
561 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
562 val);
563 panel = &vga;
564 }
565
566 return panel;
567}
568
569/*
570 * Disable all display connectors on the interface module.
571 */
572static void versatile_clcd_disable(struct clcd_fb *fb)
573{
2ad4f86b 574 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 575 u32 val;
576
577 val = readl(sys_clcd);
578 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
579 writel(val, sys_clcd);
580
581#ifdef CONFIG_MACH_VERSATILE_AB
582 /*
583 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
584 */
dc5bc8f1 585 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 586 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 587 unsigned long ctrl;
588
589 ctrl = readl(versatile_ib2_ctrl);
590 ctrl &= ~0x01;
591 writel(ctrl, versatile_ib2_ctrl);
592 }
593#endif
594}
595
596/*
597 * Enable the relevant connector on the interface module.
598 */
599static void versatile_clcd_enable(struct clcd_fb *fb)
600{
2ad4f86b 601 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
1da177e4
LT		 602 u32 val;
603
604 val = readl(sys_clcd);
605 val &= ~SYS_CLCD_MODE_MASK;
606
607 switch (fb->fb.var.green.length) {
608 case 5:
609 val |= SYS_CLCD_MODE_5551;
610 break;
611 case 6:
90ef713b 612 val |= SYS_CLCD_MODE_565_RLSB;
1da177e4
LT		 613 break;
614 case 8:
615 val |= SYS_CLCD_MODE_888;
616 break;
617 }
618
619 /*
620 * Set the MUX
621 */
622 writel(val, sys_clcd);
623
624 /*
625 * And now enable the PSUs
626 */
627 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
628 writel(val, sys_clcd);
629
630#ifdef CONFIG_MACH_VERSATILE_AB
631 /*
632 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
633 */
dc5bc8f1 634 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
2ad4f86b 635 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
1da177e4
LT		 636 unsigned long ctrl;
637
638 ctrl = readl(versatile_ib2_ctrl);
639 ctrl |= 0x01;
640 writel(ctrl, versatile_ib2_ctrl);
641 }
642#endif
643}
644
645static unsigned long framesize = SZ_1M;
646
647static int versatile_clcd_setup(struct clcd_fb *fb)
648{
649 dma_addr_t dma;
650
651 fb->panel = versatile_clcd_panel();
652
653 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
654 &dma, GFP_KERNEL);
655 if (!fb->fb.screen_base) {
656 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
657 return -ENOMEM;
658 }
659
660 fb->fb.fix.smem_start = dma;
661 fb->fb.fix.smem_len = framesize;
662
663 return 0;
664}
665
666static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
667{
668 return dma_mmap_writecombine(&fb->dev->dev, vma,
669 fb->fb.screen_base,
670 fb->fb.fix.smem_start,
671 fb->fb.fix.smem_len);
672}
673
674static void versatile_clcd_remove(struct clcd_fb *fb)
675{
676 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
677 fb->fb.screen_base, fb->fb.fix.smem_start);
678}
679
680static struct clcd_board clcd_plat_data = {
681 .name = "Versatile",
682 .check = clcdfb_check,
683 .decode = clcdfb_decode,
684 .disable = versatile_clcd_disable,
685 .enable = versatile_clcd_enable,
686 .setup = versatile_clcd_setup,
687 .mmap = versatile_clcd_mmap,
688 .remove = versatile_clcd_remove,
689};
690
bbeddc43
RK		 691static struct pl061_platform_data gpio0_plat_data = {
692 .gpio_base = 0,
693 .irq_base = IRQ_GPIO0_START,
694};
695
696static struct pl061_platform_data gpio1_plat_data = {
697 .gpio_base = 8,
698 .irq_base = IRQ_GPIO1_START,
699};
700
1da177e4
LT		 701#define AACI_IRQ { IRQ_AACI, NO_IRQ }
702#define AACI_DMA { 0x80, 0x81 }
703#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
704#define MMCI0_DMA { 0x84, 0 }
705#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
706#define KMI0_DMA { 0, 0 }
707#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
708#define KMI1_DMA { 0, 0 }
709
710/*
711 * These devices are connected directly to the multi-layer AHB switch
712 */
713#define SMC_IRQ { NO_IRQ, NO_IRQ }
714#define SMC_DMA { 0, 0 }
715#define MPMC_IRQ { NO_IRQ, NO_IRQ }
716#define MPMC_DMA { 0, 0 }
717#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
718#define CLCD_DMA { 0, 0 }
719#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
720#define DMAC_DMA { 0, 0 }
721
722/*
723 * These devices are connected via the core APB bridge
724 */
725#define SCTL_IRQ { NO_IRQ, NO_IRQ }
726#define SCTL_DMA { 0, 0 }
727#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
728#define WATCHDOG_DMA { 0, 0 }
729#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
730#define GPIO0_DMA { 0, 0 }
731#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
732#define GPIO1_DMA { 0, 0 }
733#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
734#define RTC_DMA { 0, 0 }
735
736/*
737 * These devices are connected via the DMA APB bridge
738 */
739#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
740#define SCI_DMA { 7, 6 }
741#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
742#define UART0_DMA { 15, 14 }
743#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
744#define UART1_DMA { 13, 12 }
745#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
746#define UART2_DMA { 11, 10 }
747#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
748#define SSP_DMA { 9, 8 }
749
750/* FPGA Primecells */
751AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
752AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
753AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
754AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
755
756/* DevChip Primecells */
757AMBA_DEVICE(smc, "dev:00", SMC, NULL);
758AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
759AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
760AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
761AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
762AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
bbeddc43
RK		 763AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
764AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
1da177e4
LT		 765AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
766AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
767AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
768AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
769AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
770AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
771
772static struct amba_device *amba_devs[] __initdata = {
773 &dmac_device,
774 &uart0_device,
775 &uart1_device,
776 &uart2_device,
777 &smc_device,
778 &mpmc_device,
779 &clcd_device,
780 &sctl_device,
781 &wdog_device,
782 &gpio0_device,
783 &gpio1_device,
784 &rtc_device,
785 &sci0_device,
786 &ssp0_device,
787 &aaci_device,
788 &mmc0_device,
789 &kmi0_device,
790 &kmi1_device,
791};
792
793#ifdef CONFIG_LEDS
2ad4f86b 794#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
1da177e4
LT		 795
796static void versatile_leds_event(led_event_t ledevt)
797{
798 unsigned long flags;
799 u32 val;
800
801 local_irq_save(flags);
802 val = readl(VA_LEDS_BASE);
803
804 switch (ledevt) {
805 case led_idle_start:
806 val = val & ~VERSATILE_SYS_LED0;
807 break;
808
809 case led_idle_end:
810 val = val | VERSATILE_SYS_LED0;
811 break;
812
813 case led_timer:
814 val = val ^ VERSATILE_SYS_LED1;
815 break;
816
817 case led_halted:
818 val = 0;
819 break;
820
821 default:
822 break;
823 }
824
825 writel(val, VA_LEDS_BASE);
826 local_irq_restore(flags);
827}
828#endif /* CONFIG_LEDS */
829
830void __init versatile_init(void)
831{
832 int i;
833
0a0300dc 834 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1da177e4
LT		 835
836 platform_device_register(&versatile_flash_device);
6b65cd74 837 platform_device_register(&versatile_i2c_device);
1da177e4
LT		 838 platform_device_register(&smc91x_device);
839
840 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
841 struct amba_device *d = amba_devs[i];
842 amba_device_register(d, &iomem_resource);
843 }
844
845#ifdef CONFIG_LEDS
846 leds_event = versatile_leds_event;
847#endif
848}
849
850/*
851 * Where is the timer (VA)?
852 */
2ad4f86b
AV		 853#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
854#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
855#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
856#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
b49c87c2 857
1da177e4
LT		 858/*
859 * Set up timer interrupt, and return the current time in seconds.
860 */
861static void __init versatile_timer_init(void)
862{
b720f732 863 u32 val;
1da177e4
LT		 864
865 /*
866 * set clock frequency:
867 * VERSATILE_REFCLK is 32KHz
868 * VERSATILE_TIMCLK is 1MHz
869 */
2ad4f86b 870 val = readl(__io_address(VERSATILE_SCTL_BASE));
b720f732
RK		 871 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
872 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
873 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
874 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
2ad4f86b 875 __io_address(VERSATILE_SCTL_BASE));
1da177e4
LT		 876
877 /*
878 * Initialise to a known state (all timers off)
879 */
b720f732
RK		 880 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
881 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
882 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
883 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
884
e3887714
RK		 885 sp804_clocksource_init(TIMER3_VA_BASE);
886 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
1da177e4
LT		 887}
888
889struct sys_timer versatile_timer = {
890 .init = versatile_timer_init,
1da177e4 891};
b49c87c2 892
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