[net-next-2.6.git] / arch / arm / mach-shmobile / setup-sh7372.c

/*
 * sh7372 processor support
 *
 * Copyright (C) 2010  Magnus Damm
 * Copyright (C) 2008  Yoshihiro Shimoda
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <mach/hardware.h>
#include <mach/sh7372.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

/* SCIFA0 */
static struct plat_sci_port scif0_platform_data = {
	.mapbase	= 0xe6c40000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIFA,
	.irqs		= { evt2irq(0x0c00), evt2irq(0x0c00),
			    evt2irq(0x0c00), evt2irq(0x0c00) },
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

/* SCIFA1 */
static struct plat_sci_port scif1_platform_data = {
	.mapbase	= 0xe6c50000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIFA,
	.irqs		= { evt2irq(0x0c20), evt2irq(0x0c20),
			    evt2irq(0x0c20), evt2irq(0x0c20) },
};

static struct platform_device scif1_device = {
	.name		= "sh-sci",
	.id		= 1,
	.dev		= {
		.platform_data	= &scif1_platform_data,
	},
};

/* SCIFA2 */
static struct plat_sci_port scif2_platform_data = {
	.mapbase	= 0xe6c60000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIFA,
	.irqs		= { evt2irq(0x0c40), evt2irq(0x0c40),
			    evt2irq(0x0c40), evt2irq(0x0c40) },
};

static struct platform_device scif2_device = {
	.name		= "sh-sci",
	.id		= 2,
	.dev		= {
		.platform_data	= &scif2_platform_data,
	},
};

/* SCIFA3 */
static struct plat_sci_port scif3_platform_data = {
	.mapbase	= 0xe6c70000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIFA,
	.irqs		= { evt2irq(0x0c60), evt2irq(0x0c60),
			    evt2irq(0x0c60), evt2irq(0x0c60) },
};

static struct platform_device scif3_device = {
	.name		= "sh-sci",
	.id		= 3,
	.dev		= {
		.platform_data	= &scif3_platform_data,
	},
};

/* SCIFA4 */
static struct plat_sci_port scif4_platform_data = {
	.mapbase	= 0xe6c80000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIFA,
	.irqs		= { evt2irq(0x0d20), evt2irq(0x0d20),
			    evt2irq(0x0d20), evt2irq(0x0d20) },
};

static struct platform_device scif4_device = {
	.name		= "sh-sci",
	.id		= 4,
	.dev		= {
		.platform_data	= &scif4_platform_data,
	},
};

/* SCIFA5 */
static struct plat_sci_port scif5_platform_data = {
	.mapbase	= 0xe6cb0000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIFA,
	.irqs		= { evt2irq(0x0d40), evt2irq(0x0d40),
			    evt2irq(0x0d40), evt2irq(0x0d40) },
};

static struct platform_device scif5_device = {
	.name		= "sh-sci",
	.id		= 5,
	.dev		= {
		.platform_data	= &scif5_platform_data,
	},
};

/* SCIFB */
static struct plat_sci_port scif6_platform_data = {
	.mapbase	= 0xe6c30000,
	.flags		= UPF_BOOT_AUTOCONF,
	.type		= PORT_SCIFB,
	.irqs		= { evt2irq(0x0d60), evt2irq(0x0d60),
			    evt2irq(0x0d60), evt2irq(0x0d60) },
};

static struct platform_device scif6_device = {
	.name		= "sh-sci",
	.id		= 6,
	.dev		= {
		.platform_data	= &scif6_platform_data,
	},
};

/* CMT */
static struct sh_timer_config cmt10_platform_data = {
	.name = "CMT10",
	.channel_offset = 0x10,
	.timer_bit = 0,
	.clockevent_rating = 125,
	.clocksource_rating = 125,
};

static struct resource cmt10_resources[] = {
	[0] = {
		.name	= "CMT10",
		.start	= 0xe6138010,
		.end	= 0xe613801b,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x0b00), /* CMT1_CMT10 */
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device cmt10_device = {
	.name		= "sh_cmt",
	.id		= 10,
	.dev = {
		.platform_data	= &cmt10_platform_data,
	},
	.resource	= cmt10_resources,
	.num_resources	= ARRAY_SIZE(cmt10_resources),
};

/* TMU */
static struct sh_timer_config tmu00_platform_data = {
	.name = "TMU00",
	.channel_offset = 0x4,
	.timer_bit = 0,
	.clockevent_rating = 200,
};

static struct resource tmu00_resources[] = {
	[0] = {
		.name	= "TMU00",
		.start	= 0xfff60008,
		.end	= 0xfff60013,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= intcs_evt2irq(0xe80), /* TMU_TUNI0 */
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu00_device = {
	.name		= "sh_tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu00_platform_data,
	},
	.resource	= tmu00_resources,
	.num_resources	= ARRAY_SIZE(tmu00_resources),
};

static struct sh_timer_config tmu01_platform_data = {
	.name = "TMU01",
	.channel_offset = 0x10,
	.timer_bit = 1,
	.clocksource_rating = 200,
};

static struct resource tmu01_resources[] = {
	[0] = {
		.name	= "TMU01",
		.start	= 0xfff60014,
		.end	= 0xfff6001f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= intcs_evt2irq(0xea0), /* TMU_TUNI1 */
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device tmu01_device = {
	.name		= "sh_tmu",
	.id		= 1,
	.dev = {
		.platform_data	= &tmu01_platform_data,
	},
	.resource	= tmu01_resources,
	.num_resources	= ARRAY_SIZE(tmu01_resources),
};

/* I2C */
static struct resource iic0_resources[] = {
	[0] = {
		.name	= "IIC0",
		.start  = 0xFFF20000,
		.end    = 0xFFF20425 - 1,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
		.end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device iic0_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic0_resources),
	.resource       = iic0_resources,
};

static struct resource iic1_resources[] = {
	[0] = {
		.name	= "IIC1",
		.start  = 0xE6C20000,
		.end    = 0xE6C20425 - 1,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0x780), /* IIC1_ALI1 */
		.end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device iic1_device = {
	.name           = "i2c-sh_mobile",
	.id             = 1, /* "i2c1" clock */
	.num_resources  = ARRAY_SIZE(iic1_resources),
	.resource       = iic1_resources,
};

/* DMA */
/* Transmit sizes and respective CHCR register values */
enum {
	XMIT_SZ_8BIT		= 0,
	XMIT_SZ_16BIT		= 1,
	XMIT_SZ_32BIT		= 2,
	XMIT_SZ_64BIT		= 7,
	XMIT_SZ_128BIT		= 3,
	XMIT_SZ_256BIT		= 4,
	XMIT_SZ_512BIT		= 5,
};

/* log2(size / 8) - used to calculate number of transfers */
#define TS_SHIFT {			\
	[XMIT_SZ_8BIT]		= 0,	\
	[XMIT_SZ_16BIT]		= 1,	\
	[XMIT_SZ_32BIT]		= 2,	\
	[XMIT_SZ_64BIT]		= 3,	\
	[XMIT_SZ_128BIT]	= 4,	\
	[XMIT_SZ_256BIT]	= 5,	\
	[XMIT_SZ_512BIT]	= 6,	\
}

#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
			 (((i) & 0xc) << (20 - 2)))

static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
	{
		.slave_id	= SHDMA_SLAVE_SCIF0_TX,
		.addr		= 0xe6c40020,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x21,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF0_RX,
		.addr		= 0xe6c40024,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x22,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF1_TX,
		.addr		= 0xe6c50020,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x25,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF1_RX,
		.addr		= 0xe6c50024,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x26,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF2_TX,
		.addr		= 0xe6c60020,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x29,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF2_RX,
		.addr		= 0xe6c60024,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x2a,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF3_TX,
		.addr		= 0xe6c70020,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x2d,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF3_RX,
		.addr		= 0xe6c70024,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x2e,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF4_TX,
		.addr		= 0xe6c80020,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x39,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF4_RX,
		.addr		= 0xe6c80024,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x3a,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF5_TX,
		.addr		= 0xe6cb0020,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x35,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF5_RX,
		.addr		= 0xe6cb0024,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x36,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF6_TX,
		.addr		= 0xe6c30040,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x3d,
	}, {
		.slave_id	= SHDMA_SLAVE_SCIF6_RX,
		.addr		= 0xe6c30060,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
		.mid_rid	= 0x3e,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI0_TX,
		.addr		= 0xe6850030,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
		.mid_rid	= 0xc1,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI0_RX,
		.addr		= 0xe6850030,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
		.mid_rid	= 0xc2,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI1_TX,
		.addr		= 0xe6860030,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
		.mid_rid	= 0xc9,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI1_RX,
		.addr		= 0xe6860030,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
		.mid_rid	= 0xca,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI2_TX,
		.addr		= 0xe6870030,
		.chcr		= DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
		.mid_rid	= 0xcd,
	}, {
		.slave_id	= SHDMA_SLAVE_SDHI2_RX,
		.addr		= 0xe6870030,
		.chcr		= DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
		.mid_rid	= 0xce,
	},
};

static const struct sh_dmae_channel sh7372_dmae_channels[] = {
	{
		.offset = 0,
		.dmars = 0,
		.dmars_bit = 0,
	}, {
		.offset = 0x10,
		.dmars = 0,
		.dmars_bit = 8,
	}, {
		.offset = 0x20,
		.dmars = 4,
		.dmars_bit = 0,
	}, {
		.offset = 0x30,
		.dmars = 4,
		.dmars_bit = 8,
	}, {
		.offset = 0x50,
		.dmars = 8,
		.dmars_bit = 0,
	}, {
		.offset = 0x60,
		.dmars = 8,
		.dmars_bit = 8,
	}
};

static const unsigned int ts_shift[] = TS_SHIFT;

static struct sh_dmae_pdata dma_platform_data = {
	.slave		= sh7372_dmae_slaves,
	.slave_num	= ARRAY_SIZE(sh7372_dmae_slaves),
	.channel	= sh7372_dmae_channels,
	.channel_num	= ARRAY_SIZE(sh7372_dmae_channels),
	.ts_low_shift	= 3,
	.ts_low_mask	= 0x18,
	.ts_high_shift	= (20 - 2),	/* 2 bits for shifted low TS */
	.ts_high_mask	= 0x00300000,
	.ts_shift	= ts_shift,
	.ts_shift_num	= ARRAY_SIZE(ts_shift),
	.dmaor_init	= DMAOR_DME,
};

/* Resource order important! */
static struct resource sh7372_dmae0_resources[] = {
	{
		/* Channel registers and DMAOR */
		.start	= 0xfe008020,
		.end	= 0xfe00808f,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMARSx */
		.start	= 0xfe009000,
		.end	= 0xfe00900b,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMA error IRQ */
		.start	= evt2irq(0x20c0),
		.end	= evt2irq(0x20c0),
		.flags	= IORESOURCE_IRQ,
	},
	{
		/* IRQ for channels 0-5 */
		.start	= evt2irq(0x2000),
		.end	= evt2irq(0x20a0),
		.flags	= IORESOURCE_IRQ,
	},
};

/* Resource order important! */
static struct resource sh7372_dmae1_resources[] = {
	{
		/* Channel registers and DMAOR */
		.start	= 0xfe018020,
		.end	= 0xfe01808f,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMARSx */
		.start	= 0xfe019000,
		.end	= 0xfe01900b,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMA error IRQ */
		.start	= evt2irq(0x21c0),
		.end	= evt2irq(0x21c0),
		.flags	= IORESOURCE_IRQ,
	},
	{
		/* IRQ for channels 0-5 */
		.start	= evt2irq(0x2100),
		.end	= evt2irq(0x21a0),
		.flags	= IORESOURCE_IRQ,
	},
};

/* Resource order important! */
static struct resource sh7372_dmae2_resources[] = {
	{
		/* Channel registers and DMAOR */
		.start	= 0xfe028020,
		.end	= 0xfe02808f,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMARSx */
		.start	= 0xfe029000,
		.end	= 0xfe02900b,
		.flags	= IORESOURCE_MEM,
	},
	{
		/* DMA error IRQ */
		.start	= evt2irq(0x22c0),
		.end	= evt2irq(0x22c0),
		.flags	= IORESOURCE_IRQ,
	},
	{
		/* IRQ for channels 0-5 */
		.start	= evt2irq(0x2200),
		.end	= evt2irq(0x22a0),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dma0_device = {
	.name		= "sh-dma-engine",
	.id		= 0,
	.resource	= sh7372_dmae0_resources,
	.num_resources	= ARRAY_SIZE(sh7372_dmae0_resources),
	.dev		= {
		.platform_data	= &dma_platform_data,
	},
};

static struct platform_device dma1_device = {
	.name		= "sh-dma-engine",
	.id		= 1,
	.resource	= sh7372_dmae1_resources,
	.num_resources	= ARRAY_SIZE(sh7372_dmae1_resources),
	.dev		= {
		.platform_data	= &dma_platform_data,
	},
};

static struct platform_device dma2_device = {
	.name		= "sh-dma-engine",
	.id		= 2,
	.resource	= sh7372_dmae2_resources,
	.num_resources	= ARRAY_SIZE(sh7372_dmae2_resources),
	.dev		= {
		.platform_data	= &dma_platform_data,
	},
};

static struct platform_device *sh7372_early_devices[] __initdata = {
	&scif0_device,
	&scif1_device,
	&scif2_device,
	&scif3_device,
	&scif4_device,
	&scif5_device,
	&scif6_device,
	&cmt10_device,
	&tmu00_device,
	&tmu01_device,
};

static struct platform_device *sh7372_late_devices[] __initdata = {
	&iic0_device,
	&iic1_device,
	&dma0_device,
	&dma1_device,
	&dma2_device,
};

void __init sh7372_add_standard_devices(void)
{
	platform_add_devices(sh7372_early_devices,
			    ARRAY_SIZE(sh7372_early_devices));

	platform_add_devices(sh7372_late_devices,
			    ARRAY_SIZE(sh7372_late_devices));
}

void __init sh7372_add_early_devices(void)
{
	early_platform_add_devices(sh7372_early_devices,
				   ARRAY_SIZE(sh7372_early_devices));
}
Commit	Line	Data
2b7eda63 MD	1	/*
	2	* sh7372 processor support
	3	*
	4	* Copyright (C) 2010 Magnus Damm
	5	* Copyright (C) 2008 Yoshihiro Shimoda
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/irq.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/delay.h>
	26	#include <linux/input.h>
	27	#include <linux/io.h>
	28	#include <linux/serial_sci.h>
69bf6f45	29	#include <linux/sh_dma.h>
2b7eda63 MD	30	#include <linux/sh_intc.h>
	31	#include <linux/sh_timer.h>
	32	#include <mach/hardware.h>
69bf6f45	33	#include <mach/sh7372.h>
2b7eda63 MD	34	#include <asm/mach-types.h>
	35	#include <asm/mach/arch.h>
	36
33c9607a	37	/* SCIFA0 */
2b7eda63 MD	38	static struct plat_sci_port scif0_platform_data = {
	39	.mapbase = 0xe6c40000,
	40	.flags = UPF_BOOT_AUTOCONF,
eb6e8605	41	.type = PORT_SCIFA,
33c9607a MD	42	.irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
33c9607a MD	43	evt2irq(0x0c00), evt2irq(0x0c00) },
2b7eda63 MD	44	};
	45
	46	static struct platform_device scif0_device = {
	47	.name = "sh-sci",
	48	.id = 0,
	49	.dev = {
	50	.platform_data = &scif0_platform_data,
	51	},
	52	};
	53
33c9607a	54	/* SCIFA1 */
2b7eda63 MD	55	static struct plat_sci_port scif1_platform_data = {
	56	.mapbase = 0xe6c50000,
	57	.flags = UPF_BOOT_AUTOCONF,
eb6e8605	58	.type = PORT_SCIFA,
33c9607a MD	59	.irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
33c9607a MD	60	evt2irq(0x0c20), evt2irq(0x0c20) },
2b7eda63 MD	61	};
	62
	63	static struct platform_device scif1_device = {
	64	.name = "sh-sci",
	65	.id = 1,
	66	.dev = {
	67	.platform_data = &scif1_platform_data,
	68	},
	69	};
	70
33c9607a	71	/* SCIFA2 */
2b7eda63 MD	72	static struct plat_sci_port scif2_platform_data = {
	73	.mapbase = 0xe6c60000,
	74	.flags = UPF_BOOT_AUTOCONF,
eb6e8605	75	.type = PORT_SCIFA,
33c9607a MD	76	.irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
33c9607a MD	77	evt2irq(0x0c40), evt2irq(0x0c40) },
2b7eda63 MD	78	};
	79
	80	static struct platform_device scif2_device = {
	81	.name = "sh-sci",
	82	.id = 2,
	83	.dev = {
	84	.platform_data = &scif2_platform_data,
	85	},
	86	};
	87
33c9607a	88	/* SCIFA3 */
2b7eda63 MD	89	static struct plat_sci_port scif3_platform_data = {
	90	.mapbase = 0xe6c70000,
	91	.flags = UPF_BOOT_AUTOCONF,
eb6e8605	92	.type = PORT_SCIFA,
33c9607a MD	93	.irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
33c9607a MD	94	evt2irq(0x0c60), evt2irq(0x0c60) },
2b7eda63 MD	95	};
	96
	97	static struct platform_device scif3_device = {
	98	.name = "sh-sci",
	99	.id = 3,
	100	.dev = {
	101	.platform_data = &scif3_platform_data,
	102	},
	103	};
	104
33c9607a	105	/* SCIFA4 */
2b7eda63 MD	106	static struct plat_sci_port scif4_platform_data = {
	107	.mapbase = 0xe6c80000,
	108	.flags = UPF_BOOT_AUTOCONF,
eb6e8605	109	.type = PORT_SCIFA,
33c9607a MD	110	.irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
33c9607a MD	111	evt2irq(0x0d20), evt2irq(0x0d20) },
2b7eda63 MD	112	};
	113
	114	static struct platform_device scif4_device = {
	115	.name = "sh-sci",
	116	.id = 4,
	117	.dev = {
	118	.platform_data = &scif4_platform_data,
	119	},
	120	};
	121
33c9607a	122	/* SCIFA5 */
2b7eda63 MD	123	static struct plat_sci_port scif5_platform_data = {
	124	.mapbase = 0xe6cb0000,
	125	.flags = UPF_BOOT_AUTOCONF,
eb6e8605	126	.type = PORT_SCIFA,
33c9607a MD	127	.irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
33c9607a MD	128	evt2irq(0x0d40), evt2irq(0x0d40) },
2b7eda63 MD	129	};
	130
	131	static struct platform_device scif5_device = {
	132	.name = "sh-sci",
	133	.id = 5,
	134	.dev = {
	135	.platform_data = &scif5_platform_data,
	136	},
	137	};
	138
33c9607a	139	/* SCIFB */
2b7eda63 MD	140	static struct plat_sci_port scif6_platform_data = {
	141	.mapbase = 0xe6c30000,
	142	.flags = UPF_BOOT_AUTOCONF,
eb6e8605	143	.type = PORT_SCIFB,
33c9607a MD	144	.irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
33c9607a MD	145	evt2irq(0x0d60), evt2irq(0x0d60) },
2b7eda63 MD	146	};
	147
	148	static struct platform_device scif6_device = {
	149	.name = "sh-sci",
	150	.id = 6,
	151	.dev = {
	152	.platform_data = &scif6_platform_data,
	153	},
	154	};
	155
c1909cc1	156	/* CMT */
2b7eda63 MD	157	static struct sh_timer_config cmt10_platform_data = {
	158	.name = "CMT10",
	159	.channel_offset = 0x10,
	160	.timer_bit = 0,
2b7eda63 MD	161	.clockevent_rating = 125,
	162	.clocksource_rating = 125,
	163	};
	164
	165	static struct resource cmt10_resources[] = {
	166	[0] = {
	167	.name = "CMT10",
	168	.start = 0xe6138010,
	169	.end = 0xe613801b,
	170	.flags = IORESOURCE_MEM,
	171	},
	172	[1] = {
33c9607a	173	.start = evt2irq(0x0b00), /* CMT1_CMT10 */
2b7eda63 MD	174	.flags = IORESOURCE_IRQ,
	175	},
	176	};
	177
	178	static struct platform_device cmt10_device = {
	179	.name = "sh_cmt",
	180	.id = 10,
	181	.dev = {
	182	.platform_data = &cmt10_platform_data,
	183	},
	184	.resource = cmt10_resources,
	185	.num_resources = ARRAY_SIZE(cmt10_resources),
	186	};
	187
c6c049ec MD	188	/* TMU */
	189	static struct sh_timer_config tmu00_platform_data = {
	190	.name = "TMU00",
	191	.channel_offset = 0x4,
	192	.timer_bit = 0,
	193	.clockevent_rating = 200,
	194	};
	195
	196	static struct resource tmu00_resources[] = {
	197	[0] = {
	198	.name = "TMU00",
	199	.start = 0xfff60008,
	200	.end = 0xfff60013,
	201	.flags = IORESOURCE_MEM,
	202	},
	203	[1] = {
	204	.start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
	205	.flags = IORESOURCE_IRQ,
	206	},
	207	};
	208
	209	static struct platform_device tmu00_device = {
	210	.name = "sh_tmu",
	211	.id = 0,
	212	.dev = {
	213	.platform_data = &tmu00_platform_data,
	214	},
	215	.resource = tmu00_resources,
	216	.num_resources = ARRAY_SIZE(tmu00_resources),
	217	};
	218
	219	static struct sh_timer_config tmu01_platform_data = {
	220	.name = "TMU01",
	221	.channel_offset = 0x10,
	222	.timer_bit = 1,
	223	.clocksource_rating = 200,
	224	};
	225
	226	static struct resource tmu01_resources[] = {
	227	[0] = {
	228	.name = "TMU01",
	229	.start = 0xfff60014,
	230	.end = 0xfff6001f,
	231	.flags = IORESOURCE_MEM,
	232	},
	233	[1] = {
	234	.start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
	235	.flags = IORESOURCE_IRQ,
	236	},
	237	};
	238
	239	static struct platform_device tmu01_device = {
	240	.name = "sh_tmu",
	241	.id = 1,
	242	.dev = {
	243	.platform_data = &tmu01_platform_data,
	244	},
	245	.resource = tmu01_resources,
	246	.num_resources = ARRAY_SIZE(tmu01_resources),
	247	};
	248
c1909cc1 KM	249	/* I2C */
	250	static struct resource iic0_resources[] = {
	251	[0] = {
	252	.name = "IIC0",
	253	.start = 0xFFF20000,
	254	.end = 0xFFF20425 - 1,
	255	.flags = IORESOURCE_MEM,
	256	},
	257	[1] = {
33c9607a MD	258	.start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
33c9607a MD	259	.end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
c1909cc1 KM	260	.flags = IORESOURCE_IRQ,
	261	},
	262	};
	263
	264	static struct platform_device iic0_device = {
	265	.name = "i2c-sh_mobile",
	266	.id = 0, /* "i2c0" clock */
	267	.num_resources = ARRAY_SIZE(iic0_resources),
	268	.resource = iic0_resources,
	269	};
	270
	271	static struct resource iic1_resources[] = {
	272	[0] = {
	273	.name = "IIC1",
	274	.start = 0xE6C20000,
	275	.end = 0xE6C20425 - 1,
	276	.flags = IORESOURCE_MEM,
	277	},
	278	[1] = {
33c9607a MD	279	.start = evt2irq(0x780), /* IIC1_ALI1 */
33c9607a MD	280	.end = evt2irq(0x7e0), /* IIC1_DTEI1 */
c1909cc1 KM	281	.flags = IORESOURCE_IRQ,
	282	},
	283	};
	284
	285	static struct platform_device iic1_device = {
	286	.name = "i2c-sh_mobile",
	287	.id = 1, /* "i2c1" clock */
	288	.num_resources = ARRAY_SIZE(iic1_resources),
	289	.resource = iic1_resources,
	290	};
	291
69bf6f45 GL	292	/* DMA */
	293	/* Transmit sizes and respective CHCR register values */
	294	enum {
	295	XMIT_SZ_8BIT = 0,
	296	XMIT_SZ_16BIT = 1,
	297	XMIT_SZ_32BIT = 2,
	298	XMIT_SZ_64BIT = 7,
	299	XMIT_SZ_128BIT = 3,
	300	XMIT_SZ_256BIT = 4,
	301	XMIT_SZ_512BIT = 5,
	302	};
	303
	304	/* log2(size / 8) - used to calculate number of transfers */
	305	#define TS_SHIFT { \
	306	[XMIT_SZ_8BIT] = 0, \
	307	[XMIT_SZ_16BIT] = 1, \
	308	[XMIT_SZ_32BIT] = 2, \
	309	[XMIT_SZ_64BIT] = 3, \
	310	[XMIT_SZ_128BIT] = 4, \
	311	[XMIT_SZ_256BIT] = 5, \
	312	[XMIT_SZ_512BIT] = 6, \
	313	}
	314
	315	#define TS_INDEX2VAL(i) ((((i) & 3) << 3) \| \
	316	(((i) & 0xc) << (20 - 2)))
	317
	318	static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
	319	{
8d3e17ba GL	320	.slave_id = SHDMA_SLAVE_SCIF0_TX,
	321	.addr = 0xe6c40020,
	322	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	323	.mid_rid = 0x21,
	324	}, {
	325	.slave_id = SHDMA_SLAVE_SCIF0_RX,
	326	.addr = 0xe6c40024,
	327	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	328	.mid_rid = 0x22,
	329	}, {
	330	.slave_id = SHDMA_SLAVE_SCIF1_TX,
	331	.addr = 0xe6c50020,
	332	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	333	.mid_rid = 0x25,
	334	}, {
	335	.slave_id = SHDMA_SLAVE_SCIF1_RX,
	336	.addr = 0xe6c50024,
	337	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	338	.mid_rid = 0x26,
	339	}, {
	340	.slave_id = SHDMA_SLAVE_SCIF2_TX,
	341	.addr = 0xe6c60020,
	342	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	343	.mid_rid = 0x29,
	344	}, {
	345	.slave_id = SHDMA_SLAVE_SCIF2_RX,
	346	.addr = 0xe6c60024,
	347	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	348	.mid_rid = 0x2a,
	349	}, {
	350	.slave_id = SHDMA_SLAVE_SCIF3_TX,
	351	.addr = 0xe6c70020,
	352	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	353	.mid_rid = 0x2d,
	354	}, {
	355	.slave_id = SHDMA_SLAVE_SCIF3_RX,
	356	.addr = 0xe6c70024,
	357	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	358	.mid_rid = 0x2e,
	359	}, {
	360	.slave_id = SHDMA_SLAVE_SCIF4_TX,
	361	.addr = 0xe6c80020,
	362	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	363	.mid_rid = 0x39,
	364	}, {
	365	.slave_id = SHDMA_SLAVE_SCIF4_RX,
	366	.addr = 0xe6c80024,
	367	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	368	.mid_rid = 0x3a,
	369	}, {
	370	.slave_id = SHDMA_SLAVE_SCIF5_TX,
	371	.addr = 0xe6cb0020,
	372	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	373	.mid_rid = 0x35,
	374	}, {
	375	.slave_id = SHDMA_SLAVE_SCIF5_RX,
	376	.addr = 0xe6cb0024,
	377	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	378	.mid_rid = 0x36,
	379	}, {
	380	.slave_id = SHDMA_SLAVE_SCIF6_TX,
	381	.addr = 0xe6c30040,
	382	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
	383	.mid_rid = 0x3d,
384	}, {
385	.slave_id = SHDMA_SLAVE_SCIF6_RX,
386	.addr = 0xe6c30060,
387	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_8BIT),
388	.mid_rid = 0x3e,
389	}, {
69bf6f45 GL	390	.slave_id = SHDMA_SLAVE_SDHI0_TX,
	391	.addr = 0xe6850030,
	392	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_16BIT),
	393	.mid_rid = 0xc1,
	394	}, {
	395	.slave_id = SHDMA_SLAVE_SDHI0_RX,
	396	.addr = 0xe6850030,
	397	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_16BIT),
	398	.mid_rid = 0xc2,
	399	}, {
	400	.slave_id = SHDMA_SLAVE_SDHI1_TX,
	401	.addr = 0xe6860030,
	402	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_16BIT),
	403	.mid_rid = 0xc9,
	404	}, {
	405	.slave_id = SHDMA_SLAVE_SDHI1_RX,
	406	.addr = 0xe6860030,
	407	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_16BIT),
	408	.mid_rid = 0xca,
	409	}, {
	410	.slave_id = SHDMA_SLAVE_SDHI2_TX,
	411	.addr = 0xe6870030,
	412	.chcr = DM_FIX \| SM_INC \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_16BIT),
	413	.mid_rid = 0xcd,
	414	}, {
	415	.slave_id = SHDMA_SLAVE_SDHI2_RX,
	416	.addr = 0xe6870030,
	417	.chcr = DM_INC \| SM_FIX \| 0x800 \| TS_INDEX2VAL(XMIT_SZ_16BIT),
	418	.mid_rid = 0xce,
	419	},
	420	};
	421
	422	static const struct sh_dmae_channel sh7372_dmae_channels[] = {
	423	{
	424	.offset = 0,
	425	.dmars = 0,
	426	.dmars_bit = 0,
	427	}, {
	428	.offset = 0x10,
	429	.dmars = 0,
	430	.dmars_bit = 8,
	431	}, {
	432	.offset = 0x20,
	433	.dmars = 4,
	434	.dmars_bit = 0,
	435	}, {
	436	.offset = 0x30,
	437	.dmars = 4,
	438	.dmars_bit = 8,
	439	}, {
	440	.offset = 0x50,
	441	.dmars = 8,
	442	.dmars_bit = 0,
	443	}, {
	444	.offset = 0x60,
	445	.dmars = 8,
	446	.dmars_bit = 8,
	447	}
	448	};
	449
	450	static const unsigned int ts_shift[] = TS_SHIFT;
	451
	452	static struct sh_dmae_pdata dma_platform_data = {
	453	.slave = sh7372_dmae_slaves,
454	.slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
455	.channel = sh7372_dmae_channels,
456	.channel_num = ARRAY_SIZE(sh7372_dmae_channels),
457	.ts_low_shift = 3,
458	.ts_low_mask = 0x18,
459	.ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
460	.ts_high_mask = 0x00300000,
461	.ts_shift = ts_shift,
462	.ts_shift_num = ARRAY_SIZE(ts_shift),
463	.dmaor_init = DMAOR_DME,
464	};
465
466	/* Resource order important! */
467	static struct resource sh7372_dmae0_resources[] = {
468	{
469	/* Channel registers and DMAOR */
470	.start = 0xfe008020,
471	.end = 0xfe00808f,
472	.flags = IORESOURCE_MEM,
473	},
474	{
475	/* DMARSx */
476	.start = 0xfe009000,
477	.end = 0xfe00900b,
478	.flags = IORESOURCE_MEM,
479	},
480	{
481	/* DMA error IRQ */
f989ae5b MD	482	.start = evt2irq(0x20c0),
f989ae5b MD	483	.end = evt2irq(0x20c0),
69bf6f45 GL	484	.flags = IORESOURCE_IRQ,
	485	},
	486	{
	487	/* IRQ for channels 0-5 */
f989ae5b MD	488	.start = evt2irq(0x2000),
f989ae5b MD	489	.end = evt2irq(0x20a0),
69bf6f45 GL	490	.flags = IORESOURCE_IRQ,
	491	},
	492	};
	493
	494	/* Resource order important! */
	495	static struct resource sh7372_dmae1_resources[] = {
	496	{
	497	/* Channel registers and DMAOR */
	498	.start = 0xfe018020,
	499	.end = 0xfe01808f,
	500	.flags = IORESOURCE_MEM,
	501	},
	502	{
	503	/* DMARSx */
	504	.start = 0xfe019000,
	505	.end = 0xfe01900b,
	506	.flags = IORESOURCE_MEM,
	507	},
	508	{
	509	/* DMA error IRQ */
f989ae5b MD	510	.start = evt2irq(0x21c0),
f989ae5b MD	511	.end = evt2irq(0x21c0),
69bf6f45 GL	512	.flags = IORESOURCE_IRQ,
	513	},
	514	{
	515	/* IRQ for channels 0-5 */
f989ae5b MD	516	.start = evt2irq(0x2100),
f989ae5b MD	517	.end = evt2irq(0x21a0),
69bf6f45 GL	518	.flags = IORESOURCE_IRQ,
	519	},
	520	};
	521
	522	/* Resource order important! */
	523	static struct resource sh7372_dmae2_resources[] = {
	524	{
	525	/* Channel registers and DMAOR */
	526	.start = 0xfe028020,
	527	.end = 0xfe02808f,
	528	.flags = IORESOURCE_MEM,
	529	},
	530	{
	531	/* DMARSx */
	532	.start = 0xfe029000,
	533	.end = 0xfe02900b,
	534	.flags = IORESOURCE_MEM,
	535	},
	536	{
	537	/* DMA error IRQ */
f989ae5b MD	538	.start = evt2irq(0x22c0),
f989ae5b MD	539	.end = evt2irq(0x22c0),
69bf6f45 GL	540	.flags = IORESOURCE_IRQ,
	541	},
	542	{
	543	/* IRQ for channels 0-5 */
f989ae5b MD	544	.start = evt2irq(0x2200),
f989ae5b MD	545	.end = evt2irq(0x22a0),
69bf6f45 GL	546	.flags = IORESOURCE_IRQ,
	547	},
	548	};
	549
	550	static struct platform_device dma0_device = {
	551	.name = "sh-dma-engine",
	552	.id = 0,
	553	.resource = sh7372_dmae0_resources,
	554	.num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
	555	.dev = {
	556	.platform_data = &dma_platform_data,
	557	},
	558	};
	559
	560	static struct platform_device dma1_device = {
	561	.name = "sh-dma-engine",
	562	.id = 1,
	563	.resource = sh7372_dmae1_resources,
	564	.num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
	565	.dev = {
	566	.platform_data = &dma_platform_data,
	567	},
	568	};
	569
	570	static struct platform_device dma2_device = {
	571	.name = "sh-dma-engine",
	572	.id = 2,
	573	.resource = sh7372_dmae2_resources,
	574	.num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
	575	.dev = {
	576	.platform_data = &dma_platform_data,
	577	},
	578	};
	579
2b7eda63 MD	580	static struct platform_device *sh7372_early_devices[] __initdata = {
	581	&scif0_device,
	582	&scif1_device,
	583	&scif2_device,
	584	&scif3_device,
	585	&scif4_device,
	586	&scif5_device,
	587	&scif6_device,
	588	&cmt10_device,
c6c049ec MD	589	&tmu00_device,
c6c049ec MD	590	&tmu01_device,
934e4078 MD	591	};
	592
	593	static struct platform_device *sh7372_late_devices[] __initdata = {
c1909cc1 KM	594	&iic0_device,
c1909cc1 KM	595	&iic1_device,
69bf6f45 GL	596	&dma0_device,
	597	&dma1_device,
	598	&dma2_device,
2b7eda63 MD	599	};
	600
	601	void __init sh7372_add_standard_devices(void)
	602	{
	603	platform_add_devices(sh7372_early_devices,
	604	ARRAY_SIZE(sh7372_early_devices));
934e4078 MD	605
	606	platform_add_devices(sh7372_late_devices,
	607	ARRAY_SIZE(sh7372_late_devices));
2b7eda63 MD	608	}
2b7eda63 MD	609
2b7eda63 MD	610	void __init sh7372_add_early_devices(void)
2b7eda63 MD	611	{
2b7eda63 MD	612	early_platform_add_devices(sh7372_early_devices,
	613	ARRAY_SIZE(sh7372_early_devices));
	614	}