[net-next-2.6.git] / arch / arm / mach-s5pv210 / include / mach / regs-clock.h

/* linux/arch/arm/mach-s5pv210/include/mach/regs-clock.h
 *
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * S5PV210 - Clock register definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__

#include <mach/map.h>

#define S5P_CLKREG(x)		(S3C_VA_SYS + (x))

#define S5P_APLL_LOCK		S5P_CLKREG(0x00)
#define S5P_MPLL_LOCK		S5P_CLKREG(0x08)
#define S5P_EPLL_LOCK		S5P_CLKREG(0x10)
#define S5P_VPLL_LOCK		S5P_CLKREG(0x20)

#define S5P_APLL_CON		S5P_CLKREG(0x100)
#define S5P_MPLL_CON		S5P_CLKREG(0x108)
#define S5P_EPLL_CON		S5P_CLKREG(0x110)
#define S5P_VPLL_CON		S5P_CLKREG(0x120)

#define S5P_CLK_SRC0		S5P_CLKREG(0x200)
#define S5P_CLK_SRC1		S5P_CLKREG(0x204)
#define S5P_CLK_SRC2		S5P_CLKREG(0x208)
#define S5P_CLK_SRC3		S5P_CLKREG(0x20C)
#define S5P_CLK_SRC4		S5P_CLKREG(0x210)
#define S5P_CLK_SRC5		S5P_CLKREG(0x214)
#define S5P_CLK_SRC6		S5P_CLKREG(0x218)

#define S5P_CLK_SRC_MASK0	S5P_CLKREG(0x280)
#define S5P_CLK_SRC_MASK1	S5P_CLKREG(0x284)

#define S5P_CLK_DIV0		S5P_CLKREG(0x300)
#define S5P_CLK_DIV1		S5P_CLKREG(0x304)
#define S5P_CLK_DIV2		S5P_CLKREG(0x308)
#define S5P_CLK_DIV3		S5P_CLKREG(0x30C)
#define S5P_CLK_DIV4		S5P_CLKREG(0x310)
#define S5P_CLK_DIV5		S5P_CLKREG(0x314)
#define S5P_CLK_DIV6		S5P_CLKREG(0x318)
#define S5P_CLK_DIV7		S5P_CLKREG(0x31C)

#define S5P_CLKGATE_MAIN0	S5P_CLKREG(0x400)
#define S5P_CLKGATE_MAIN1	S5P_CLKREG(0x404)
#define S5P_CLKGATE_MAIN2	S5P_CLKREG(0x408)

#define S5P_CLKGATE_PERI0	S5P_CLKREG(0x420)
#define S5P_CLKGATE_PERI1	S5P_CLKREG(0x424)

#define S5P_CLKGATE_SCLK0	S5P_CLKREG(0x440)
#define S5P_CLKGATE_SCLK1	S5P_CLKREG(0x444)
#define S5P_CLKGATE_IP0		S5P_CLKREG(0x460)
#define S5P_CLKGATE_IP1		S5P_CLKREG(0x464)
#define S5P_CLKGATE_IP2		S5P_CLKREG(0x468)
#define S5P_CLKGATE_IP3		S5P_CLKREG(0x46C)
#define S5P_CLKGATE_IP4		S5P_CLKREG(0x470)

#define S5P_CLKGATE_BLOCK	S5P_CLKREG(0x480)
#define S5P_CLKGATE_BUS0	S5P_CLKREG(0x484)
#define S5P_CLKGATE_BUS1	S5P_CLKREG(0x488)
#define S5P_CLK_OUT		S5P_CLKREG(0x500)

/* CLKSRC0 */
#define S5P_CLKSRC0_MUX200_MASK		(0x1<<16)
#define S5P_CLKSRC0_MUX166_MASK		(0x1<<20)
#define S5P_CLKSRC0_MUX133_MASK		(0x1<<24)

/* CLKDIV0 */
#define S5P_CLKDIV0_APLL_SHIFT		(0)
#define S5P_CLKDIV0_APLL_MASK		(0x7 << S5P_CLKDIV0_APLL_SHIFT)
#define S5P_CLKDIV0_A2M_SHIFT		(4)
#define S5P_CLKDIV0_A2M_MASK		(0x7 << S5P_CLKDIV0_A2M_SHIFT)
#define S5P_CLKDIV0_HCLK200_SHIFT	(8)
#define S5P_CLKDIV0_HCLK200_MASK	(0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
#define S5P_CLKDIV0_PCLK100_SHIFT	(12)
#define S5P_CLKDIV0_PCLK100_MASK	(0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
#define S5P_CLKDIV0_HCLK166_SHIFT	(16)
#define S5P_CLKDIV0_HCLK166_MASK	(0xF << S5P_CLKDIV0_HCLK166_SHIFT)
#define S5P_CLKDIV0_PCLK83_SHIFT	(20)
#define S5P_CLKDIV0_PCLK83_MASK		(0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
#define S5P_CLKDIV0_HCLK133_SHIFT	(24)
#define S5P_CLKDIV0_HCLK133_MASK	(0xF << S5P_CLKDIV0_HCLK133_SHIFT)
#define S5P_CLKDIV0_PCLK66_SHIFT	(28)
#define S5P_CLKDIV0_PCLK66_MASK		(0x7 << S5P_CLKDIV0_PCLK66_SHIFT)

#define S5P_SWRESET		S5P_CLKREG(0x2000)

/* Registers related to power management */
#define S5P_PWR_CFG		S5P_CLKREG(0xC000)
#define S5P_EINT_WAKEUP_MASK	S5P_CLKREG(0xC004)
#define S5P_WAKEUP_MASK 	S5P_CLKREG(0xC008)
#define S5P_PWR_MODE		S5P_CLKREG(0xC00C)
#define S5P_NORMAL_CFG		S5P_CLKREG(0xC010)
#define S5P_IDLE_CFG		S5P_CLKREG(0xC020)
#define S5P_STOP_CFG		S5P_CLKREG(0xC030)
#define S5P_STOP_MEM_CFG	S5P_CLKREG(0xC034)
#define S5P_SLEEP_CFG		S5P_CLKREG(0xC040)

#define S5P_OSC_FREQ		S5P_CLKREG(0xC100)
#define S5P_OSC_STABLE		S5P_CLKREG(0xC104)
#define S5P_PWR_STABLE		S5P_CLKREG(0xC108)
#define S5P_MTC_STABLE		S5P_CLKREG(0xC110)
#define S5P_CLAMP_STABLE	S5P_CLKREG(0xC114)

#define S5P_WAKEUP_STAT		S5P_CLKREG(0xC200)
#define S5P_BLK_PWR_STAT	S5P_CLKREG(0xC204)

#define S5P_OTHERS		S5P_CLKREG(0xE000)
#define S5P_OM_STAT		S5P_CLKREG(0xE100)
#define S5P_USB_PHY_CONTROL	S5P_CLKREG(0xE80C)
#define S5P_DAC_CONTROL		S5P_CLKREG(0xE810)

#define S5P_INFORM0		S5P_CLKREG(0xF000)
#define S5P_INFORM1		S5P_CLKREG(0xF004)
#define S5P_INFORM2		S5P_CLKREG(0xF008)
#define S5P_INFORM3		S5P_CLKREG(0xF00C)
#define S5P_INFORM4		S5P_CLKREG(0xF010)
#define S5P_INFORM5		S5P_CLKREG(0xF014)
#define S5P_INFORM6		S5P_CLKREG(0xF018)
#define S5P_INFORM7		S5P_CLKREG(0xF01C)

#define S5P_RST_STAT		S5P_CLKREG(0xA000)
#define S5P_OSC_CON		S5P_CLKREG(0x8000)
#define S5P_MDNIE_SEL		S5P_CLKREG(0x7008)
#define S5P_MIPI_PHY_CON0	S5P_CLKREG(0x7200)
#define S5P_MIPI_PHY_CON1	S5P_CLKREG(0x7204)
#define S5P_MIPI_CONTROL	S5P_CLKREG(0xE814)

#define S5P_IDLE_CFG_TL_MASK	(3 << 30)
#define S5P_IDLE_CFG_TM_MASK	(3 << 28)
#define S5P_IDLE_CFG_TL_ON	(2 << 30)
#define S5P_IDLE_CFG_TM_ON	(2 << 28)
#define S5P_IDLE_CFG_DIDLE	(1 << 0)

#define S5P_CFG_WFI_CLEAN		(~(3 << 8))
#define S5P_CFG_WFI_IDLE		(1 << 8)
#define S5P_CFG_WFI_STOP		(2 << 8)
#define S5P_CFG_WFI_SLEEP		(3 << 8)

#define S5P_OTHER_SYS_INT		24
#define S5P_OTHER_STA_TYPE		23
#define S5P_OTHER_SYSC_INTOFF		(1 << 0)
#define STA_TYPE_EXPON			0
#define STA_TYPE_SFR			1

#define S5P_PWR_STA_EXP_SCALE		0
#define S5P_PWR_STA_CNT			4

#define S5P_PWR_STABLE_COUNT		85500

#define S5P_SLEEP_CFG_OSC_EN		(1 << 0)
#define S5P_SLEEP_CFG_USBOSC_EN		(1 << 1)

/* OTHERS Resgister */
#define S5P_OTHERS_USB_SIG_MASK		(1 << 16)
#define S5P_OTHERS_MIPI_DPHY_EN		(1 << 28)

/* MIPI */
#define S5P_MIPI_DPHY_EN		(3)

/* S5P_DAC_CONTROL */
#define S5P_DAC_ENABLE			(1)
#define S5P_DAC_DISABLE			(0)

#endif /* __ASM_ARCH_REGS_CLOCK_H */
Commit	Line	Data
0c1945d3 KK	1	/* linux/arch/arm/mach-s5pv210/include/mach/regs-clock.h
	2	*
	3	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com/
	5	*
	6	* S5PV210 - Clock register definitions
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __ASM_ARCH_REGS_CLOCK_H
	14	#define __ASM_ARCH_REGS_CLOCK_H __FILE__
	15
	16	#include <mach/map.h>
	17
	18	#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
	19
	20	#define S5P_APLL_LOCK S5P_CLKREG(0x00)
	21	#define S5P_MPLL_LOCK S5P_CLKREG(0x08)
	22	#define S5P_EPLL_LOCK S5P_CLKREG(0x10)
	23	#define S5P_VPLL_LOCK S5P_CLKREG(0x20)
	24
	25	#define S5P_APLL_CON S5P_CLKREG(0x100)
	26	#define S5P_MPLL_CON S5P_CLKREG(0x108)
	27	#define S5P_EPLL_CON S5P_CLKREG(0x110)
	28	#define S5P_VPLL_CON S5P_CLKREG(0x120)
	29
	30	#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
	31	#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
	32	#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
	33	#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
	34	#define S5P_CLK_SRC4 S5P_CLKREG(0x210)
	35	#define S5P_CLK_SRC5 S5P_CLKREG(0x214)
	36	#define S5P_CLK_SRC6 S5P_CLKREG(0x218)
	37
	38	#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280)
	39	#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284)
	40
	41	#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
	42	#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
	43	#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
	44	#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
	45	#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
	46	#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
	47	#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
	48	#define S5P_CLK_DIV7 S5P_CLKREG(0x31C)
	49
	50	#define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x400)
	51	#define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x404)
	52	#define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x408)
	53
	54	#define S5P_CLKGATE_PERI0 S5P_CLKREG(0x420)
	55	#define S5P_CLKGATE_PERI1 S5P_CLKREG(0x424)
	56
	57	#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x440)
	58	#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x444)
	59	#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
	60	#define S5P_CLKGATE_IP1 S5P_CLKREG(0x464)
	61	#define S5P_CLKGATE_IP2 S5P_CLKREG(0x468)
	62	#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
	63	#define S5P_CLKGATE_IP4 S5P_CLKREG(0x470)
	64
65	#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480)
66	#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484)
67	#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488)
68	#define S5P_CLK_OUT S5P_CLKREG(0x500)
69
70	/* CLKSRC0 */
71	#define S5P_CLKSRC0_MUX200_MASK (0x1<<16)
72	#define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
73	#define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
74
75	/* CLKDIV0 */
76	#define S5P_CLKDIV0_APLL_SHIFT (0)
77	#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
78	#define S5P_CLKDIV0_A2M_SHIFT (4)
79	#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
80	#define S5P_CLKDIV0_HCLK200_SHIFT (8)
81	#define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
82	#define S5P_CLKDIV0_PCLK100_SHIFT (12)
83	#define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
84	#define S5P_CLKDIV0_HCLK166_SHIFT (16)
85	#define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT)
86	#define S5P_CLKDIV0_PCLK83_SHIFT (20)
87	#define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
88	#define S5P_CLKDIV0_HCLK133_SHIFT (24)
89	#define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT)
90	#define S5P_CLKDIV0_PCLK66_SHIFT (28)
91	#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
92
4550ee20 JL	93	#define S5P_SWRESET S5P_CLKREG(0x2000)
4550ee20 JL	94
0c1945d3 KK	95	/* Registers related to power management */
	96	#define S5P_PWR_CFG S5P_CLKREG(0xC000)
	97	#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004)
	98	#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008)
	99	#define S5P_PWR_MODE S5P_CLKREG(0xC00C)
	100	#define S5P_NORMAL_CFG S5P_CLKREG(0xC010)
	101	#define S5P_IDLE_CFG S5P_CLKREG(0xC020)
	102	#define S5P_STOP_CFG S5P_CLKREG(0xC030)
	103	#define S5P_STOP_MEM_CFG S5P_CLKREG(0xC034)
	104	#define S5P_SLEEP_CFG S5P_CLKREG(0xC040)
	105
	106	#define S5P_OSC_FREQ S5P_CLKREG(0xC100)
	107	#define S5P_OSC_STABLE S5P_CLKREG(0xC104)
	108	#define S5P_PWR_STABLE S5P_CLKREG(0xC108)
	109	#define S5P_MTC_STABLE S5P_CLKREG(0xC110)
	110	#define S5P_CLAMP_STABLE S5P_CLKREG(0xC114)
	111
	112	#define S5P_WAKEUP_STAT S5P_CLKREG(0xC200)
	113	#define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204)
	114
	115	#define S5P_OTHERS S5P_CLKREG(0xE000)
	116	#define S5P_OM_STAT S5P_CLKREG(0xE100)
	117	#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C)
	118	#define S5P_DAC_CONTROL S5P_CLKREG(0xE810)
	119
	120	#define S5P_INFORM0 S5P_CLKREG(0xF000)
	121	#define S5P_INFORM1 S5P_CLKREG(0xF004)
	122	#define S5P_INFORM2 S5P_CLKREG(0xF008)
	123	#define S5P_INFORM3 S5P_CLKREG(0xF00C)
	124	#define S5P_INFORM4 S5P_CLKREG(0xF010)
	125	#define S5P_INFORM5 S5P_CLKREG(0xF014)
	126	#define S5P_INFORM6 S5P_CLKREG(0xF018)
	127	#define S5P_INFORM7 S5P_CLKREG(0xF01C)
	128
	129	#define S5P_RST_STAT S5P_CLKREG(0xA000)
	130	#define S5P_OSC_CON S5P_CLKREG(0x8000)
5b696a67	131	#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
0c1945d3 KK	132	#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200)
	133	#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204)
	134	#define S5P_MIPI_CONTROL S5P_CLKREG(0xE814)
	135
	136	#define S5P_IDLE_CFG_TL_MASK (3 << 30)
	137	#define S5P_IDLE_CFG_TM_MASK (3 << 28)
	138	#define S5P_IDLE_CFG_TL_ON (2 << 30)
	139	#define S5P_IDLE_CFG_TM_ON (2 << 28)
	140	#define S5P_IDLE_CFG_DIDLE (1 << 0)
	141
	142	#define S5P_CFG_WFI_CLEAN (~(3 << 8))
	143	#define S5P_CFG_WFI_IDLE (1 << 8)
	144	#define S5P_CFG_WFI_STOP (2 << 8)
	145	#define S5P_CFG_WFI_SLEEP (3 << 8)
	146
	147	#define S5P_OTHER_SYS_INT 24
	148	#define S5P_OTHER_STA_TYPE 23
	149	#define S5P_OTHER_SYSC_INTOFF (1 << 0)
	150	#define STA_TYPE_EXPON 0
	151	#define STA_TYPE_SFR 1
	152
	153	#define S5P_PWR_STA_EXP_SCALE 0
	154	#define S5P_PWR_STA_CNT 4
	155
	156	#define S5P_PWR_STABLE_COUNT 85500
	157
	158	#define S5P_SLEEP_CFG_OSC_EN (1 << 0)
	159	#define S5P_SLEEP_CFG_USBOSC_EN (1 << 1)
	160
	161	/* OTHERS Resgister */
	162	#define S5P_OTHERS_USB_SIG_MASK (1 << 16)
	163	#define S5P_OTHERS_MIPI_DPHY_EN (1 << 28)
	164
	165	/* MIPI */
	166	#define S5P_MIPI_DPHY_EN (3)
	167
	168	/* S5P_DAC_CONTROL */
	169	#define S5P_DAC_ENABLE (1)
	170	#define S5P_DAC_DISABLE (0)
	171
	172	#endif /* __ASM_ARCH_REGS_CLOCK_H */