[net-next-2.6.git] / arch / arm / mach-s3c2440 / s3c244x.c

/* linux/arch/arm/plat-s3c24xx/s3c244x.c
 *
 * Copyright (c) 2004-2006 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#include <plat/cpu-freq.h>

#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-gpioj.h>
#include <mach/regs-dsc.h>

#include <plat/s3c2410.h>
#include <plat/s3c244x.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/nand-core.h>

static struct map_desc s3c244x_iodesc[] __initdata = {
	IODESC_ENT(CLKPWR),
	IODESC_ENT(TIMER),
	IODESC_ENT(WATCHDOG),
};

/* uart initialisation */

void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
}

void __init s3c244x_map_io(void)
{
	/* register our io-tables */

	iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));

	/* rename any peripherals used differing from the s3c2410 */

	s3c_device_sdi.name  = "s3c2440-sdi";
	s3c_device_i2c0.name  = "s3c2440-i2c";
	s3c_nand_setname("s3c2440-nand");
	s3c_device_ts.name = "s3c2440-ts";
	s3c_device_usbgadget.name = "s3c2440-usbgadget";
}

void __init_or_cpufreq s3c244x_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long clkdiv;
	unsigned long camdiv;
	unsigned long xtal;
	unsigned long hclk, fclk, pclk;
	int hdiv = 1;

	xtal_clk = clk_get(NULL, "xtal");
	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;

	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	camdiv = __raw_readl(S3C2440_CAMDIVN);

	/* work out clock scalings */

	switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
	case S3C2440_CLKDIVN_HDIVN_1:
		hdiv = 1;
		break;

	case S3C2440_CLKDIVN_HDIVN_2:
		hdiv = 2;
		break;

	case S3C2440_CLKDIVN_HDIVN_4_8:
		hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
		break;

	case S3C2440_CLKDIVN_HDIVN_3_6:
		hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
		break;
	}

	hclk = fclk / hdiv;
	pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);

	/* print brief summary of clocks, etc */

	printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	       print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));

	s3c24xx_setup_clocks(fclk, hclk, pclk);
}

void __init s3c244x_init_clocks(int xtal)
{
	/* initialise the clocks here, to allow other things like the
	 * console to use them, and to add new ones after the initialisation
	 */

	s3c24xx_register_baseclocks(xtal);
	s3c244x_setup_clocks();
	s3c2410_baseclk_add();
}

#ifdef CONFIG_PM

static struct sleep_save s3c244x_sleep[] = {
	SAVE_ITEM(S3C2440_DSC0),
	SAVE_ITEM(S3C2440_DSC1),
	SAVE_ITEM(S3C2440_GPJDAT),
	SAVE_ITEM(S3C2440_GPJCON),
	SAVE_ITEM(S3C2440_GPJUP)
};

static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
{
	s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
	return 0;
}

static int s3c244x_resume(struct sys_device *dev)
{
	s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
	return 0;
}

#else
#define s3c244x_suspend NULL
#define s3c244x_resume  NULL
#endif

/* Since the S3C2442 and S3C2440 share  items, put both sysclasses here */

struct sysdev_class s3c2440_sysclass = {
	.name		= "s3c2440-core",
	.suspend	= s3c244x_suspend,
	.resume		= s3c244x_resume
};

struct sysdev_class s3c2442_sysclass = {
	.name		= "s3c2442-core",
	.suspend	= s3c244x_suspend,
	.resume		= s3c244x_resume
};

/* need to register class before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2440 based system)
 * as a driver which may support both 2410 and 2440 may try and use it.
*/

static int __init s3c2440_core_init(void)
{
	return sysdev_class_register(&s3c2440_sysclass);
}

core_initcall(s3c2440_core_init);

static int __init s3c2442_core_init(void)
{
	return sysdev_class_register(&s3c2442_sysclass);
}

core_initcall(s3c2442_core_init);
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/plat-s3c24xx/s3c244x.c
96ce2385 BD	2	*
	3	* Copyright (c) 2004-2006 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
e4d06e39	6	* Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
96ce2385 BD	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
b6d1f542	19	#include <linux/serial_core.h>
96ce2385 BD	20	#include <linux/platform_device.h>
	21	#include <linux/sysdev.h>
	22	#include <linux/clk.h>
fced80c7	23	#include <linux/io.h>
96ce2385 BD	24
	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/map.h>
	27	#include <asm/mach/irq.h>
	28
a09e64fb	29	#include <mach/hardware.h>
96ce2385 BD	30	#include <asm/irq.h>
96ce2385 BD	31
e425382e BD	32	#include <plat/cpu-freq.h>
e425382e BD	33
a09e64fb	34	#include <mach/regs-clock.h>
a2b7ba9c	35	#include <plat/regs-serial.h>
a09e64fb RK	36	#include <mach/regs-gpio.h>
	37	#include <mach/regs-gpioj.h>
	38	#include <mach/regs-dsc.h>
96ce2385	39
a2b7ba9c	40	#include <plat/s3c2410.h>
58bac7b8	41	#include <plat/s3c244x.h>
d5120ae7	42	#include <plat/clock.h>
a2b7ba9c BD	43	#include <plat/devs.h>
	44	#include <plat/cpu.h>
	45	#include <plat/pm.h>
e24b864a	46	#include <plat/pll.h>
ef3f2dd4	47	#include <plat/nand-core.h>
96ce2385 BD	48
	49	static struct map_desc s3c244x_iodesc[] __initdata = {
	50	IODESC_ENT(CLKPWR),
	51	IODESC_ENT(TIMER),
	52	IODESC_ENT(WATCHDOG),
96ce2385 BD	53	};
	54
	55	/* uart initialisation */
	56
	57	void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
	58	{
	59	s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
	60	}
	61
74b265d4	62	void __init s3c244x_map_io(void)
96ce2385 BD	63	{
	64	/* register our io-tables */
	65
	66	iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
96ce2385 BD	67
	68	/* rename any peripherals used differing from the s3c2410 */
	69
90239bbd	70	s3c_device_sdi.name = "s3c2440-sdi";
3e1b776c	71	s3c_device_i2c0.name = "s3c2440-i2c";
ef3f2dd4	72	s3c_nand_setname("s3c2440-nand");
ce8877b5	73	s3c_device_ts.name = "s3c2440-ts";
b8ccca4a	74	s3c_device_usbgadget.name = "s3c2440-usbgadget";
96ce2385 BD	75	}
96ce2385 BD	76
e425382e	77	void __init_or_cpufreq s3c244x_setup_clocks(void)
96ce2385	78	{
e425382e	79	struct clk *xtal_clk;
96ce2385 BD	80	unsigned long clkdiv;
96ce2385 BD	81	unsigned long camdiv;
e425382e	82	unsigned long xtal;
96ce2385 BD	83	unsigned long hclk, fclk, pclk;
	84	int hdiv = 1;
	85
e425382e BD	86	xtal_clk = clk_get(NULL, "xtal");
	87	xtal = clk_get_rate(xtal_clk);
	88	clk_put(xtal_clk);
96ce2385	89
e24b864a	90	fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
96ce2385 BD	91
	92	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	93	camdiv = __raw_readl(S3C2440_CAMDIVN);
	94
	95	/* work out clock scalings */
	96
	97	switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
	98	case S3C2440_CLKDIVN_HDIVN_1:
	99	hdiv = 1;
	100	break;
	101
	102	case S3C2440_CLKDIVN_HDIVN_2:
	103	hdiv = 2;
	104	break;
	105
	106	case S3C2440_CLKDIVN_HDIVN_4_8:
	107	hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
	108	break;
	109
	110	case S3C2440_CLKDIVN_HDIVN_3_6:
	111	hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
	112	break;
	113	}
	114
	115	hclk = fclk / hdiv;
e425382e	116	pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
96ce2385 BD	117
	118	/* print brief summary of clocks, etc */
	119
	120	printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
	121	print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
	122
e425382e BD	123	s3c24xx_setup_clocks(fclk, hclk, pclk);
	124	}
	125
	126	void __init s3c244x_init_clocks(int xtal)
	127	{
96ce2385 BD	128	/* initialise the clocks here, to allow other things like the
	129	* console to use them, and to add new ones after the initialisation
	130	*/
	131
e425382e BD	132	s3c24xx_register_baseclocks(xtal);
e425382e BD	133	s3c244x_setup_clocks();
99c13853	134	s3c2410_baseclk_add();
96ce2385 BD	135	}
	136
	137	#ifdef CONFIG_PM
	138
	139	static struct sleep_save s3c244x_sleep[] = {
	140	SAVE_ITEM(S3C2440_DSC0),
	141	SAVE_ITEM(S3C2440_DSC1),
	142	SAVE_ITEM(S3C2440_GPJDAT),
	143	SAVE_ITEM(S3C2440_GPJCON),
	144	SAVE_ITEM(S3C2440_GPJUP)
	145	};
	146
	147	static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
	148	{
6419711a	149	s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
96ce2385 BD	150	return 0;
	151	}
	152
	153	static int s3c244x_resume(struct sys_device *dev)
	154	{
6419711a	155	s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
96ce2385 BD	156	return 0;
	157	}
	158
	159	#else
	160	#define s3c244x_suspend NULL
	161	#define s3c244x_resume NULL
	162	#endif
	163
	164	/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
	165
	166	struct sysdev_class s3c2440_sysclass = {
af5ca3f4	167	.name = "s3c2440-core",
96ce2385 BD	168	.suspend = s3c244x_suspend,
	169	.resume = s3c244x_resume
	170	};
	171
	172	struct sysdev_class s3c2442_sysclass = {
af5ca3f4	173	.name = "s3c2442-core",
96ce2385 BD	174	.suspend = s3c244x_suspend,
	175	.resume = s3c244x_resume
	176	};
	177
	178	/* need to register class before we actually register the device, and
	179	* we also need to ensure that it has been initialised before any of the
	180	* drivers even try to use it (even if not on an s3c2440 based system)
	181	* as a driver which may support both 2410 and 2440 may try and use it.
	182	*/
	183
	184	static int __init s3c2440_core_init(void)
	185	{
	186	return sysdev_class_register(&s3c2440_sysclass);
	187	}
	188
	189	core_initcall(s3c2440_core_init);
	190
	191	static int __init s3c2442_core_init(void)
	192	{
	193	return sysdev_class_register(&s3c2442_sysclass);
	194	}
	195
	196	core_initcall(s3c2442_core_init);