[net-next-2.6.git] / arch / arm / mach-realview / realview_eb.c

/*
 *  linux/arch/arm/mach-realview/realview_eb.c
 *
 *  Copyright (C) 2004 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/amba/bus.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/icst307.h>
#include <asm/hardware/cache-l2x0.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/mmc.h>
#include <asm/mach/time.h>

#include <asm/arch/board-eb.h>
#include <asm/arch/irqs.h>

#include "core.h"
#include "clock.h"

static struct map_desc realview_eb_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(REALVIEW_SYS_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_SYS_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_SCTL_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_SCTL_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
#ifdef CONFIG_DEBUG_LL
	{
		.virtual	= IO_ADDRESS(REALVIEW_EB_UART0_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_EB_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}
#endif
};

static struct map_desc realview_eb11mp_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	}
};

static void __init realview_eb_map_io(void)
{
	iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
	if (core_tile_eb11mp())
		iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
}

/*
 * RealView EB AMBA devices
 */

/*
 * These devices are connected via the core APB bridge
 */
#define GPIO2_IRQ	{ IRQ_EB_GPIO2, NO_IRQ }
#define GPIO2_DMA	{ 0, 0 }
#define GPIO3_IRQ	{ IRQ_EB_GPIO3, NO_IRQ }
#define GPIO3_DMA	{ 0, 0 }

#define AACI_IRQ	{ IRQ_EB_AACI, NO_IRQ }
#define AACI_DMA	{ 0x80, 0x81 }
#define MMCI0_IRQ	{ IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
#define MMCI0_DMA	{ 0x84, 0 }
#define KMI0_IRQ	{ IRQ_EB_KMI0, NO_IRQ }
#define KMI0_DMA	{ 0, 0 }
#define KMI1_IRQ	{ IRQ_EB_KMI1, NO_IRQ }
#define KMI1_DMA	{ 0, 0 }

/*
 * These devices are connected directly to the multi-layer AHB switch
 */
#define SMC_IRQ		{ NO_IRQ, NO_IRQ }
#define SMC_DMA		{ 0, 0 }
#define MPMC_IRQ	{ NO_IRQ, NO_IRQ }
#define MPMC_DMA	{ 0, 0 }
#define CLCD_IRQ	{ IRQ_EB_CLCD, NO_IRQ }
#define CLCD_DMA	{ 0, 0 }
#define DMAC_IRQ	{ IRQ_EB_DMA, NO_IRQ }
#define DMAC_DMA	{ 0, 0 }

/*
 * These devices are connected via the core APB bridge
 */
#define SCTL_IRQ	{ NO_IRQ, NO_IRQ }
#define SCTL_DMA	{ 0, 0 }
#define WATCHDOG_IRQ	{ IRQ_EB_WDOG, NO_IRQ }
#define WATCHDOG_DMA	{ 0, 0 }
#define GPIO0_IRQ	{ IRQ_EB_GPIO0, NO_IRQ }
#define GPIO0_DMA	{ 0, 0 }
#define GPIO1_IRQ	{ IRQ_EB_GPIO1, NO_IRQ }
#define GPIO1_DMA	{ 0, 0 }
#define RTC_IRQ		{ IRQ_EB_RTC, NO_IRQ }
#define RTC_DMA		{ 0, 0 }

/*
 * These devices are connected via the DMA APB bridge
 */
#define SCI_IRQ		{ IRQ_EB_SCI, NO_IRQ }
#define SCI_DMA		{ 7, 6 }
#define EB_UART0_IRQ	{ IRQ_EB_UART0, NO_IRQ }
#define EB_UART0_DMA	{ 15, 14 }
#define EB_UART1_IRQ	{ IRQ_EB_UART1, NO_IRQ }
#define EB_UART1_DMA	{ 13, 12 }
#define EB_UART2_IRQ	{ IRQ_EB_UART2, NO_IRQ }
#define EB_UART2_DMA	{ 11, 10 }
#define EB_UART3_IRQ	{ IRQ_EB_UART3, NO_IRQ }
#define EB_UART3_DMA	{ 0x86, 0x87 }
#define SSP_IRQ		{ IRQ_EB_SSP, NO_IRQ }
#define SSP_DMA		{ 9, 8 }

/* FPGA Primecells */
AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &realview_mmc0_plat_data);
AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL);

/* DevChip Primecells */
AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
AMBA_DEVICE(uart0, "dev:f1",  EB_UART0, NULL);
AMBA_DEVICE(uart1, "dev:f2",  EB_UART1, NULL);
AMBA_DEVICE(uart2, "dev:f3",  EB_UART2, NULL);
AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);

static struct amba_device *amba_devs[] __initdata = {
	&dmac_device,
	&uart0_device,
	&uart1_device,
	&uart2_device,
	&uart3_device,
	&smc_device,
	&clcd_device,
	&sctl_device,
	&wdog_device,
	&gpio0_device,
	&gpio1_device,
	&gpio2_device,
	&rtc_device,
	&sci0_device,
	&ssp0_device,
	&aaci_device,
	&mmc0_device,
	&kmi0_device,
	&kmi1_device,
};

/*
 * RealView EB platform devices
 */
static struct resource realview_eb_flash_resource = {
	.start			= REALVIEW_EB_FLASH_BASE,
	.end			= REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
	.flags			= IORESOURCE_MEM,
};

static struct resource realview_eb_eth_resources[] = {
	[0] = {
		.start		= REALVIEW_ETH_BASE,
		.end		= REALVIEW_ETH_BASE + SZ_64K - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= IRQ_EB_ETH,
		.end		= IRQ_EB_ETH,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device realview_eb_eth_device = {
	.id		= 0,
	.num_resources	= ARRAY_SIZE(realview_eb_eth_resources),
	.resource	= realview_eb_eth_resources,
};

/*
 * Detect and register the correct Ethernet device. RealView/EB rev D
 * platforms use the newer SMSC LAN9118 Ethernet chip
 */
static int eth_device_register(void)
{
	void __iomem *eth_addr = ioremap(REALVIEW_ETH_BASE, SZ_4K);
	u32 idrev;

	if (!eth_addr)
		return -ENOMEM;

	idrev = readl(eth_addr + 0x50);
	if ((idrev & 0xFFFF0000) == 0x01180000)
		/* SMSC LAN9118 chip present */
		realview_eb_eth_device.name = "smc911x";
	else
		/* SMSC 91C111 chip present */
		realview_eb_eth_device.name = "smc91x";

	iounmap(eth_addr);
	return platform_device_register(&realview_eb_eth_device);
}

static void __init gic_init_irq(void)
{
	if (core_tile_eb11mp()) {
		unsigned int pldctrl;

		/* new irq mode */
		writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
		pldctrl = readl(__io_address(REALVIEW_SYS_BASE)	+ REALVIEW_EB11MP_SYS_PLD_CTRL1);
		pldctrl |= 0x00800000;
		writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
		writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));

		/* core tile GIC, primary */
		gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
		gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
		gic_cpu_init(0, gic_cpu_base_addr);

#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
		/* board GIC, secondary */
		gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
		gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
		gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
#endif
	} else {
		/* board GIC, primary */
		gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
		gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
		gic_cpu_init(0, gic_cpu_base_addr);
	}
}

/*
 * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
 */
static void realview_eb11mp_fixup(void)
{
	/* AMBA devices */
	dmac_device.irq[0]	= IRQ_EB11MP_DMA;
	uart0_device.irq[0]	= IRQ_EB11MP_UART0;
	uart1_device.irq[0]	= IRQ_EB11MP_UART1;
	uart2_device.irq[0]	= IRQ_EB11MP_UART2;
	uart3_device.irq[0]	= IRQ_EB11MP_UART3;
	clcd_device.irq[0]	= IRQ_EB11MP_CLCD;
	wdog_device.irq[0]	= IRQ_EB11MP_WDOG;
	gpio0_device.irq[0]	= IRQ_EB11MP_GPIO0;
	gpio1_device.irq[0]	= IRQ_EB11MP_GPIO1;
	gpio2_device.irq[0]	= IRQ_EB11MP_GPIO2;
	rtc_device.irq[0]	= IRQ_EB11MP_RTC;
	sci0_device.irq[0]	= IRQ_EB11MP_SCI;
	ssp0_device.irq[0]	= IRQ_EB11MP_SSP;
	aaci_device.irq[0]	= IRQ_EB11MP_AACI;
	mmc0_device.irq[0]	= IRQ_EB11MP_MMCI0A;
	mmc0_device.irq[1]	= IRQ_EB11MP_MMCI0B;
	kmi0_device.irq[0]	= IRQ_EB11MP_KMI0;
	kmi1_device.irq[0]	= IRQ_EB11MP_KMI1;

	/* platform devices */
	realview_eb_eth_resources[1].start	= IRQ_EB11MP_ETH;
	realview_eb_eth_resources[1].end	= IRQ_EB11MP_ETH;
}

static void __init realview_eb_timer_init(void)
{
	unsigned int timer_irq;

	timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
	timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
	timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
	timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;

	if (core_tile_eb11mp()) {
#ifdef CONFIG_LOCAL_TIMERS
		twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
		twd_size = REALVIEW_EB11MP_TWD_SIZE;
#endif
		timer_irq = IRQ_EB11MP_TIMER0_1;
	} else
		timer_irq = IRQ_EB_TIMER0_1;

	realview_timer_init(timer_irq);
}

static struct sys_timer realview_eb_timer = {
	.init		= realview_eb_timer_init,
};

static void __init realview_eb_init(void)
{
	int i;

	if (core_tile_eb11mp()) {
		realview_eb11mp_fixup();

		/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
		 * Bits:  .... ...0 0111 1001 0000 .... .... .... */
		l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
	}

	clk_register(&realview_clcd_clk);

	realview_flash_register(&realview_eb_flash_resource, 1);
	platform_device_register(&realview_i2c_device);
	eth_device_register();

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}

#ifdef CONFIG_LEDS
	leds_event = realview_leds_event;
#endif
}

MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.phys_io	= REALVIEW_EB_UART0_BASE,
	.io_pg_offst	= (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
	.boot_params	= 0x00000100,
	.map_io		= realview_eb_map_io,
	.init_irq	= gic_init_irq,
	.timer		= &realview_eb_timer,
	.init_machine	= realview_eb_init,
MACHINE_END
Commit	Line	Data
8ad68bbf CM	1	/*
	2	* linux/arch/arm/mach-realview/realview_eb.c
	3	*
	4	* Copyright (C) 2004 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
8ad68bbf	22	#include <linux/init.h>
1be7228d	23	#include <linux/platform_device.h>
8ad68bbf	24	#include <linux/sysdev.h>
a62c80e5	25	#include <linux/amba/bus.h>
8ad68bbf CM	26
	27	#include <asm/hardware.h>
	28	#include <asm/io.h>
	29	#include <asm/irq.h>
	30	#include <asm/leds.h>
	31	#include <asm/mach-types.h>
	32	#include <asm/hardware/gic.h>
8ad68bbf	33	#include <asm/hardware/icst307.h>
7770bddb	34	#include <asm/hardware/cache-l2x0.h>
8ad68bbf CM	35
	36	#include <asm/mach/arch.h>
	37	#include <asm/mach/map.h>
	38	#include <asm/mach/mmc.h>
8cc4c548	39	#include <asm/mach/time.h>
8ad68bbf	40
356cb470	41	#include <asm/arch/board-eb.h>
8ad68bbf CM	42	#include <asm/arch/irqs.h>
	43
	44	#include "core.h"
	45	#include "clock.h"
	46
	47	static struct map_desc realview_eb_io_desc[] __initdata = {
1ffedce7 RK	48	{
	49	.virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
	50	.pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
	51	.length = SZ_4K,
	52	.type = MT_DEVICE,
	53	}, {
073b6ff3 CM	54	.virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
073b6ff3 CM	55	.pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
1ffedce7 RK	56	.length = SZ_4K,
	57	.type = MT_DEVICE,
	58	}, {
073b6ff3 CM	59	.virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
073b6ff3 CM	60	.pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
1ffedce7 RK	61	.length = SZ_4K,
	62	.type = MT_DEVICE,
	63	}, {
	64	.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
	65	.pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
	66	.length = SZ_4K,
	67	.type = MT_DEVICE,
	68	}, {
80192735 CM	69	.virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
80192735 CM	70	.pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
1ffedce7 RK	71	.length = SZ_4K,
	72	.type = MT_DEVICE,
	73	}, {
80192735 CM	74	.virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
80192735 CM	75	.pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
1ffedce7 RK	76	.length = SZ_4K,
	77	.type = MT_DEVICE,
	78	},
8ad68bbf	79	#ifdef CONFIG_DEBUG_LL
1ffedce7	80	{
9a386f06 CM	81	.virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
9a386f06 CM	82	.pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
1ffedce7 RK	83	.length = SZ_4K,
	84	.type = MT_DEVICE,
	85	}
8ad68bbf CM	86	#endif
	87	};
	88
7dd19e75 CM	89	static struct map_desc realview_eb11mp_io_desc[] __initdata = {
	90	{
	91	.virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
	92	.pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
	93	.length = SZ_4K,
	94	.type = MT_DEVICE,
	95	}, {
	96	.virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
	97	.pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
	98	.length = SZ_4K,
	99	.type = MT_DEVICE,
	100	}, {
	101	.virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
	102	.pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
	103	.length = SZ_8K,
	104	.type = MT_DEVICE,
	105	}
	106	};
	107
8ad68bbf CM	108	static void __init realview_eb_map_io(void)
	109	{
	110	iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
7dd19e75 CM	111	if (core_tile_eb11mp())
7dd19e75 CM	112	iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
8ad68bbf CM	113	}
8ad68bbf CM	114
0fc2a161 CM	115	/*
	116	* RealView EB AMBA devices
	117	*/
	118
	119	/*
	120	* These devices are connected via the core APB bridge
	121	*/
	122	#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ }
	123	#define GPIO2_DMA { 0, 0 }
	124	#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ }
	125	#define GPIO3_DMA { 0, 0 }
	126
	127	#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ }
	128	#define AACI_DMA { 0x80, 0x81 }
	129	#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
	130	#define MMCI0_DMA { 0x84, 0 }
	131	#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ }
	132	#define KMI0_DMA { 0, 0 }
	133	#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ }
	134	#define KMI1_DMA { 0, 0 }
	135
	136	/*
	137	* These devices are connected directly to the multi-layer AHB switch
	138	*/
	139	#define SMC_IRQ { NO_IRQ, NO_IRQ }
	140	#define SMC_DMA { 0, 0 }
	141	#define MPMC_IRQ { NO_IRQ, NO_IRQ }
	142	#define MPMC_DMA { 0, 0 }
	143	#define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
	144	#define CLCD_DMA { 0, 0 }
	145	#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
	146	#define DMAC_DMA { 0, 0 }
	147
	148	/*
	149	* These devices are connected via the core APB bridge
	150	*/
	151	#define SCTL_IRQ { NO_IRQ, NO_IRQ }
	152	#define SCTL_DMA { 0, 0 }
	153	#define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
	154	#define WATCHDOG_DMA { 0, 0 }
	155	#define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
	156	#define GPIO0_DMA { 0, 0 }
	157	#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
	158	#define GPIO1_DMA { 0, 0 }
	159	#define RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
	160	#define RTC_DMA { 0, 0 }
	161
	162	/*
	163	* These devices are connected via the DMA APB bridge
	164	*/
	165	#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
	166	#define SCI_DMA { 7, 6 }
9a386f06 CM	167	#define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
	168	#define EB_UART0_DMA { 15, 14 }
	169	#define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
	170	#define EB_UART1_DMA { 13, 12 }
	171	#define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
	172	#define EB_UART2_DMA { 11, 10 }
	173	#define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
	174	#define EB_UART3_DMA { 0x86, 0x87 }
0fc2a161 CM	175	#define SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
	176	#define SSP_DMA { 9, 8 }
	177
8ad68bbf CM	178	/* FPGA Primecells */
	179	AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
	180	AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
	181	AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
	182	AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
9a386f06	183	AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL);
8ad68bbf CM	184
	185	/* DevChip Primecells */
	186	AMBA_DEVICE(smc, "dev:00", SMC, NULL);
	187	AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
	188	AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
	189	AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
	190	AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
	191	AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
	192	AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
	193	AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL);
	194	AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
	195	AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
9a386f06 CM	196	AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL);
	197	AMBA_DEVICE(uart1, "dev:f2", EB_UART1, NULL);
	198	AMBA_DEVICE(uart2, "dev:f3", EB_UART2, NULL);
8ad68bbf CM	199	AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
	200
	201	static struct amba_device *amba_devs[] __initdata = {
	202	&dmac_device,
	203	&uart0_device,
	204	&uart1_device,
	205	&uart2_device,
	206	&uart3_device,
	207	&smc_device,
	208	&clcd_device,
	209	&sctl_device,
	210	&wdog_device,
	211	&gpio0_device,
	212	&gpio1_device,
	213	&gpio2_device,
	214	&rtc_device,
	215	&sci0_device,
	216	&ssp0_device,
	217	&aaci_device,
	218	&mmc0_device,
	219	&kmi0_device,
	220	&kmi1_device,
	221	};
	222
0fc2a161 CM	223	/*
	224	* RealView EB platform devices
	225	*/
a44ddfd5 CM	226	static struct resource realview_eb_flash_resource = {
	227	.start = REALVIEW_EB_FLASH_BASE,
	228	.end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
	229	.flags = IORESOURCE_MEM,
	230	};
0fc2a161	231
be4f3c86	232	static struct resource realview_eb_eth_resources[] = {
0fc2a161 CM	233	[0] = {
	234	.start = REALVIEW_ETH_BASE,
	235	.end = REALVIEW_ETH_BASE + SZ_64K - 1,
	236	.flags = IORESOURCE_MEM,
	237	},
	238	[1] = {
	239	.start = IRQ_EB_ETH,
	240	.end = IRQ_EB_ETH,
	241	.flags = IORESOURCE_IRQ,
	242	},
	243	};
	244
be4f3c86	245	static struct platform_device realview_eb_eth_device = {
0fc2a161	246	.id = 0,
be4f3c86 CM	247	.num_resources = ARRAY_SIZE(realview_eb_eth_resources),
be4f3c86 CM	248	.resource = realview_eb_eth_resources,
0fc2a161 CM	249	};
0fc2a161 CM	250
be4f3c86 CM	251	/*
	252	* Detect and register the correct Ethernet device. RealView/EB rev D
	253	* platforms use the newer SMSC LAN9118 Ethernet chip
	254	*/
	255	static int eth_device_register(void)
	256	{
	257	void __iomem *eth_addr = ioremap(REALVIEW_ETH_BASE, SZ_4K);
	258	u32 idrev;
	259
	260	if (!eth_addr)
	261	return -ENOMEM;
	262
	263	idrev = readl(eth_addr + 0x50);
	264	if ((idrev & 0xFFFF0000) == 0x01180000)
	265	/* SMSC LAN9118 chip present */
	266	realview_eb_eth_device.name = "smc911x";
	267	else
	268	/* SMSC 91C111 chip present */
	269	realview_eb_eth_device.name = "smc91x";
	270
	271	iounmap(eth_addr);
	272	return platform_device_register(&realview_eb_eth_device);
	273	}
	274
8ad68bbf CM	275	static void __init gic_init_irq(void)
8ad68bbf CM	276	{
7dd19e75 CM	277	if (core_tile_eb11mp()) {
	278	unsigned int pldctrl;
	279
	280	/* new irq mode */
	281	writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
	282	pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
	283	pldctrl \|= 0x00800000;
	284	writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
	285	writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
	286
	287	/* core tile GIC, primary */
c4057f52	288	gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
7dd19e75	289	gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
c4057f52	290	gic_cpu_init(0, gic_cpu_base_addr);
7dd19e75	291
41579f49	292	#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
7dd19e75	293	/* board GIC, secondary */
073b6ff3 CM	294	gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
073b6ff3 CM	295	gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
7dd19e75	296	gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
3edf22ab	297	#endif
7dd19e75 CM	298	} else {
7dd19e75 CM	299	/* board GIC, primary */
073b6ff3 CM	300	gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
073b6ff3 CM	301	gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
c4057f52	302	gic_cpu_init(0, gic_cpu_base_addr);
7dd19e75	303	}
8ad68bbf CM	304	}
8ad68bbf CM	305
0fc2a161 CM	306	/*
	307	* Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
	308	*/
	309	static void realview_eb11mp_fixup(void)
	310	{
	311	/* AMBA devices */
	312	dmac_device.irq[0] = IRQ_EB11MP_DMA;
	313	uart0_device.irq[0] = IRQ_EB11MP_UART0;
	314	uart1_device.irq[0] = IRQ_EB11MP_UART1;
	315	uart2_device.irq[0] = IRQ_EB11MP_UART2;
	316	uart3_device.irq[0] = IRQ_EB11MP_UART3;
	317	clcd_device.irq[0] = IRQ_EB11MP_CLCD;
	318	wdog_device.irq[0] = IRQ_EB11MP_WDOG;
	319	gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
	320	gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
	321	gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
	322	rtc_device.irq[0] = IRQ_EB11MP_RTC;
	323	sci0_device.irq[0] = IRQ_EB11MP_SCI;
	324	ssp0_device.irq[0] = IRQ_EB11MP_SSP;
	325	aaci_device.irq[0] = IRQ_EB11MP_AACI;
	326	mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
	327	mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
	328	kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
	329	kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
	330
	331	/* platform devices */
be4f3c86 CM	332	realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
be4f3c86 CM	333	realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
0fc2a161	334	}
0fc2a161	335
8cc4c548 CM	336	static void __init realview_eb_timer_init(void)
	337	{
	338	unsigned int timer_irq;
	339
80192735 CM	340	timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
	341	timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
	342	timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
	343	timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
	344
39e823e3 CM	345	if (core_tile_eb11mp()) {
	346	#ifdef CONFIG_LOCAL_TIMERS
	347	twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
	348	twd_size = REALVIEW_EB11MP_TWD_SIZE;
	349	#endif
8cc4c548	350	timer_irq = IRQ_EB11MP_TIMER0_1;
39e823e3	351	} else
8cc4c548 CM	352	timer_irq = IRQ_EB_TIMER0_1;
	353
	354	realview_timer_init(timer_irq);
	355	}
	356
	357	static struct sys_timer realview_eb_timer = {
	358	.init = realview_eb_timer_init,
	359	};
	360
8ad68bbf CM	361	static void __init realview_eb_init(void)
	362	{
	363	int i;
	364
7dd19e75 CM	365	if (core_tile_eb11mp()) {
	366	realview_eb11mp_fixup();
	367
	368	/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
	369	* Bits: .... ...0 0111 1001 0000 .... .... .... */
	370	l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
	371	}
0fc2a161	372
8ad68bbf CM	373	clk_register(&realview_clcd_clk);
8ad68bbf CM	374
a44ddfd5	375	realview_flash_register(&realview_eb_flash_resource, 1);
6b65cd74	376	platform_device_register(&realview_i2c_device);
be4f3c86	377	eth_device_register();
8ad68bbf CM	378
	379	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
	380	struct amba_device *d = amba_devs[i];
	381	amba_device_register(d, &iomem_resource);
	382	}
	383
	384	#ifdef CONFIG_LEDS
	385	leds_event = realview_leds_event;
	386	#endif
	387	}
	388
	389	MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
	390	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
9a386f06 CM	391	.phys_io = REALVIEW_EB_UART0_BASE,
9a386f06 CM	392	.io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
8ad68bbf CM	393	.boot_params = 0x00000100,
	394	.map_io = realview_eb_map_io,
	395	.init_irq = gic_init_irq,
8cc4c548	396	.timer = &realview_eb_timer,
8ad68bbf CM	397	.init_machine = realview_eb_init,
8ad68bbf CM	398	MACHINE_END