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Merge branch 'imx-for-2.6.35' of git://git.pengutronix.de/git/imx/linux-2.6
[net-next-2.6.git] / arch / arm / mach-realview / realview_eb.c
CommitLineData
8ad68bbf
CM		 1/*
2 * linux/arch/arm/mach-realview/realview_eb.c
3 *
4 * Copyright (C) 2004 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
8ad68bbf 22#include <linux/init.h>
1be7228d 23#include <linux/platform_device.h>
8ad68bbf 24#include <linux/sysdev.h>
a62c80e5 25#include <linux/amba/bus.h>
eb7fffa3 26#include <linux/amba/pl061.h>
6ef297f8 27#include <linux/amba/mmci.h>
fced80c7 28#include <linux/io.h>
8ad68bbf 29
a09e64fb 30#include <mach/hardware.h>
8ad68bbf
CM		 31#include <asm/irq.h>
32#include <asm/leds.h>
33#include <asm/mach-types.h>
f417cbad 34#include <asm/pmu.h>
cc9897df 35#include <asm/pgtable.h>
8ad68bbf 36#include <asm/hardware/gic.h>
7770bddb 37#include <asm/hardware/cache-l2x0.h>
f32f4ce2 38#include <asm/localtimer.h>
8ad68bbf
CM		 39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
8cc4c548 42#include <asm/mach/time.h>
8ad68bbf 43
a09e64fb
RK		 44#include <mach/board-eb.h>
45#include <mach/irqs.h>
8ad68bbf
CM		 46
47#include "core.h"
8ad68bbf
CM		 48
49static struct map_desc realview_eb_io_desc[] __initdata = {
1ffedce7
RK		 50 {
51 .virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
52 .pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
53 .length = SZ_4K,
54 .type = MT_DEVICE,
55 }, {
073b6ff3
CM		 56 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
57 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
1ffedce7
RK		 58 .length = SZ_4K,
59 .type = MT_DEVICE,
60 }, {
073b6ff3
CM		 61 .virtual = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
62 .pfn = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
1ffedce7
RK		 63 .length = SZ_4K,
64 .type = MT_DEVICE,
65 }, {
66 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
67 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
68 .length = SZ_4K,
69 .type = MT_DEVICE,
70 }, {
80192735
CM		 71 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
72 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
1ffedce7
RK		 73 .length = SZ_4K,
74 .type = MT_DEVICE,
75 }, {
80192735
CM		 76 .virtual = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
77 .pfn = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
1ffedce7
RK		 78 .length = SZ_4K,
79 .type = MT_DEVICE,
80 },
8ad68bbf 81#ifdef CONFIG_DEBUG_LL
1ffedce7 82 {
9a386f06
CM		 83 .virtual = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
84 .pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
1ffedce7
RK		 85 .length = SZ_4K,
86 .type = MT_DEVICE,
87 }
8ad68bbf
CM		 88#endif
89};
90
7dd19e75
CM		 91static struct map_desc realview_eb11mp_io_desc[] __initdata = {
92 {
93 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
94 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
95 .length = SZ_4K,
96 .type = MT_DEVICE,
97 }, {
98 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
99 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
100 .length = SZ_4K,
101 .type = MT_DEVICE,
102 }, {
103 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
104 .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
105 .length = SZ_8K,
106 .type = MT_DEVICE,
107 }
108};
109
8ad68bbf
CM		 110static void __init realview_eb_map_io(void)
111{
112 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
4c3ea371 113 if (core_tile_eb11mp() || core_tile_a9mp())
7dd19e75 114 iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
8ad68bbf
CM		 115}
116
eb7fffa3
RK		 117static struct pl061_platform_data gpio0_plat_data = {
118 .gpio_base = 0,
119 .irq_base = -1,
120};
121
122static struct pl061_platform_data gpio1_plat_data = {
123 .gpio_base = 8,
124 .irq_base = -1,
125};
126
127static struct pl061_platform_data gpio2_plat_data = {
128 .gpio_base = 16,
129 .irq_base = -1,
130};
131
0fc2a161
CM		 132/*
133 * RealView EB AMBA devices
134 */
135
136/*
137 * These devices are connected via the core APB bridge
138 */
139#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ }
140#define GPIO2_DMA { 0, 0 }
141#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ }
142#define GPIO3_DMA { 0, 0 }
143
144#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ }
145#define AACI_DMA { 0x80, 0x81 }
146#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
147#define MMCI0_DMA { 0x84, 0 }
148#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ }
149#define KMI0_DMA { 0, 0 }
150#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ }
151#define KMI1_DMA { 0, 0 }
152
153/*
154 * These devices are connected directly to the multi-layer AHB switch
155 */
393538e6
CM		 156#define EB_SMC_IRQ { NO_IRQ, NO_IRQ }
157#define EB_SMC_DMA { 0, 0 }
0fc2a161
CM		 158#define MPMC_IRQ { NO_IRQ, NO_IRQ }
159#define MPMC_DMA { 0, 0 }
393538e6
CM		 160#define EB_CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
161#define EB_CLCD_DMA { 0, 0 }
0fc2a161
CM		 162#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
163#define DMAC_DMA { 0, 0 }
164
165/*
166 * These devices are connected via the core APB bridge
167 */
168#define SCTL_IRQ { NO_IRQ, NO_IRQ }
169#define SCTL_DMA { 0, 0 }
393538e6
CM		 170#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
171#define EB_WATCHDOG_DMA { 0, 0 }
172#define EB_GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
173#define EB_GPIO0_DMA { 0, 0 }
0fc2a161
CM		 174#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
175#define GPIO1_DMA { 0, 0 }
393538e6
CM		 176#define EB_RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
177#define EB_RTC_DMA { 0, 0 }
0fc2a161
CM		 178
179/*
180 * These devices are connected via the DMA APB bridge
181 */
182#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
183#define SCI_DMA { 7, 6 }
9a386f06
CM		 184#define EB_UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
185#define EB_UART0_DMA { 15, 14 }
186#define EB_UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
187#define EB_UART1_DMA { 13, 12 }
188#define EB_UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
189#define EB_UART2_DMA { 11, 10 }
190#define EB_UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
191#define EB_UART3_DMA { 0x86, 0x87 }
393538e6
CM		 192#define EB_SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
193#define EB_SSP_DMA { 9, 8 }
0fc2a161 194
8ad68bbf 195/* FPGA Primecells */
4321532c
LW		 196AMBA_DEVICE(aaci, "fpga:aaci", AACI, NULL);
197AMBA_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
198AMBA_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
199AMBA_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
200AMBA_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
8ad68bbf
CM		 201
202/* DevChip Primecells */
4321532c
LW		 203AMBA_DEVICE(smc, "dev:smc", EB_SMC, NULL);
204AMBA_DEVICE(clcd, "dev:clcd", EB_CLCD, &clcd_plat_data);
205AMBA_DEVICE(dmac, "dev:dmac", DMAC, NULL);
206AMBA_DEVICE(sctl, "dev:sctl", SCTL, NULL);
207AMBA_DEVICE(wdog, "dev:wdog", EB_WATCHDOG, NULL);
208AMBA_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
209AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
210AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
211AMBA_DEVICE(rtc, "dev:rtc", EB_RTC, NULL);
212AMBA_DEVICE(sci0, "dev:sci0", SCI, NULL);
213AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
214AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
215AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
216AMBA_DEVICE(ssp0, "dev:ssp0", EB_SSP, NULL);
8ad68bbf
CM		 217
218static struct amba_device *amba_devs[] __initdata = {
219 &dmac_device,
220 &uart0_device,
221 &uart1_device,
222 &uart2_device,
223 &uart3_device,
224 &smc_device,
225 &clcd_device,
226 &sctl_device,
227 &wdog_device,
228 &gpio0_device,
229 &gpio1_device,
230 &gpio2_device,
231 &rtc_device,
232 &sci0_device,
233 &ssp0_device,
234 &aaci_device,
235 &mmc0_device,
236 &kmi0_device,
237 &kmi1_device,
238};
239
0fc2a161
CM		 240/*
241 * RealView EB platform devices
242 */
a44ddfd5
CM		 243static struct resource realview_eb_flash_resource = {
244 .start = REALVIEW_EB_FLASH_BASE,
245 .end = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
246 .flags = IORESOURCE_MEM,
247};
0fc2a161 248
be4f3c86 249static struct resource realview_eb_eth_resources[] = {
0fc2a161 250 [0] = {
393538e6
CM		 251 .start = REALVIEW_EB_ETH_BASE,
252 .end = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
0fc2a161
CM		 253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
256 .start = IRQ_EB_ETH,
257 .end = IRQ_EB_ETH,
258 .flags = IORESOURCE_IRQ,
259 },
260};
261
be4f3c86
CM		 262/*
263 * Detect and register the correct Ethernet device. RealView/EB rev D
264 * platforms use the newer SMSC LAN9118 Ethernet chip
265 */
266static int eth_device_register(void)
267{
393538e6 268 void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
0a381330 269 const char *name = NULL;
be4f3c86
CM		 270 u32 idrev;
271
272 if (!eth_addr)
273 return -ENOMEM;
274
275 idrev = readl(eth_addr + 0x50);
0a381330
CM		 276 if ((idrev & 0xFFFF0000) != 0x01180000)
277 /* SMSC LAN9118 not present, use LAN91C111 instead */
278 name = "smc91x";
be4f3c86
CM		 279
280 iounmap(eth_addr);
0a381330 281 return realview_eth_register(name, realview_eb_eth_resources);
be4f3c86
CM		 282}
283
7db21712
CM		 284static struct resource realview_eb_isp1761_resources[] = {
285 [0] = {
286 .start = REALVIEW_EB_USB_BASE,
287 .end = REALVIEW_EB_USB_BASE + SZ_128K - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = IRQ_EB_USB,
292 .end = IRQ_EB_USB,
293 .flags = IORESOURCE_IRQ,
294 },
295};
296
f417cbad
WD		 297static struct resource pmu_resources[] = {
298 [0] = {
299 .start = IRQ_EB11MP_PMU_CPU0,
300 .end = IRQ_EB11MP_PMU_CPU0,
301 .flags = IORESOURCE_IRQ,
302 },
303 [1] = {
304 .start = IRQ_EB11MP_PMU_CPU1,
305 .end = IRQ_EB11MP_PMU_CPU1,
306 .flags = IORESOURCE_IRQ,
307 },
308 [2] = {
309 .start = IRQ_EB11MP_PMU_CPU2,
310 .end = IRQ_EB11MP_PMU_CPU2,
311 .flags = IORESOURCE_IRQ,
312 },
313 [3] = {
314 .start = IRQ_EB11MP_PMU_CPU3,
315 .end = IRQ_EB11MP_PMU_CPU3,
316 .flags = IORESOURCE_IRQ,
317 },
318};
319
320static struct platform_device pmu_device = {
321 .name = "arm-pmu",
322 .id = ARM_PMU_DEVICE_CPU,
323 .num_resources = ARRAY_SIZE(pmu_resources),
324 .resource = pmu_resources,
325};
326
8ad68bbf
CM		 327static void __init gic_init_irq(void)
328{
4c3ea371 329 if (core_tile_eb11mp() || core_tile_a9mp()) {
7dd19e75
CM		 330 unsigned int pldctrl;
331
332 /* new irq mode */
333 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
334 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
335 pldctrl |= 0x00800000;
336 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
337 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
338
339 /* core tile GIC, primary */
c4057f52 340 gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
7dd19e75 341 gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
c4057f52 342 gic_cpu_init(0, gic_cpu_base_addr);
7dd19e75 343
41579f49 344#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
7dd19e75 345 /* board GIC, secondary */
073b6ff3
CM		 346 gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
347 gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
7dd19e75 348 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
3edf22ab 349#endif
7dd19e75
CM		 350 } else {
351 /* board GIC, primary */
073b6ff3
CM		 352 gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
353 gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
c4057f52 354 gic_cpu_init(0, gic_cpu_base_addr);
7dd19e75 355 }
8ad68bbf
CM		 356}
357
0fc2a161
CM		 358/*
359 * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
360 */
361static void realview_eb11mp_fixup(void)
362{
363 /* AMBA devices */
364 dmac_device.irq[0] = IRQ_EB11MP_DMA;
365 uart0_device.irq[0] = IRQ_EB11MP_UART0;
366 uart1_device.irq[0] = IRQ_EB11MP_UART1;
367 uart2_device.irq[0] = IRQ_EB11MP_UART2;
368 uart3_device.irq[0] = IRQ_EB11MP_UART3;
369 clcd_device.irq[0] = IRQ_EB11MP_CLCD;
370 wdog_device.irq[0] = IRQ_EB11MP_WDOG;
371 gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
372 gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
373 gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
374 rtc_device.irq[0] = IRQ_EB11MP_RTC;
375 sci0_device.irq[0] = IRQ_EB11MP_SCI;
376 ssp0_device.irq[0] = IRQ_EB11MP_SSP;
377 aaci_device.irq[0] = IRQ_EB11MP_AACI;
378 mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
379 mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
380 kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
381 kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
382
383 /* platform devices */
be4f3c86
CM		 384 realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH;
385 realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH;
7db21712
CM		 386 realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB;
387 realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB;
0fc2a161 388}
0fc2a161 389
8cc4c548
CM		 390static void __init realview_eb_timer_init(void)
391{
392 unsigned int timer_irq;
393
80192735
CM		 394 timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
395 timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
396 timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
397 timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
398
4c3ea371 399 if (core_tile_eb11mp() || core_tile_a9mp()) {
39e823e3 400#ifdef CONFIG_LOCAL_TIMERS
ebac6546 401 twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE);
39e823e3 402#endif
8cc4c548 403 timer_irq = IRQ_EB11MP_TIMER0_1;
39e823e3 404 } else
8cc4c548
CM		 405 timer_irq = IRQ_EB_TIMER0_1;
406
407 realview_timer_init(timer_irq);
408}
409
410static struct sys_timer realview_eb_timer = {
411 .init = realview_eb_timer_init,
412};
413
4c9f8be7
CT		 414static void realview_eb_reset(char mode)
415{
416 void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
417 void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
418
419 /*
420 * To reset, we hit the on-board reset register
421 * in the system FPGA
422 */
423 __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
424 if (core_tile_eb11mp())
425 __raw_writel(0x0008, reset_ctrl);
426}
427
8ad68bbf
CM		 428static void __init realview_eb_init(void)
429{
430 int i;
431
4c3ea371 432 if (core_tile_eb11mp() || core_tile_a9mp()) {
7dd19e75
CM		 433 realview_eb11mp_fixup();
434
ba927951 435#ifdef CONFIG_CACHE_L2X0
7dd19e75
CM		 436 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
437 * Bits: .... ...0 0111 1001 0000 .... .... .... */
438 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
ba927951 439#endif
f417cbad 440 platform_device_register(&pmu_device);
7dd19e75 441 }
0fc2a161 442
a44ddfd5 443 realview_flash_register(&realview_eb_flash_resource, 1);
6b65cd74 444 platform_device_register(&realview_i2c_device);
be4f3c86 445 eth_device_register();
7db21712 446 realview_usb_register(realview_eb_isp1761_resources);
8ad68bbf
CM		 447
448 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
449 struct amba_device *d = amba_devs[i];
450 amba_device_register(d, &iomem_resource);
451 }
452
453#ifdef CONFIG_LEDS
454 leds_event = realview_leds_event;
455#endif
4c9f8be7 456 realview_reset = realview_eb_reset;
8ad68bbf
CM		 457}
458
459MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
460 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
cc9897df 461 .phys_io = REALVIEW_EB_UART0_BASE & SECTION_MASK,
9a386f06 462 .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
70bb62f8 463 .boot_params = PHYS_OFFSET + 0x00000100,
5b39d154 464 .fixup = realview_fixup,
8ad68bbf
CM		 465 .map_io = realview_eb_map_io,
466 .init_irq = gic_init_irq,
8cc4c548 467 .timer = &realview_eb_timer,
8ad68bbf
CM		 468 .init_machine = realview_eb_init,
469MACHINE_END
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