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ARM: ICST: use Hz instead of kHz
[net-next-2.6.git] / arch / arm / mach-realview / core.c
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8ad68bbf
CM		 1/*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
8ad68bbf 21#include <linux/init.h>
1be7228d 22#include <linux/platform_device.h>
8ad68bbf
CM		 23#include <linux/dma-mapping.h>
24#include <linux/sysdev.h>
25#include <linux/interrupt.h>
a62c80e5
RK		 26#include <linux/amba/bus.h>
27#include <linux/amba/clcd.h>
85802afe 28#include <linux/clocksource.h>
ae30ceac 29#include <linux/clockchips.h>
fced80c7 30#include <linux/io.h>
c5142e84 31#include <linux/smsc911x.h>
6be62ba2 32#include <linux/ata_platform.h>
6ef297f8 33#include <linux/amba/mmci.h>
8ad68bbf 34
cf30fb4a 35#include <asm/clkdev.h>
8ad68bbf 36#include <asm/system.h>
a09e64fb 37#include <mach/hardware.h>
8ad68bbf
CM		 38#include <asm/irq.h>
39#include <asm/leds.h>
68c3d935 40#include <asm/mach-types.h>
8ad68bbf
CM		 41#include <asm/hardware/arm_timer.h>
42#include <asm/hardware/icst307.h>
43
44#include <asm/mach/arch.h>
45#include <asm/mach/flash.h>
46#include <asm/mach/irq.h>
8ad68bbf 47#include <asm/mach/map.h>
8ad68bbf
CM		 48
49#include <asm/hardware/gic.h>
50
ee8c9571
CM		 51#include <mach/platform.h>
52#include <mach/irqs.h>
53
8ad68bbf
CM		 54#include "core.h"
55#include "clock.h"
56
57#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
58
1bbdf637 59/* used by entry-macro.S and platsmp.c */
c4057f52
CM		 60void __iomem *gic_cpu_base_addr;
61
c97c5aa8
CM		 62#ifdef CONFIG_ZONE_DMA
63/*
64 * Adjust the zones if there are restrictions for DMA access.
65 */
66void __init realview_adjust_zones(int node, unsigned long *size,
67 unsigned long *hole)
68{
69 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
70
71 if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
72 return;
73
74 size[ZONE_NORMAL] = size[0] - dma_size;
75 size[ZONE_DMA] = dma_size;
76 hole[ZONE_NORMAL] = hole[0];
77 hole[ZONE_DMA] = 0;
78}
79#endif
80
8ad68bbf
CM		 81/*
82 * This is the RealView sched_clock implementation. This has
83 * a resolution of 41.7ns, and a maximum value of about 179s.
84 */
85unsigned long long sched_clock(void)
86{
87 unsigned long long v;
88
89 v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
90 do_div(v, 3);
91
92 return v;
93}
94
95
96#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
97
98static int realview_flash_init(void)
99{
100 u32 val;
101
102 val = __raw_readl(REALVIEW_FLASHCTRL);
103 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
104 __raw_writel(val, REALVIEW_FLASHCTRL);
105
106 return 0;
107}
108
109static void realview_flash_exit(void)
110{
111 u32 val;
112
113 val = __raw_readl(REALVIEW_FLASHCTRL);
114 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
115 __raw_writel(val, REALVIEW_FLASHCTRL);
116}
117
118static void realview_flash_set_vpp(int on)
119{
120 u32 val;
121
122 val = __raw_readl(REALVIEW_FLASHCTRL);
123 if (on)
124 val |= REALVIEW_FLASHPROG_FLVPPEN;
125 else
126 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
127 __raw_writel(val, REALVIEW_FLASHCTRL);
128}
129
130static struct flash_platform_data realview_flash_data = {
131 .map_name = "cfi_probe",
132 .width = 4,
133 .init = realview_flash_init,
134 .exit = realview_flash_exit,
135 .set_vpp = realview_flash_set_vpp,
136};
137
8ad68bbf
CM		 138struct platform_device realview_flash_device = {
139 .name = "armflash",
140 .id = 0,
141 .dev = {
142 .platform_data = &realview_flash_data,
143 },
8ad68bbf
CM		 144};
145
a44ddfd5
CM		 146int realview_flash_register(struct resource *res, u32 num)
147{
148 realview_flash_device.resource = res;
149 realview_flash_device.num_resources = num;
150 return platform_device_register(&realview_flash_device);
151}
152
c5142e84
SG		 153static struct smsc911x_platform_config smsc911x_config = {
154 .flags = SMSC911X_USE_32BIT,
155 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
156 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
157 .phy_interface = PHY_INTERFACE_MODE_MII,
0a5b2f6b
CM		 158};
159
0a381330 160static struct platform_device realview_eth_device = {
c5142e84 161 .name = "smsc911x",
0a381330
CM		 162 .id = 0,
163 .num_resources = 2,
164};
165
166int realview_eth_register(const char *name, struct resource *res)
167{
168 if (name)
169 realview_eth_device.name = name;
170 realview_eth_device.resource = res;
c5142e84
SG		 171 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
172 realview_eth_device.dev.platform_data = &smsc911x_config;
0a381330
CM		 173
174 return platform_device_register(&realview_eth_device);
7db21712
CM		 175}
176
177struct platform_device realview_usb_device = {
178 .name = "isp1760",
179 .num_resources = 2,
180};
181
182int realview_usb_register(struct resource *res)
183{
184 realview_usb_device.resource = res;
185 return platform_device_register(&realview_usb_device);
0a381330
CM		 186}
187
6be62ba2
CM		 188static struct pata_platform_info pata_platform_data = {
189 .ioport_shift = 1,
190};
191
192static struct resource pata_resources[] = {
193 [0] = {
194 .start = REALVIEW_CF_BASE,
195 .end = REALVIEW_CF_BASE + 0xff,
196 .flags = IORESOURCE_MEM,
197 },
198 [1] = {
199 .start = REALVIEW_CF_BASE + 0x100,
200 .end = REALVIEW_CF_BASE + SZ_4K - 1,
201 .flags = IORESOURCE_MEM,
202 },
203};
204
205struct platform_device realview_cf_device = {
206 .name = "pata_platform",
207 .id = -1,
208 .num_resources = ARRAY_SIZE(pata_resources),
209 .resource = pata_resources,
210 .dev = {
211 .platform_data = &pata_platform_data,
212 },
213};
214
6b65cd74
RK		 215static struct resource realview_i2c_resource = {
216 .start = REALVIEW_I2C_BASE,
217 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
218 .flags = IORESOURCE_MEM,
219};
220
221struct platform_device realview_i2c_device = {
222 .name = "versatile-i2c",
533ad5e6 223 .id = 0,
6b65cd74
RK		 224 .num_resources = 1,
225 .resource = &realview_i2c_resource,
226};
227
533ad5e6
CM		 228static struct i2c_board_info realview_i2c_board_info[] = {
229 {
64e8be6e 230 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
533ad5e6
CM		 231 },
232};
233
234static int __init realview_i2c_init(void)
235{
236 return i2c_register_board_info(0, realview_i2c_board_info,
237 ARRAY_SIZE(realview_i2c_board_info));
238}
239arch_initcall(realview_i2c_init);
240
8ad68bbf
CM		 241#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
242
98b0979f
RK		 243/*
244 * This is only used if GPIOLIB support is disabled
245 */
8ad68bbf
CM		 246static unsigned int realview_mmc_status(struct device *dev)
247{
248 struct amba_device *adev = container_of(dev, struct amba_device, dev);
249 u32 mask;
250
251 if (adev->res.start == REALVIEW_MMCI0_BASE)
252 mask = 1;
253 else
254 mask = 2;
255
256 return readl(REALVIEW_SYSMCI) & mask;
257}
258
6ef297f8 259struct mmci_platform_data realview_mmc0_plat_data = {
8ad68bbf
CM		 260 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
261 .status = realview_mmc_status,
98b0979f
RK		 262 .gpio_wp = 17,
263 .gpio_cd = 16,
8ad68bbf
CM		 264};
265
6ef297f8 266struct mmci_platform_data realview_mmc1_plat_data = {
8ad68bbf
CM		 267 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
268 .status = realview_mmc_status,
98b0979f
RK		 269 .gpio_wp = 19,
270 .gpio_cd = 18,
8ad68bbf
CM		 271};
272
273/*
274 * Clock handling
275 */
39c0cb02 276static const struct icst_params realview_oscvco_params = {
64fceb1d 277 .ref = 24000000,
4de2edbd 278 .vco_max = ICST307_VCO_MAX,
8ad68bbf
CM		 279 .vd_min = 4 + 8,
280 .vd_max = 511 + 8,
281 .rd_min = 1 + 2,
282 .rd_max = 127 + 2,
283};
284
39c0cb02 285static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
8ad68bbf
CM		 286{
287 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
68c3d935 288 void __iomem *sys_osc;
8ad68bbf
CM		 289 u32 val;
290
68c3d935
CT		 291 if (machine_is_realview_pb1176())
292 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
293 else
294 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
295
8ad68bbf
CM		 296 val = readl(sys_osc) & ~0x7ffff;
297 val |= vco.v | (vco.r << 9) | (vco.s << 16);
298
299 writel(0xa05f, sys_lock);
300 writel(val, sys_osc);
301 writel(0, sys_lock);
302}
303
cf30fb4a 304static struct clk oscvco_clk = {
8ad68bbf
CM		 305 .params = &realview_oscvco_params,
306 .setvco = realview_oscvco_set,
307};
308
cf30fb4a
RK		 309/*
310 * These are fixed clocks.
311 */
312static struct clk ref24_clk = {
313 .rate = 24000000,
314};
315
316static struct clk_lookup lookups[] = {
317 { /* UART0 */
4321532c 318 .dev_id = "dev:uart0",
cf30fb4a
RK		 319 .clk = &ref24_clk,
320 }, { /* UART1 */
4321532c 321 .dev_id = "dev:uart1",
cf30fb4a
RK		 322 .clk = &ref24_clk,
323 }, { /* UART2 */
4321532c 324 .dev_id = "dev:uart2",
cf30fb4a
RK		 325 .clk = &ref24_clk,
326 }, { /* UART3 */
4321532c 327 .dev_id = "fpga:uart3",
cf30fb4a
RK		 328 .clk = &ref24_clk,
329 }, { /* KMI0 */
4321532c 330 .dev_id = "fpga:kmi0",
cf30fb4a
RK		 331 .clk = &ref24_clk,
332 }, { /* KMI1 */
4321532c 333 .dev_id = "fpga:kmi1",
cf30fb4a
RK		 334 .clk = &ref24_clk,
335 }, { /* MMC0 */
4321532c 336 .dev_id = "fpga:mmc0",
cf30fb4a
RK		 337 .clk = &ref24_clk,
338 }, { /* EB:CLCD */
4321532c 339 .dev_id = "dev:clcd",
cf30fb4a
RK		 340 .clk = &oscvco_clk,
341 }, { /* PB:CLCD */
4321532c 342 .dev_id = "issp:clcd",
cf30fb4a
RK		 343 .clk = &oscvco_clk,
344 }
345};
346
347static int __init clk_init(void)
348{
0a0300dc 349 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
cf30fb4a
RK		 350 return 0;
351}
352arch_initcall(clk_init);
353
8ad68bbf
CM		 354/*
355 * CLCD support.
356 */
8ad68bbf
CM		 357#define SYS_CLCD_NLCDIOON (1 << 2)
358#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
359#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
360#define SYS_CLCD_ID_MASK (0x1f << 8)
361#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
362#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
363#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
364#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
365#define SYS_CLCD_ID_VGA (0x1f << 8)
366
367static struct clcd_panel vga = {
368 .mode = {
369 .name = "VGA",
370 .refresh = 60,
371 .xres = 640,
372 .yres = 480,
373 .pixclock = 39721,
374 .left_margin = 40,
375 .right_margin = 24,
376 .upper_margin = 32,
377 .lower_margin = 11,
378 .hsync_len = 96,
379 .vsync_len = 2,
380 .sync = 0,
381 .vmode = FB_VMODE_NONINTERLACED,
382 },
383 .width = -1,
384 .height = -1,
385 .tim2 = TIM2_BCD | TIM2_IPC,
4eccca20 386 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 387 .bpp = 16,
388};
389
c34a1025
CT		 390static struct clcd_panel xvga = {
391 .mode = {
392 .name = "XVGA",
393 .refresh = 60,
394 .xres = 1024,
395 .yres = 768,
396 .pixclock = 15748,
397 .left_margin = 152,
398 .right_margin = 48,
399 .upper_margin = 23,
400 .lower_margin = 3,
401 .hsync_len = 104,
402 .vsync_len = 4,
403 .sync = 0,
404 .vmode = FB_VMODE_NONINTERLACED,
405 },
406 .width = -1,
407 .height = -1,
408 .tim2 = TIM2_BCD | TIM2_IPC,
4eccca20 409 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 410 .bpp = 16,
411};
412
413static struct clcd_panel sanyo_3_8_in = {
414 .mode = {
415 .name = "Sanyo QVGA",
416 .refresh = 116,
417 .xres = 320,
418 .yres = 240,
419 .pixclock = 100000,
420 .left_margin = 6,
421 .right_margin = 6,
422 .upper_margin = 5,
423 .lower_margin = 5,
424 .hsync_len = 6,
425 .vsync_len = 6,
426 .sync = 0,
427 .vmode = FB_VMODE_NONINTERLACED,
428 },
429 .width = -1,
430 .height = -1,
431 .tim2 = TIM2_BCD,
4eccca20 432 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 433 .bpp = 16,
434};
435
436static struct clcd_panel sanyo_2_5_in = {
437 .mode = {
438 .name = "Sanyo QVGA Portrait",
439 .refresh = 116,
440 .xres = 240,
441 .yres = 320,
442 .pixclock = 100000,
443 .left_margin = 20,
444 .right_margin = 10,
445 .upper_margin = 2,
446 .lower_margin = 2,
447 .hsync_len = 10,
448 .vsync_len = 2,
449 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
450 .vmode = FB_VMODE_NONINTERLACED,
451 },
452 .width = -1,
453 .height = -1,
454 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
4eccca20 455 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 456 .bpp = 16,
457};
458
459static struct clcd_panel epson_2_2_in = {
460 .mode = {
461 .name = "Epson QCIF",
462 .refresh = 390,
463 .xres = 176,
464 .yres = 220,
465 .pixclock = 62500,
466 .left_margin = 3,
467 .right_margin = 2,
468 .upper_margin = 1,
469 .lower_margin = 0,
470 .hsync_len = 3,
471 .vsync_len = 2,
472 .sync = 0,
473 .vmode = FB_VMODE_NONINTERLACED,
474 },
475 .width = -1,
476 .height = -1,
477 .tim2 = TIM2_BCD | TIM2_IPC,
4eccca20 478 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
8ad68bbf
CM		 479 .bpp = 16,
480};
481
482/*
483 * Detect which LCD panel is connected, and return the appropriate
484 * clcd_panel structure. Note: we do not have any information on
485 * the required timings for the 8.4in panel, so we presently assume
486 * VGA timings.
487 */
488static struct clcd_panel *realview_clcd_panel(void)
489{
490 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
c34a1025
CT		 491 struct clcd_panel *vga_panel;
492 struct clcd_panel *panel;
8ad68bbf
CM		 493 u32 val;
494
c34a1025
CT		 495 if (machine_is_realview_eb())
496 vga_panel = &vga;
497 else
498 vga_panel = &xvga;
499
8ad68bbf
CM		 500 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
501 if (val == SYS_CLCD_ID_SANYO_3_8)
502 panel = &sanyo_3_8_in;
503 else if (val == SYS_CLCD_ID_SANYO_2_5)
504 panel = &sanyo_2_5_in;
505 else if (val == SYS_CLCD_ID_EPSON_2_2)
506 panel = &epson_2_2_in;
507 else if (val == SYS_CLCD_ID_VGA)
c34a1025 508 panel = vga_panel;
8ad68bbf
CM		 509 else {
510 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
511 val);
c34a1025 512 panel = vga_panel;
8ad68bbf
CM		 513 }
514
515 return panel;
516}
517
518/*
519 * Disable all display connectors on the interface module.
520 */
521static void realview_clcd_disable(struct clcd_fb *fb)
522{
523 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
524 u32 val;
525
526 val = readl(sys_clcd);
527 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
528 writel(val, sys_clcd);
529}
530
531/*
532 * Enable the relevant connector on the interface module.
533 */
534static void realview_clcd_enable(struct clcd_fb *fb)
535{
536 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
537 u32 val;
538
8ad68bbf 539 /*
9e7714d0 540 * Enable the PSUs
8ad68bbf 541 */
9e7714d0 542 val = readl(sys_clcd);
8ad68bbf
CM		 543 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
544 writel(val, sys_clcd);
545}
546
8ad68bbf
CM		 547static int realview_clcd_setup(struct clcd_fb *fb)
548{
c34a1025 549 unsigned long framesize;
8ad68bbf
CM		 550 dma_addr_t dma;
551
c34a1025
CT		 552 if (machine_is_realview_eb())
553 /* VGA, 16bpp */
554 framesize = 640 * 480 * 2;
555 else
556 /* XVGA, 16bpp */
557 framesize = 1024 * 768 * 2;
558
8ad68bbf
CM		 559 fb->panel = realview_clcd_panel();
560
561 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
c97c5aa8 562 &dma, GFP_KERNEL | GFP_DMA);
8ad68bbf
CM		 563 if (!fb->fb.screen_base) {
564 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
565 return -ENOMEM;
566 }
567
568 fb->fb.fix.smem_start = dma;
569 fb->fb.fix.smem_len = framesize;
570
571 return 0;
572}
573
574static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
575{
576 return dma_mmap_writecombine(&fb->dev->dev, vma,
577 fb->fb.screen_base,
578 fb->fb.fix.smem_start,
579 fb->fb.fix.smem_len);
580}
581
582static void realview_clcd_remove(struct clcd_fb *fb)
583{
584 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
585 fb->fb.screen_base, fb->fb.fix.smem_start);
586}
587
588struct clcd_board clcd_plat_data = {
589 .name = "RealView",
590 .check = clcdfb_check,
591 .decode = clcdfb_decode,
592 .disable = realview_clcd_disable,
593 .enable = realview_clcd_enable,
594 .setup = realview_clcd_setup,
595 .mmap = realview_clcd_mmap,
596 .remove = realview_clcd_remove,
597};
598
599#ifdef CONFIG_LEDS
600#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
601
602void realview_leds_event(led_event_t ledevt)
603{
604 unsigned long flags;
605 u32 val;
da055eb5 606 u32 led = 1 << smp_processor_id();
8ad68bbf
CM		 607
608 local_irq_save(flags);
609 val = readl(VA_LEDS_BASE);
610
611 switch (ledevt) {
612 case led_idle_start:
da055eb5 613 val = val & ~led;
8ad68bbf
CM		 614 break;
615
616 case led_idle_end:
da055eb5 617 val = val | led;
8ad68bbf
CM		 618 break;
619
620 case led_timer:
da055eb5 621 val = val ^ REALVIEW_SYS_LED7;
8ad68bbf
CM		 622 break;
623
624 case led_halted:
625 val = 0;
626 break;
627
628 default:
629 break;
630 }
631
632 writel(val, VA_LEDS_BASE);
633 local_irq_restore(flags);
634}
635#endif /* CONFIG_LEDS */
636
637/*
638 * Where is the timer (VA)?
639 */
80192735
CM		 640void __iomem *timer0_va_base;
641void __iomem *timer1_va_base;
642void __iomem *timer2_va_base;
643void __iomem *timer3_va_base;
8ad68bbf
CM		 644
645/*
646 * How long is the timer interval?
647 */
648#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
649#if TIMER_INTERVAL >= 0x100000
650#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
651#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
652#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
653#elif TIMER_INTERVAL >= 0x10000
654#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
655#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
656#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
657#else
658#define TIMER_RELOAD (TIMER_INTERVAL)
659#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
660#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
661#endif
662
ae30ceac
CM		 663static void timer_set_mode(enum clock_event_mode mode,
664 struct clock_event_device *clk)
665{
666 unsigned long ctrl;
667
668 switch(mode) {
669 case CLOCK_EVT_MODE_PERIODIC:
80192735 670 writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
ae30ceac
CM		 671
672 ctrl = TIMER_CTRL_PERIODIC;
673 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
674 break;
675 case CLOCK_EVT_MODE_ONESHOT:
676 /* period set, and timer enabled in 'next_event' hook */
677 ctrl = TIMER_CTRL_ONESHOT;
678 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
679 break;
680 case CLOCK_EVT_MODE_UNUSED:
681 case CLOCK_EVT_MODE_SHUTDOWN:
682 default:
683 ctrl = 0;
684 }
685
80192735 686 writel(ctrl, timer0_va_base + TIMER_CTRL);
ae30ceac
CM		 687}
688
689static int timer_set_next_event(unsigned long evt,
690 struct clock_event_device *unused)
691{
80192735 692 unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
ae30ceac 693
80192735
CM		 694 writel(evt, timer0_va_base + TIMER_LOAD);
695 writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
ae30ceac
CM		 696
697 return 0;
698}
699
700static struct clock_event_device timer0_clockevent = {
701 .name = "timer0",
702 .shift = 32,
703 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
704 .set_mode = timer_set_mode,
705 .set_next_event = timer_set_next_event,
706 .rating = 300,
320ab2b0 707 .cpumask = cpu_all_mask,
ae30ceac
CM		 708};
709
8cc4c548 710static void __init realview_clockevents_init(unsigned int timer_irq)
ae30ceac 711{
8cc4c548 712 timer0_clockevent.irq = timer_irq;
ae30ceac
CM		 713 timer0_clockevent.mult =
714 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
715 timer0_clockevent.max_delta_ns =
716 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
717 timer0_clockevent.min_delta_ns =
718 clockevent_delta2ns(0xf, &timer0_clockevent);
719
720 clockevents_register_device(&timer0_clockevent);
721}
722
8ad68bbf
CM		 723/*
724 * IRQ handler for the timer
725 */
0cd61b68 726static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
8ad68bbf 727{
ae30ceac 728 struct clock_event_device *evt = &timer0_clockevent;
8ad68bbf 729
ae30ceac 730 /* clear the interrupt */
80192735 731 writel(1, timer0_va_base + TIMER_INTCLR);
8ad68bbf 732
ae30ceac 733 evt->event_handler(evt);
dbebb4cb 734
8ad68bbf
CM		 735 return IRQ_HANDLED;
736}
737
738static struct irqaction realview_timer_irq = {
739 .name = "RealView Timer Tick",
b30fabad 740 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
8ad68bbf
CM		 741 .handler = realview_timer_interrupt,
742};
743
8e19608e 744static cycle_t realview_get_cycles(struct clocksource *cs)
85802afe 745{
80192735 746 return ~readl(timer3_va_base + TIMER_VALUE);
85802afe
CM		 747}
748
749static struct clocksource clocksource_realview = {
750 .name = "timer3",
751 .rating = 200,
752 .read = realview_get_cycles,
753 .mask = CLOCKSOURCE_MASK(32),
754 .shift = 20,
755 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
756};
757
758static void __init realview_clocksource_init(void)
759{
760 /* setup timer 0 as free-running clocksource */
80192735
CM		 761 writel(0, timer3_va_base + TIMER_CTRL);
762 writel(0xffffffff, timer3_va_base + TIMER_LOAD);
763 writel(0xffffffff, timer3_va_base + TIMER_VALUE);
85802afe 764 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
80192735 765 timer3_va_base + TIMER_CTRL);
85802afe
CM		 766
767 clocksource_realview.mult =
768 clocksource_khz2mult(1000, clocksource_realview.shift);
769 clocksource_register(&clocksource_realview);
770}
771
8ad68bbf 772/*
a8655e83 773 * Set up the clock source and clock events devices
8ad68bbf 774 */
8cc4c548 775void __init realview_timer_init(unsigned int timer_irq)
8ad68bbf
CM		 776{
777 u32 val;
778
779 /*
780 * set clock frequency:
781 * REALVIEW_REFCLK is 32KHz
782 * REALVIEW_TIMCLK is 1MHz
783 */
784 val = readl(__io_address(REALVIEW_SCTL_BASE));
785 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
786 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
787 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
788 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
789 __io_address(REALVIEW_SCTL_BASE));
790
791 /*
792 * Initialise to a known state (all timers off)
793 */
80192735
CM		 794 writel(0, timer0_va_base + TIMER_CTRL);
795 writel(0, timer1_va_base + TIMER_CTRL);
796 writel(0, timer2_va_base + TIMER_CTRL);
797 writel(0, timer3_va_base + TIMER_CTRL);
8ad68bbf 798
8ad68bbf
CM		 799 /*
800 * Make irqs happen for the system timer
801 */
8cc4c548 802 setup_irq(timer_irq, &realview_timer_irq);
85802afe
CM		 803
804 realview_clocksource_init();
8cc4c548 805 realview_clockevents_init(timer_irq);
8ad68bbf 806}
5b39d154
CM		 807
808/*
809 * Setup the memory banks.
810 */
811void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
812 struct meminfo *meminfo)
813{
814 /*
815 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
816 * Half of this is mirrored at 0.
817 */
818#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
819 meminfo->bank[0].start = 0x70000000;
820 meminfo->bank[0].size = SZ_512M;
821 meminfo->nr_banks = 1;
822#else
823 meminfo->bank[0].start = 0;
824 meminfo->bank[0].size = SZ_256M;
825 meminfo->nr_banks = 1;
826#endif
827}
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