[net-next-2.6.git] / arch / arm / mach-pxa / pxa3xx.c

/*
 * linux/arch/arm/mach-pxa/pxa3xx.c
 *
 * code specific to pxa3xx aka Monahans
 *
 * Copyright (C) 2006 Marvell International Ltd.
 *
 * 2007-09-02: eric miao <eric.miao@marvell.com>
 *             initial version
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/pxa3xx-regs.h>
#include <mach/reset.h>
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
#include <mach/regs-intc.h>
#include <plat/i2c.h>

#include "generic.h"
#include "devices.h"
#include "clock.h"

/* Crystal clock: 13MHz */
#define BASE_CLK	13000000

/* Ring Oscillator Clock: 60MHz */
#define RO_CLK		60000000

#define ACCR_D0CS	(1 << 26)
#define ACCR_PCCE	(1 << 11)

#define PECR_IE(n)	((1 << ((n) * 2)) << 28)
#define PECR_IS(n)	((1 << ((n) * 2)) << 29)

/* crystal frequency to static memory controller multiplier (SMCFS) */
static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };

/* crystal frequency to HSIO bus frequency multiplier (HSS) */
static unsigned char hss_mult[4] = { 8, 12, 16, 24 };

/*
 * Get the clock frequency as reflected by CCSR and the turbo flag.
 * We assume these values have been applied via a fcs.
 * If info is not 0 we also display the current settings.
 */
unsigned int pxa3xx_get_clk_frequency_khz(int info)
{
	unsigned long acsr, xclkcfg;
	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;

	/* Read XCLKCFG register turbo bit */
	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	t = xclkcfg & 0x1;

	acsr = ACSR;

	xl  = acsr & 0x1f;
	xn  = (acsr >> 8) & 0x7;
	hss = (acsr >> 14) & 0x3;

	XL = xl * BASE_CLK;
	XN = xn * XL;

	ro = acsr & ACCR_D0CS;

	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	if (info) {
		pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
			RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
			(ro) ? "" : "in");
		pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
			XL / 1000000, (XL % 1000000) / 10000, xl);
		pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
			XN / 1000000, (XN % 1000000) / 10000, xn,
			(t) ? "" : "in");
		pr_info("HSIO bus clock: %d.%02dMHz\n",
			HSS / 1000000, (HSS % 1000000) / 10000);
	}

	return CLK / 1000;
}

/*
 * Return the current static memory controller clock frequency
 * in units of 10kHz
 */
unsigned int pxa3xx_get_memclk_frequency_10khz(void)
{
	unsigned long acsr;
	unsigned int smcfs, clk = 0;

	acsr = ACSR;

	smcfs = (acsr >> 23) & 0x7;
	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;

	return (clk / 10000);
}

void pxa3xx_clear_reset_status(unsigned int mask)
{
	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	ARSR = mask;
}

/*
 * Return the current AC97 clock frequency.
 */
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
{
	unsigned long rate = 312000000;
	unsigned long ac97_div;

	ac97_div = AC97_DIV;

	/* This may loose precision for some rates but won't for the
	 * standard 24.576MHz.
	 */
	rate /= (ac97_div >> 12) & 0x7fff;
	rate *= (ac97_div & 0xfff);

	return rate;
}

/*
 * Return the current HSIO bus clock frequency
 */
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
{
	unsigned long acsr;
	unsigned int hss, hsio_clk;

	acsr = ACSR;

	hss = (acsr >> 14) & 0x3;
	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;

	return hsio_clk;
}

void clk_pxa3xx_cken_enable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA |= mask;
	else
		CKENB |= mask;
}

void clk_pxa3xx_cken_disable(struct clk *clk)
{
	unsigned long mask = 1ul << (clk->cken & 0x1f);

	if (clk->cken < 32)
		CKENA &= ~mask;
	else
		CKENB &= ~mask;
}

const struct clkops clk_pxa3xx_cken_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
};

static const struct clkops clk_pxa3xx_hsio_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_hsio_getrate,
};

static const struct clkops clk_pxa3xx_ac97_ops = {
	.enable		= clk_pxa3xx_cken_enable,
	.disable	= clk_pxa3xx_cken_disable,
	.getrate	= clk_pxa3xx_ac97_getrate,
};

static void clk_pout_enable(struct clk *clk)
{
	OSCC |= OSCC_PEN;
}

static void clk_pout_disable(struct clk *clk)
{
	OSCC &= ~OSCC_PEN;
}

static const struct clkops clk_pout_ops = {
	.enable		= clk_pout_enable,
	.disable	= clk_pout_disable,
};

static void clk_dummy_enable(struct clk *clk)
{
}

static void clk_dummy_disable(struct clk *clk)
{
}

static const struct clkops clk_dummy_ops = {
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable,
};

static struct clk clk_pxa3xx_pout = {
	.ops		= &clk_pout_ops,
	.rate		= 13000000,
	.delay		= 70,
};

static struct clk clk_dummy = {
	.ops		= &clk_dummy_ops,
};

static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);

static struct clk_lookup pxa3xx_clkregs[] = {
	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	/* Power I2C clock is always on */
	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
	INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
};

#ifdef CONFIG_PM

#define ISRAM_START	0x5c000000
#define ISRAM_SIZE	SZ_256K

static void __iomem *sram;
static unsigned long wakeup_src;

#define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]

enum {	SLEEP_SAVE_CKENA,
	SLEEP_SAVE_CKENB,
	SLEEP_SAVE_ACCR,

	SLEEP_SAVE_COUNT,
};

static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
{
	SAVE(CKENA);
	SAVE(CKENB);
	SAVE(ACCR);
}

static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
{
	RESTORE(ACCR);
	RESTORE(CKENA);
	RESTORE(CKENB);
}

/*
 * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 * memory controller has to be reinitialised, so we place some code
 * in the SRAM to perform this function.
 *
 * We disable FIQs across the standby - otherwise, we might receive a
 * FIQ while the SDRAM is unavailable.
 */
static void pxa3xx_cpu_standby(unsigned int pwrmode)
{
	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);

	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
		    pm_enter_standby_end - pm_enter_standby_start);

	AD2D0SR = ~0;
	AD2D1SR = ~0;
	AD2D0ER = wakeup_src;
	AD2D1ER = 0;
	ASCR = ASCR;
	ARSR = ARSR;

	local_fiq_disable();
	fn(pwrmode);
	local_fiq_enable();

	AD2D0ER = 0;
	AD2D1ER = 0;
}

/*
 * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 * PXA3xx development kits assumes that the resuming process continues
 * with the address stored within the first 4 bytes of SDRAM. The PSPR
 * register is used privately by BootROM and OBM, and _must_ be set to
 * 0x5c014000 for the moment.
 */
static void pxa3xx_cpu_pm_suspend(void)
{
	volatile unsigned long *p = (volatile void *)0xc0000000;
	unsigned long saved_data = *p;

	extern void pxa3xx_cpu_suspend(void);
	extern void pxa3xx_cpu_resume(void);

	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);

	/* clear and setup wakeup source */
	AD3SR = ~0;
	AD3ER = wakeup_src;
	ASCR = ASCR;
	ARSR = ARSR;

	PCFR |= (1u << 13);			/* L1_DIS */
	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */

	PSPR = 0x5c014000;

	/* overwrite with the resume address */
	*p = virt_to_phys(pxa3xx_cpu_resume);

	pxa3xx_cpu_suspend();

	*p = saved_data;

	AD3ER = 0;
}

static void pxa3xx_cpu_pm_enter(suspend_state_t state)
{
	/*
	 * Don't sleep if no wakeup sources are defined
	 */
	if (wakeup_src == 0) {
		printk(KERN_ERR "Not suspending: no wakeup sources\n");
		return;
	}

	switch (state) {
	case PM_SUSPEND_STANDBY:
		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
		break;

	case PM_SUSPEND_MEM:
		pxa3xx_cpu_pm_suspend();
		break;
	}
}

static int pxa3xx_cpu_pm_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
	.save_count	= SLEEP_SAVE_COUNT,
	.save		= pxa3xx_cpu_pm_save,
	.restore	= pxa3xx_cpu_pm_restore,
	.valid		= pxa3xx_cpu_pm_valid,
	.enter		= pxa3xx_cpu_pm_enter,
};

static void __init pxa3xx_init_pm(void)
{
	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	if (!sram) {
		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
		return;
	}

	/*
	 * Since we copy wakeup code into the SRAM, we need to ensure
	 * that it is preserved over the low power modes.  Note: bit 8
	 * is undocumented in the developer manual, but must be set.
	 */
	AD1R |= ADXR_L2 | ADXR_R0;
	AD2R |= ADXR_L2 | ADXR_R0;
	AD3R |= ADXR_L2 | ADXR_R0;

	/*
	 * Clear the resume enable registers.
	 */
	AD1D0ER = 0;
	AD2D0ER = 0;
	AD2D1ER = 0;
	AD3ER = 0;

	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
}

static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
{
	unsigned long flags, mask = 0;

	switch (irq) {
	case IRQ_SSP3:
		mask = ADXER_MFP_WSSP3;
		break;
	case IRQ_MSL:
		mask = ADXER_WMSL0;
		break;
	case IRQ_USBH2:
	case IRQ_USBH1:
		mask = ADXER_WUSBH;
		break;
	case IRQ_KEYPAD:
		mask = ADXER_WKP;
		break;
	case IRQ_AC97:
		mask = ADXER_MFP_WAC97;
		break;
	case IRQ_USIM:
		mask = ADXER_WUSIM0;
		break;
	case IRQ_SSP2:
		mask = ADXER_MFP_WSSP2;
		break;
	case IRQ_I2C:
		mask = ADXER_MFP_WI2C;
		break;
	case IRQ_STUART:
		mask = ADXER_MFP_WUART3;
		break;
	case IRQ_BTUART:
		mask = ADXER_MFP_WUART2;
		break;
	case IRQ_FFUART:
		mask = ADXER_MFP_WUART1;
		break;
	case IRQ_MMC:
		mask = ADXER_MFP_WMMC1;
		break;
	case IRQ_SSP:
		mask = ADXER_MFP_WSSP1;
		break;
	case IRQ_RTCAlrm:
		mask = ADXER_WRTC;
		break;
	case IRQ_SSP4:
		mask = ADXER_MFP_WSSP4;
		break;
	case IRQ_TSI:
		mask = ADXER_WTSI;
		break;
	case IRQ_USIM2:
		mask = ADXER_WUSIM1;
		break;
	case IRQ_MMC2:
		mask = ADXER_MFP_WMMC2;
		break;
	case IRQ_NAND:
		mask = ADXER_MFP_WFLASH;
		break;
	case IRQ_USB2:
		mask = ADXER_WUSB2;
		break;
	case IRQ_WAKEUP0:
		mask = ADXER_WEXTWAKE0;
		break;
	case IRQ_WAKEUP1:
		mask = ADXER_WEXTWAKE1;
		break;
	case IRQ_MMC3:
		mask = ADXER_MFP_GEN12;
		break;
	default:
		return -EINVAL;
	}

	local_irq_save(flags);
	if (on)
		wakeup_src |= mask;
	else
		wakeup_src &= ~mask;
	local_irq_restore(flags);

	return 0;
}
#else
static inline void pxa3xx_init_pm(void) {}
#define pxa3xx_set_wake	NULL
#endif

static void pxa_ack_ext_wakeup(unsigned int irq)
{
	PECR |= PECR_IS(irq - IRQ_WAKEUP0);
}

static void pxa_mask_ext_wakeup(unsigned int irq)
{
	ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
	PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
}

static void pxa_unmask_ext_wakeup(unsigned int irq)
{
	ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
	PECR |= PECR_IE(irq - IRQ_WAKEUP0);
}

static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
{
	if (flow_type & IRQ_TYPE_EDGE_RISING)
		PWER |= 1 << (irq - IRQ_WAKEUP0);

	if (flow_type & IRQ_TYPE_EDGE_FALLING)
		PWER |= 1 << (irq - IRQ_WAKEUP0 + 2);

	return 0;
}

static struct irq_chip pxa_ext_wakeup_chip = {
	.name		= "WAKEUP",
	.ack		= pxa_ack_ext_wakeup,
	.mask		= pxa_mask_ext_wakeup,
	.unmask		= pxa_unmask_ext_wakeup,
	.set_type	= pxa_set_ext_wakeup_type,
};

static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
{
	int irq;

	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
		set_irq_chip(irq, &pxa_ext_wakeup_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	pxa_ext_wakeup_chip.set_wake = fn;
}

void __init pxa3xx_init_irq(void)
{
	/* enable CP6 access */
	u32 value;
	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	value |= (1 << 6);
	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));

	pxa_init_irq(56, pxa3xx_set_wake);
	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
}

/*
 * device registration specific to PXA3xx.
 */

void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
{
	pxa_register_device(&pxa3xx_device_i2c_power, info);
}

static struct platform_device *devices[] __initdata = {
	&pxa27x_device_udc,
	&pxa_device_pmu,
	&pxa_device_i2s,
	&sa1100_device_rtc,
	&pxa_device_rtc,
	&pxa27x_device_ssp1,
	&pxa27x_device_ssp2,
	&pxa27x_device_ssp3,
	&pxa3xx_device_ssp4,
	&pxa27x_device_pwm0,
	&pxa27x_device_pwm1,
};

static struct sys_device pxa3xx_sysdev[] = {
	{
		.cls	= &pxa_irq_sysclass,
	}, {
		.cls	= &pxa3xx_mfp_sysclass,
	}, {
		.cls	= &pxa_gpio_sysclass,
	},
};

static int __init pxa3xx_init(void)
{
	int i, ret = 0;

	if (cpu_is_pxa3xx()) {

		reset_status = ARSR;

		/*
		 * clear RDH bit every time after reset
		 *
		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
		 * preserve them here in case they will be referenced later
		 */
		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);

		clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));

		if ((ret = pxa_init_dma(IRQ_DMA, 32)))
			return ret;

		pxa3xx_init_pm();

		for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
			ret = sysdev_register(&pxa3xx_sysdev[i]);
			if (ret)
				pr_err("failed to register sysdev[%d]\n", i);
		}

		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
	}

	return ret;
}

postcore_initcall(pxa3xx_init);
Commit	Line	Data
2c8086a5	1	/*
	2	* linux/arch/arm/mach-pxa/pxa3xx.c
	3	*
	4	* code specific to pxa3xx aka Monahans
	5	*
	6	* Copyright (C) 2006 Marvell International Ltd.
	7	*
e9bba8ee	8	* 2007-09-02: eric miao <eric.miao@marvell.com>
2c8086a5	9	* initial version
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/pm.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/irq.h>
7b5dea12	22	#include <linux/io.h>
c0165504	23	#include <linux/sysdev.h>
2c8086a5	24
a09e64fb	25	#include <mach/hardware.h>
a58fbcd8	26	#include <mach/gpio.h>
a09e64fb	27	#include <mach/pxa3xx-regs.h>
afd2fc02	28	#include <mach/reset.h>
a09e64fb RK	29	#include <mach/ohci.h>
	30	#include <mach/pm.h>
	31	#include <mach/dma.h>
bf293aec	32	#include <mach/regs-intc.h>
f0a83701	33	#include <plat/i2c.h>
2c8086a5	34
	35	#include "generic.h"
	36	#include "devices.h"
	37	#include "clock.h"
	38
	39	/* Crystal clock: 13MHz */
	40	#define BASE_CLK 13000000
	41
	42	/* Ring Oscillator Clock: 60MHz */
	43	#define RO_CLK 60000000
	44
	45	#define ACCR_D0CS (1 << 26)
c4d1fb62	46	#define ACCR_PCCE (1 << 11)
2c8086a5	47
bf293aec MR	48	#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
	49	#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
	50
2c8086a5	51	/* crystal frequency to static memory controller multiplier (SMCFS) */
	52	static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
	53
	54	/* crystal frequency to HSIO bus frequency multiplier (HSS) */
5852984a	55	static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
2c8086a5	56
	57	/*
	58	* Get the clock frequency as reflected by CCSR and the turbo flag.
	59	* We assume these values have been applied via a fcs.
	60	* If info is not 0 we also display the current settings.
	61	*/
	62	unsigned int pxa3xx_get_clk_frequency_khz(int info)
	63	{
	64	unsigned long acsr, xclkcfg;
	65	unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
	66
	67	/* Read XCLKCFG register turbo bit */
	68	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
	69	t = xclkcfg & 0x1;
	70
	71	acsr = ACSR;
	72
	73	xl = acsr & 0x1f;
	74	xn = (acsr >> 8) & 0x7;
	75	hss = (acsr >> 14) & 0x3;
	76
	77	XL = xl * BASE_CLK;
	78	XN = xn * XL;
	79
	80	ro = acsr & ACCR_D0CS;
	81
	82	CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
	83	HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	84
	85	if (info) {
	86	pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
	87	RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
	88	(ro) ? "" : "in");
	89	pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
	90	XL / 1000000, (XL % 1000000) / 10000, xl);
	91	pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
	92	XN / 1000000, (XN % 1000000) / 10000, xn,
	93	(t) ? "" : "in");
	94	pr_info("HSIO bus clock: %d.%02dMHz\n",
	95	HSS / 1000000, (HSS % 1000000) / 10000);
	96	}
	97
6232be32	98	return CLK / 1000;
2c8086a5	99	}
	100
	101	/*
	102	* Return the current static memory controller clock frequency
	103	* in units of 10kHz
	104	*/
	105	unsigned int pxa3xx_get_memclk_frequency_10khz(void)
	106	{
	107	unsigned long acsr;
	108	unsigned int smcfs, clk = 0;
	109
	110	acsr = ACSR;
	111
	112	smcfs = (acsr >> 23) & 0x7;
	113	clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
	114
	115	return (clk / 10000);
	116	}
	117
04fef228 EM	118	void pxa3xx_clear_reset_status(unsigned int mask)
	119	{
	120	/* RESET_STATUS_* has a 1:1 mapping with ARSR */
	121	ARSR = mask;
	122	}
	123
60bfe7fa MB	124	/*
	125	* Return the current AC97 clock frequency.
	126	*/
	127	static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
	128	{
	129	unsigned long rate = 312000000;
	130	unsigned long ac97_div;
	131
	132	ac97_div = AC97_DIV;
	133
	134	/* This may loose precision for some rates but won't for the
	135	* standard 24.576MHz.
	136	*/
	137	rate /= (ac97_div >> 12) & 0x7fff;
	138	rate *= (ac97_div & 0xfff);
	139
	140	return rate;
	141	}
	142
2c8086a5	143	/*
	144	* Return the current HSIO bus clock frequency
	145	*/
	146	static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
	147	{
	148	unsigned long acsr;
	149	unsigned int hss, hsio_clk;
	150
	151	acsr = ACSR;
	152
	153	hss = (acsr >> 14) & 0x3;
	154	hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
	155
	156	return hsio_clk;
	157	}
	158
7a2c5cb0	159	void clk_pxa3xx_cken_enable(struct clk *clk)
2c8086a5	160	{
	161	unsigned long mask = 1ul << (clk->cken & 0x1f);
	162
2c8086a5	163	if (clk->cken < 32)
	164	CKENA \|= mask;
	165	else
	166	CKENB \|= mask;
2c8086a5	167	}
2c8086a5	168
7a2c5cb0	169	void clk_pxa3xx_cken_disable(struct clk *clk)
2c8086a5	170	{
	171	unsigned long mask = 1ul << (clk->cken & 0x1f);
	172
2c8086a5	173	if (clk->cken < 32)
	174	CKENA &= ~mask;
	175	else
	176	CKENB &= ~mask;
2c8086a5	177	}
2c8086a5	178
7a2c5cb0	179	const struct clkops clk_pxa3xx_cken_ops = {
2a0d7187	180	.enable = clk_pxa3xx_cken_enable,
	181	.disable = clk_pxa3xx_cken_disable,
	182	};
	183
2c8086a5	184	static const struct clkops clk_pxa3xx_hsio_ops = {
	185	.enable = clk_pxa3xx_cken_enable,
	186	.disable = clk_pxa3xx_cken_disable,
	187	.getrate = clk_pxa3xx_hsio_getrate,
	188	};
	189
60bfe7fa MB	190	static const struct clkops clk_pxa3xx_ac97_ops = {
	191	.enable = clk_pxa3xx_cken_enable,
	192	.disable = clk_pxa3xx_cken_disable,
	193	.getrate = clk_pxa3xx_ac97_getrate,
	194	};
	195
dcc88a17 MB	196	static void clk_pout_enable(struct clk *clk)
	197	{
	198	OSCC \|= OSCC_PEN;
	199	}
	200
	201	static void clk_pout_disable(struct clk *clk)
	202	{
	203	OSCC &= ~OSCC_PEN;
	204	}
	205
	206	static const struct clkops clk_pout_ops = {
	207	.enable = clk_pout_enable,
	208	.disable = clk_pout_disable,
	209	};
	210
9ba63c4f MR	211	static void clk_dummy_enable(struct clk *clk)
	212	{
	213	}
	214
	215	static void clk_dummy_disable(struct clk *clk)
	216	{
	217	}
	218
	219	static const struct clkops clk_dummy_ops = {
	220	.enable = clk_dummy_enable,
	221	.disable = clk_dummy_disable,
	222	};
	223
8c3abc7d RK	224	static struct clk clk_pxa3xx_pout = {
	225	.ops = &clk_pout_ops,
	226	.rate = 13000000,
	227	.delay = 70,
	228	};
d8e0db11	229
8c3abc7d RK	230	static struct clk clk_dummy = {
	231	.ops = &clk_dummy_ops,
	232	};
fafc9d3f	233
8c3abc7d RK	234	static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
	235	static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
	236	static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
	237	static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
	238	static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
	239	static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
	240	static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
	241	static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
	242	static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
e68750ae	243	static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
8c3abc7d RK	244	static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
	245	static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
	246	static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
	247	static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
	248	static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
	249	static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
	250	static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
	251	static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
	252	static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
	253
	254	static struct clk_lookup pxa3xx_clkregs[] = {
	255	INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
	256	/* Power I2C clock is always on */
5c68b099	257	INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
8c3abc7d RK	258	INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
	259	INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
	260	INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
	261	INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
	262	INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
	263	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
	264	INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
	265	INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
	266	INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
	267	INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
e68750ae	268	INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"),
8c3abc7d RK	269	INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
	270	INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
	271	INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
	272	INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
	273	INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
	274	INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
	275	INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
	276	INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
	277	INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
2c8086a5	278	};
2c8086a5	279
7b5dea12	280	#ifdef CONFIG_PM
7b5dea12 RK	281
	282	#define ISRAM_START 0x5c000000
	283	#define ISRAM_SIZE SZ_256K
	284
	285	static void __iomem *sram;
	286	static unsigned long wakeup_src;
	287
c4d1fb62	288	#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
c4d1fb62	289	#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
7b5dea12	290
649de51b	291	enum { SLEEP_SAVE_CKENA,
c4d1fb62	292	SLEEP_SAVE_CKENB,
c4d1fb62	293	SLEEP_SAVE_ACCR,
7b5dea12	294
649de51b	295	SLEEP_SAVE_COUNT,
c4d1fb62	296	};
	297
	298	static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
	299	{
	300	SAVE(CKENA);
	301	SAVE(CKENB);
	302	SAVE(ACCR);
7b5dea12 RK	303	}
	304
	305	static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
	306	{
c4d1fb62	307	RESTORE(ACCR);
	308	RESTORE(CKENA);
	309	RESTORE(CKENB);
7b5dea12 RK	310	}
	311
	312	/*
	313	* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
	314	* memory controller has to be reinitialised, so we place some code
	315	* in the SRAM to perform this function.
	316	*
	317	* We disable FIQs across the standby - otherwise, we might receive a
	318	* FIQ while the SDRAM is unavailable.
	319	*/
	320	static void pxa3xx_cpu_standby(unsigned int pwrmode)
	321	{
	322	extern const char pm_enter_standby_start[], pm_enter_standby_end[];
	323	void (fn)(unsigned int) = (void __force )(sram + 0x8000);
	324
	325	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
	326	pm_enter_standby_end - pm_enter_standby_start);
	327
	328	AD2D0SR = ~0;
	329	AD2D1SR = ~0;
	330	AD2D0ER = wakeup_src;
	331	AD2D1ER = 0;
	332	ASCR = ASCR;
	333	ARSR = ARSR;
	334
	335	local_fiq_disable();
	336	fn(pwrmode);
	337	local_fiq_enable();
	338
	339	AD2D0ER = 0;
	340	AD2D1ER = 0;
7b5dea12 RK	341	}
7b5dea12 RK	342
c4d1fb62	343	/*
	344	* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
	345	* PXA3xx development kits assumes that the resuming process continues
	346	* with the address stored within the first 4 bytes of SDRAM. The PSPR
	347	* register is used privately by BootROM and OBM, and _must_ be set to
	348	* 0x5c014000 for the moment.
	349	*/
	350	static void pxa3xx_cpu_pm_suspend(void)
	351	{
	352	volatile unsigned long p = (volatile void )0xc0000000;
	353	unsigned long saved_data = *p;
	354
	355	extern void pxa3xx_cpu_suspend(void);
	356	extern void pxa3xx_cpu_resume(void);
	357
	358	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
	359	CKENA \|= (1 << CKEN_BOOT) \| (1 << CKEN_TPM);
	360	CKENB \|= 1 << (CKEN_HSIO2 & 0x1f);
	361
	362	/* clear and setup wakeup source */
	363	AD3SR = ~0;
	364	AD3ER = wakeup_src;
	365	ASCR = ASCR;
	366	ARSR = ARSR;
	367
	368	PCFR \|= (1u << 13); /* L1_DIS */
	369	PCFR &= ~((1u << 12) \| (1u << 1)); /* L0_EN \| SL_ROD */
	370
	371	PSPR = 0x5c014000;
	372
	373	/* overwrite with the resume address */
	374	*p = virt_to_phys(pxa3xx_cpu_resume);
	375
	376	pxa3xx_cpu_suspend();
	377
	378	*p = saved_data;
	379
	380	AD3ER = 0;
	381	}
	382
7b5dea12 RK	383	static void pxa3xx_cpu_pm_enter(suspend_state_t state)
	384	{
	385	/*
	386	* Don't sleep if no wakeup sources are defined
	387	*/
b86a5da8 MB	388	if (wakeup_src == 0) {
b86a5da8 MB	389	printk(KERN_ERR "Not suspending: no wakeup sources\n");
7b5dea12	390	return;
b86a5da8	391	}
7b5dea12 RK	392
	393	switch (state) {
	394	case PM_SUSPEND_STANDBY:
	395	pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
	396	break;
	397
	398	case PM_SUSPEND_MEM:
c4d1fb62	399	pxa3xx_cpu_pm_suspend();
7b5dea12 RK	400	break;
	401	}
	402	}
	403
	404	static int pxa3xx_cpu_pm_valid(suspend_state_t state)
	405	{
	406	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	407	}
	408
	409	static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
649de51b	410	.save_count = SLEEP_SAVE_COUNT,
7b5dea12 RK	411	.save = pxa3xx_cpu_pm_save,
	412	.restore = pxa3xx_cpu_pm_restore,
	413	.valid = pxa3xx_cpu_pm_valid,
	414	.enter = pxa3xx_cpu_pm_enter,
2c8086a5	415	};
2c8086a5	416
7b5dea12 RK	417	static void __init pxa3xx_init_pm(void)
	418	{
	419	sram = ioremap(ISRAM_START, ISRAM_SIZE);
	420	if (!sram) {
	421	printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
	422	return;
	423	}
	424
	425	/*
	426	* Since we copy wakeup code into the SRAM, we need to ensure
	427	* that it is preserved over the low power modes. Note: bit 8
	428	* is undocumented in the developer manual, but must be set.
	429	*/
	430	AD1R \|= ADXR_L2 \| ADXR_R0;
	431	AD2R \|= ADXR_L2 \| ADXR_R0;
	432	AD3R \|= ADXR_L2 \| ADXR_R0;
	433
	434	/*
	435	* Clear the resume enable registers.
	436	*/
	437	AD1D0ER = 0;
	438	AD2D0ER = 0;
	439	AD2D1ER = 0;
	440	AD3ER = 0;
	441
	442	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
	443	}
	444
	445	static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
	446	{
	447	unsigned long flags, mask = 0;
	448
	449	switch (irq) {
	450	case IRQ_SSP3:
	451	mask = ADXER_MFP_WSSP3;
	452	break;
	453	case IRQ_MSL:
	454	mask = ADXER_WMSL0;
	455	break;
	456	case IRQ_USBH2:
	457	case IRQ_USBH1:
	458	mask = ADXER_WUSBH;
	459	break;
	460	case IRQ_KEYPAD:
	461	mask = ADXER_WKP;
	462	break;
	463	case IRQ_AC97:
	464	mask = ADXER_MFP_WAC97;
	465	break;
	466	case IRQ_USIM:
	467	mask = ADXER_WUSIM0;
	468	break;
	469	case IRQ_SSP2:
	470	mask = ADXER_MFP_WSSP2;
	471	break;
	472	case IRQ_I2C:
	473	mask = ADXER_MFP_WI2C;
	474	break;
	475	case IRQ_STUART:
	476	mask = ADXER_MFP_WUART3;
	477	break;
	478	case IRQ_BTUART:
	479	mask = ADXER_MFP_WUART2;
	480	break;
481	case IRQ_FFUART:
482	mask = ADXER_MFP_WUART1;
483	break;
484	case IRQ_MMC:
485	mask = ADXER_MFP_WMMC1;
486	break;
487	case IRQ_SSP:
488	mask = ADXER_MFP_WSSP1;
489	break;
490	case IRQ_RTCAlrm:
491	mask = ADXER_WRTC;
492	break;
493	case IRQ_SSP4:
494	mask = ADXER_MFP_WSSP4;
495	break;
496	case IRQ_TSI:
497	mask = ADXER_WTSI;
498	break;
499	case IRQ_USIM2:
500	mask = ADXER_WUSIM1;
501	break;
502	case IRQ_MMC2:
503	mask = ADXER_MFP_WMMC2;
504	break;
505	case IRQ_NAND:
506	mask = ADXER_MFP_WFLASH;
507	break;
508	case IRQ_USB2:
509	mask = ADXER_WUSB2;
510	break;
511	case IRQ_WAKEUP0:
512	mask = ADXER_WEXTWAKE0;
513	break;
514	case IRQ_WAKEUP1:
515	mask = ADXER_WEXTWAKE1;
516	break;
517	case IRQ_MMC3:
518	mask = ADXER_MFP_GEN12;
519	break;
e1217707 MB	520	default:
e1217707 MB	521	return -EINVAL;
7b5dea12 RK	522	}
	523
	524	local_irq_save(flags);
	525	if (on)
	526	wakeup_src \|= mask;
	527	else
	528	wakeup_src &= ~mask;
	529	local_irq_restore(flags);
	530
	531	return 0;
	532	}
7b5dea12 RK	533	#else
7b5dea12 RK	534	static inline void pxa3xx_init_pm(void) {}
b9e25ace	535	#define pxa3xx_set_wake NULL
7b5dea12 RK	536	#endif
7b5dea12 RK	537
bf293aec MR	538	static void pxa_ack_ext_wakeup(unsigned int irq)
	539	{
	540	PECR \|= PECR_IS(irq - IRQ_WAKEUP0);
	541	}
	542
	543	static void pxa_mask_ext_wakeup(unsigned int irq)
	544	{
	545	ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
	546	PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
	547	}
	548
	549	static void pxa_unmask_ext_wakeup(unsigned int irq)
	550	{
	551	ICMR2 \|= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
	552	PECR \|= PECR_IE(irq - IRQ_WAKEUP0);
	553	}
	554
12882096 IG	555	static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
	556	{
	557	if (flow_type & IRQ_TYPE_EDGE_RISING)
	558	PWER \|= 1 << (irq - IRQ_WAKEUP0);
	559
	560	if (flow_type & IRQ_TYPE_EDGE_FALLING)
	561	PWER \|= 1 << (irq - IRQ_WAKEUP0 + 2);
	562
	563	return 0;
	564	}
	565
bf293aec MR	566	static struct irq_chip pxa_ext_wakeup_chip = {
	567	.name = "WAKEUP",
	568	.ack = pxa_ack_ext_wakeup,
	569	.mask = pxa_mask_ext_wakeup,
	570	.unmask = pxa_unmask_ext_wakeup,
12882096	571	.set_type = pxa_set_ext_wakeup_type,
bf293aec MR	572	};
	573
	574	static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
	575	{
	576	int irq;
	577
	578	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
	579	set_irq_chip(irq, &pxa_ext_wakeup_chip);
	580	set_irq_handler(irq, handle_edge_irq);
	581	set_irq_flags(irq, IRQF_VALID);
	582	}
	583
	584	pxa_ext_wakeup_chip.set_wake = fn;
	585	}
	586
2c8086a5	587	void __init pxa3xx_init_irq(void)
	588	{
	589	/* enable CP6 access */
	590	u32 value;
	591	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
	592	value \|= (1 << 6);
	593	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
	594
b9e25ace	595	pxa_init_irq(56, pxa3xx_set_wake);
bf293aec	596	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
a58fbcd8	597	pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
2c8086a5	598	}
	599
	600	/*
	601	* device registration specific to PXA3xx.
	602	*/
	603
9ba63c4f MR	604	void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
9ba63c4f MR	605	{
14758220	606	pxa_register_device(&pxa3xx_device_i2c_power, info);
9ba63c4f MR	607	}
9ba63c4f MR	608
2c8086a5	609	static struct platform_device *devices[] __initdata = {
94c35a6b	610	&pxa27x_device_udc,
09a5358d	611	&pxa_device_pmu,
2c8086a5	612	&pxa_device_i2s,
72493146	613	&sa1100_device_rtc,
2c8086a5	614	&pxa_device_rtc,
d8e0db11	615	&pxa27x_device_ssp1,
	616	&pxa27x_device_ssp2,
	617	&pxa27x_device_ssp3,
	618	&pxa3xx_device_ssp4,
75540c1a	619	&pxa27x_device_pwm0,
75540c1a	620	&pxa27x_device_pwm1,
2c8086a5	621	};
2c8086a5	622
c0165504	623	static struct sys_device pxa3xx_sysdev[] = {
c0165504	624	{
c0165504	625	.cls = &pxa_irq_sysclass,
4be35e23	626	}, {
4be35e23	627	.cls = &pxa3xx_mfp_sysclass,
16dfdbf0	628	}, {
16dfdbf0	629	.cls = &pxa_gpio_sysclass,
c0165504	630	},
	631	};
	632
2c8086a5	633	static int __init pxa3xx_init(void)
2c8086a5	634	{
c0165504	635	int i, ret = 0;
2c8086a5	636
2c8086a5	637	if (cpu_is_pxa3xx()) {
04fef228 EM	638
	639	reset_status = ARSR;
	640
86260f98 DK	641	/*
	642	* clear RDH bit every time after reset
	643	*
	644	* Note: the last 3 bits DxS are write-1-to-clear so carefully
	645	* preserve them here in case they will be referenced later
	646	*/
	647	ASCR &= ~(ASCR_RDH \| ASCR_D1S \| ASCR_D2S \| ASCR_D3S);
	648
0a0300dc	649	clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
2c8086a5	650
fef1f99a	651	if ((ret = pxa_init_dma(IRQ_DMA, 32)))
2c8086a5	652	return ret;
2c8086a5	653
7b5dea12 RK	654	pxa3xx_init_pm();
7b5dea12 RK	655
c0165504	656	for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
	657	ret = sysdev_register(&pxa3xx_sysdev[i]);
	658	if (ret)
	659	pr_err("failed to register sysdev[%d]\n", i);
	660	}
	661
	662	ret = platform_add_devices(devices, ARRAY_SIZE(devices));
2c8086a5	663	}
c0165504	664
c0165504	665	return ret;
2c8086a5	666	}
2c8086a5	667
1c104e0e	668	postcore_initcall(pxa3xx_init);