[net-next-2.6.git] / arch / arm / mach-pxa / mainstone.c

/*
 *  linux/arch/arm/mach-pxa/mainstone.c
 *
 *  Support for the Intel HCDDBBVA0 Development Platform.
 *  (go figure how they came up with such name...)
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 05, 2002
 *  Copyright:	MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>

#include <asm/arch/pxa-regs.h>
#include <asm/arch/mainstone.h>
#include <asm/arch/audio.h>
#include <asm/arch/pxafb.h>
#include <asm/arch/mmc.h>
#include <asm/arch/irda.h>
#include <asm/arch/ohci.h>

#include "generic.h"
#include "devices.h"


static unsigned long mainstone_irq_enabled;

static void mainstone_mask_irq(unsigned int irq)
{
	int mainstone_irq = (irq - MAINSTONE_IRQ(0));
	MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
}

static void mainstone_unmask_irq(unsigned int irq)
{
	int mainstone_irq = (irq - MAINSTONE_IRQ(0));
	/* the irq can be acknowledged only if deasserted, so it's done here */
	MST_INTSETCLR &= ~(1 << mainstone_irq);
	MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
}

static struct irq_chip mainstone_irq_chip = {
	.name		= "FPGA",
	.ack		= mainstone_mask_irq,
	.mask		= mainstone_mask_irq,
	.unmask		= mainstone_unmask_irq,
};

static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
	do {
		GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
		if (likely(pending)) {
			irq = MAINSTONE_IRQ(0) + __ffs(pending);
			desc = irq_desc + irq;
			desc_handle_irq(irq, desc);
		}
		pending = MST_INTSETCLR & mainstone_irq_enabled;
	} while (pending);
}

static void __init mainstone_init_irq(void)
{
	int irq;

	pxa27x_init_irq();

	/* setup extra Mainstone irqs */
	for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
		set_irq_chip(irq, &mainstone_irq_chip);
		set_irq_handler(irq, handle_level_irq);
		if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
		else
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}
	set_irq_flags(MAINSTONE_IRQ(8), 0);
	set_irq_flags(MAINSTONE_IRQ(12), 0);

	MST_INTMSKENA = 0;
	MST_INTSETCLR = 0;

	set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
	set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
}

#ifdef CONFIG_PM

static int mainstone_irq_resume(struct sys_device *dev)
{
	MST_INTMSKENA = mainstone_irq_enabled;
	return 0;
}

static struct sysdev_class mainstone_irq_sysclass = {
	.name = "cpld_irq",
	.resume = mainstone_irq_resume,
};

static struct sys_device mainstone_irq_device = {
	.cls = &mainstone_irq_sysclass,
};

static int __init mainstone_irq_device_init(void)
{
	int ret = sysdev_class_register(&mainstone_irq_sysclass);
	if (ret == 0)
		ret = sysdev_register(&mainstone_irq_device);
	return ret;
}

device_initcall(mainstone_irq_device_init);

#endif


static struct resource smc91x_resources[] = {
	[0] = {
		.start	= (MST_ETH_PHYS + 0x300),
		.end	= (MST_ETH_PHYS + 0xfffff),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= MAINSTONE_IRQ(3),
		.end	= MAINSTONE_IRQ(3),
		.flags	= IORESOURCE_IRQ,
	}
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
	return 0;
}

static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
}

static long mst_audio_suspend_mask;

static void mst_audio_suspend(void *priv)
{
	mst_audio_suspend_mask = MST_MSCWR2;
	MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
}

static void mst_audio_resume(void *priv)
{
	MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
}

static pxa2xx_audio_ops_t mst_audio_ops = {
	.startup	= mst_audio_startup,
	.shutdown	= mst_audio_shutdown,
	.suspend	= mst_audio_suspend,
	.resume		= mst_audio_resume,
};

static struct platform_device mst_audio_device = {
	.name		= "pxa2xx-ac97",
	.id		= -1,
	.dev		= { .platform_data = &mst_audio_ops },
};

static struct resource flash_resources[] = {
	[0] = {
		.start	= PXA_CS0_PHYS,
		.end	= PXA_CS0_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= PXA_CS1_PHYS,
		.end	= PXA_CS1_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct mtd_partition mainstoneflash0_partitions[] = {
	{
		.name =		"Bootloader",
		.size =		0x00040000,
		.offset =	0,
		.mask_flags =	MTD_WRITEABLE  /* force read-only */
	},{
		.name =		"Kernel",
		.size =		0x00400000,
		.offset =	0x00040000,
	},{
		.name =		"Filesystem",
		.size =		MTDPART_SIZ_FULL,
		.offset =	0x00440000
	}
};

static struct flash_platform_data mst_flash_data[2] = {
	{
		.map_name	= "cfi_probe",
		.parts		= mainstoneflash0_partitions,
		.nr_parts	= ARRAY_SIZE(mainstoneflash0_partitions),
	}, {
		.map_name	= "cfi_probe",
		.parts		= NULL,
		.nr_parts	= 0,
	}
};

static struct platform_device mst_flash_device[2] = {
	{
		.name		= "pxa2xx-flash",
		.id		= 0,
		.dev = {
			.platform_data = &mst_flash_data[0],
		},
		.resource = &flash_resources[0],
		.num_resources = 1,
	},
	{
		.name		= "pxa2xx-flash",
		.id		= 1,
		.dev = {
			.platform_data = &mst_flash_data[1],
		},
		.resource = &flash_resources[1],
		.num_resources = 1,
	},
};

static void mainstone_backlight_power(int on)
{
	if (on) {
		pxa_gpio_mode(GPIO16_PWM0_MD);
		pxa_set_cken(CKEN_PWM0, 1);
		PWM_CTRL0 = 0;
		PWM_PWDUTY0 = 0x3ff;
		PWM_PERVAL0 = 0x3ff;
	} else {
		PWM_CTRL0 = 0;
		PWM_PWDUTY0 = 0x0;
		PWM_PERVAL0 = 0x3FF;
		pxa_set_cken(CKEN_PWM0, 0);
	}
}

static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
	.pixclock		= 50000,
	.xres			= 640,
	.yres			= 480,
	.bpp			= 16,
	.hsync_len		= 1,
	.left_margin		= 0x9f,
	.right_margin		= 1,
	.vsync_len		= 44,
	.upper_margin		= 0,
	.lower_margin		= 0,
	.sync			= FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
	.pixclock		= 110000,
	.xres			= 240,
	.yres			= 320,
	.bpp			= 16,
	.hsync_len		= 4,
	.left_margin		= 8,
	.right_margin		= 20,
	.vsync_len		= 3,
	.upper_margin		= 1,
	.lower_margin		= 10,
	.sync			= FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info mainstone_pxafb_info = {
	.num_modes      	= 1,
	.lccr0			= LCCR0_Act,
	.lccr3			= LCCR3_PCP,
	.pxafb_backlight_power	= mainstone_backlight_power,
};

static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
{
	int err;

	/*
	 * setup GPIO for PXA27x MMC controller
	 */
	pxa_gpio_mode(GPIO32_MMCCLK_MD);
	pxa_gpio_mode(GPIO112_MMCCMD_MD);
	pxa_gpio_mode(GPIO92_MMCDAT0_MD);
	pxa_gpio_mode(GPIO109_MMCDAT1_MD);
	pxa_gpio_mode(GPIO110_MMCDAT2_MD);
	pxa_gpio_mode(GPIO111_MMCDAT3_MD);

	/* make sure SD/Memory Stick multiplexer's signals
	 * are routed to MMC controller
	 */
	MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;

	err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
			     "MMC card detect", data);
	if (err) {
		printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
		return -1;
	}

	return 0;
}

static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
{
	struct pxamci_platform_data* p_d = dev->platform_data;

	if (( 1 << vdd) & p_d->ocr_mask) {
		printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
		MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
		MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
	} else {
		printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
		MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
	}
}

static void mainstone_mci_exit(struct device *dev, void *data)
{
	free_irq(MAINSTONE_MMC_IRQ, data);
}

static struct pxamci_platform_data mainstone_mci_platform_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.init 		= mainstone_mci_init,
	.setpower 	= mainstone_mci_setpower,
	.exit		= mainstone_mci_exit,
};

static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
{
	unsigned long flags;

	local_irq_save(flags);
	if (mode & IR_SIRMODE) {
		MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
	} else if (mode & IR_FIRMODE) {
		MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
	}
	if (mode & IR_OFF) {
		MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
	} else {
		MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
	}
	local_irq_restore(flags);
}

static struct pxaficp_platform_data mainstone_ficp_platform_data = {
	.transceiver_cap  = IR_SIRMODE | IR_FIRMODE | IR_OFF,
	.transceiver_mode = mainstone_irda_transceiver_mode,
};

static struct platform_device *platform_devices[] __initdata = {
	&smc91x_device,
	&mst_audio_device,
	&mst_flash_device[0],
	&mst_flash_device[1],
};

static int mainstone_ohci_init(struct device *dev)
{
	/* setup Port1 GPIO pin. */
	pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);	/* USBHPWR1 */
	pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT);	/* USBHPEN1 */

	/* Set the Power Control Polarity Low and Power Sense
	   Polarity Low to active low. */
	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
		~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);

	return 0;
}

static struct pxaohci_platform_data mainstone_ohci_platform_data = {
	.port_mode	= PMM_PERPORT_MODE,
	.init		= mainstone_ohci_init,
};

static void __init mainstone_init(void)
{
	int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */

	mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
	mst_flash_data[1].width = 4;

	/* Compensate for SW7 which swaps the flash banks */
	mst_flash_data[SW7].name = "processor-flash";
	mst_flash_data[SW7 ^ 1].name = "mainboard-flash";

	printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
	       mst_flash_data[0].name);

	/* system bus arbiter setting
	 * - Core_Park
	 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	 */
	ARB_CNTRL = ARB_CORE_PARK | 0x234;

	/*
	 * On Mainstone, we route AC97_SYSCLK via GPIO45 to
	 * the audio daughter card
	 */
	pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);

	GPSR(GPIO48_nPOE) =
		GPIO_bit(GPIO48_nPOE) |
		GPIO_bit(GPIO49_nPWE) |
		GPIO_bit(GPIO50_nPIOR) |
		GPIO_bit(GPIO51_nPIOW) |
		GPIO_bit(GPIO85_nPCE_1) |
		GPIO_bit(GPIO54_nPCE_2);

	pxa_gpio_mode(GPIO48_nPOE_MD);
	pxa_gpio_mode(GPIO49_nPWE_MD);
	pxa_gpio_mode(GPIO50_nPIOR_MD);
	pxa_gpio_mode(GPIO51_nPIOW_MD);
	pxa_gpio_mode(GPIO85_nPCE_1_MD);
	pxa_gpio_mode(GPIO54_nPCE_2_MD);
	pxa_gpio_mode(GPIO79_pSKTSEL_MD);
	pxa_gpio_mode(GPIO55_nPREG_MD);
	pxa_gpio_mode(GPIO56_nPWAIT_MD);
	pxa_gpio_mode(GPIO57_nIOIS16_MD);

	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

	/* reading Mainstone's "Virtual Configuration Register"
	   might be handy to select LCD type here */
	if (0)
		mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
	else
		mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;

	set_pxa_fb_info(&mainstone_pxafb_info);

	pxa_set_mci_info(&mainstone_mci_platform_data);
	pxa_set_ficp_info(&mainstone_ficp_platform_data);
	pxa_set_ohci_info(&mainstone_ohci_platform_data);
}


static struct map_desc mainstone_io_desc[] __initdata = {
  	{	/* CPLD */
		.virtual	=  MST_FPGA_VIRT,
		.pfn		= __phys_to_pfn(MST_FPGA_PHYS),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}
};

static void __init mainstone_map_io(void)
{
	pxa_map_io();
	iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));

	/* initialize sleep mode regs (wake-up sources, etc) */
	PGSR0 = 0x00008800;
	PGSR1 = 0x00000002;
	PGSR2 = 0x0001FC00;
	PGSR3 = 0x00001F81;
	PWER  = 0xC0000002;
	PRER  = 0x00000002;
	PFER  = 0x00000002;
 	/*	for use I SRAM as framebuffer.	*/
 	PSLR |= 0xF04;
 	PCFR = 0x66;
 	/*	For Keypad wakeup.	*/
 	KPC &=~KPC_ASACT;
 	KPC |=KPC_AS;
 	PKWR  = 0x000FD000;
 	/*	Need read PKWR back after set it.	*/
 	PKWR;
}

MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
	/* Maintainer: MontaVista Software Inc. */
	.phys_io	= 0x40000000,
	.boot_params	= 0xa0000100,	/* BLOB boot parameter setting */
	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
	.map_io		= mainstone_map_io,
	.init_irq	= mainstone_init_irq,
	.timer		= &pxa_timer,
	.init_machine	= mainstone_init,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-pxa/mainstone.c
	3	*
	4	* Support for the Intel HCDDBBVA0 Development Platform.
	5	* (go figure how they came up with such name...)
	6	*
	7	* Author: Nicolas Pitre
	8	* Created: Nov 05, 2002
	9	* Copyright: MontaVista Software Inc.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
d052d1be	17	#include <linux/platform_device.h>
22f11c4e	18	#include <linux/sysdev.h>
1da177e4 LT	19	#include <linux/interrupt.h>
	20	#include <linux/sched.h>
	21	#include <linux/bitops.h>
	22	#include <linux/fb.h>
74ec71e1 TP	23	#include <linux/ioport.h>
	24	#include <linux/mtd/mtd.h>
	25	#include <linux/mtd/partitions.h>
1da177e4 LT	26
	27	#include <asm/types.h>
	28	#include <asm/setup.h>
	29	#include <asm/memory.h>
	30	#include <asm/mach-types.h>
	31	#include <asm/hardware.h>
	32	#include <asm/irq.h>
74ec71e1	33	#include <asm/sizes.h>
1da177e4 LT	34
	35	#include <asm/mach/arch.h>
	36	#include <asm/mach/map.h>
	37	#include <asm/mach/irq.h>
74ec71e1	38	#include <asm/mach/flash.h>
1da177e4 LT	39
	40	#include <asm/arch/pxa-regs.h>
	41	#include <asm/arch/mainstone.h>
	42	#include <asm/arch/audio.h>
	43	#include <asm/arch/pxafb.h>
	44	#include <asm/arch/mmc.h>
6f475c01	45	#include <asm/arch/irda.h>
81f280e2	46	#include <asm/arch/ohci.h>
1da177e4 LT	47
1da177e4 LT	48	#include "generic.h"
46c41e62	49	#include "devices.h"
1da177e4 LT	50
	51
	52	static unsigned long mainstone_irq_enabled;
	53
	54	static void mainstone_mask_irq(unsigned int irq)
	55	{
	56	int mainstone_irq = (irq - MAINSTONE_IRQ(0));
	57	MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
	58	}
	59
	60	static void mainstone_unmask_irq(unsigned int irq)
	61	{
	62	int mainstone_irq = (irq - MAINSTONE_IRQ(0));
	63	/* the irq can be acknowledged only if deasserted, so it's done here */
	64	MST_INTSETCLR &= ~(1 << mainstone_irq);
	65	MST_INTMSKENA = (mainstone_irq_enabled \|= (1 << mainstone_irq));
	66	}
	67
38c677cb DB	68	static struct irq_chip mainstone_irq_chip = {
38c677cb DB	69	.name = "FPGA",
1da177e4 LT	70	.ack = mainstone_mask_irq,
	71	.mask = mainstone_mask_irq,
	72	.unmask = mainstone_unmask_irq,
	73	};
	74
10dd5ce2	75	static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	76	{
	77	unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
	78	do {
	79	GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
	80	if (likely(pending)) {
	81	irq = MAINSTONE_IRQ(0) + __ffs(pending);
	82	desc = irq_desc + irq;
0cd61b68	83	desc_handle_irq(irq, desc);
1da177e4 LT	84	}
	85	pending = MST_INTSETCLR & mainstone_irq_enabled;
	86	} while (pending);
	87	}
	88
	89	static void __init mainstone_init_irq(void)
	90	{
	91	int irq;
	92
cd49104d	93	pxa27x_init_irq();
1da177e4 LT	94
	95	/* setup extra Mainstone irqs */
	96	for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
	97	set_irq_chip(irq, &mainstone_irq_chip);
10dd5ce2	98	set_irq_handler(irq, handle_level_irq);
ec64152f TG	99	if (irq == MAINSTONE_IRQ(10) \|\| irq == MAINSTONE_IRQ(14))
	100	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE \| IRQF_NOAUTOEN);
	101	else
	102	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
1da177e4 LT	103	}
	104	set_irq_flags(MAINSTONE_IRQ(8), 0);
	105	set_irq_flags(MAINSTONE_IRQ(12), 0);
	106
	107	MST_INTMSKENA = 0;
	108	MST_INTSETCLR = 0;
	109
	110	set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
	111	set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
	112	}
	113
22f11c4e NP	114	#ifdef CONFIG_PM
	115
	116	static int mainstone_irq_resume(struct sys_device *dev)
	117	{
	118	MST_INTMSKENA = mainstone_irq_enabled;
	119	return 0;
	120	}
	121
	122	static struct sysdev_class mainstone_irq_sysclass = {
af5ca3f4	123	.name = "cpld_irq",
22f11c4e NP	124	.resume = mainstone_irq_resume,
	125	};
	126
	127	static struct sys_device mainstone_irq_device = {
	128	.cls = &mainstone_irq_sysclass,
	129	};
	130
	131	static int __init mainstone_irq_device_init(void)
	132	{
	133	int ret = sysdev_class_register(&mainstone_irq_sysclass);
	134	if (ret == 0)
	135	ret = sysdev_register(&mainstone_irq_device);
	136	return ret;
	137	}
	138
	139	device_initcall(mainstone_irq_device_init);
	140
	141	#endif
	142
1da177e4 LT	143
	144	static struct resource smc91x_resources[] = {
	145	[0] = {
	146	.start = (MST_ETH_PHYS + 0x300),
	147	.end = (MST_ETH_PHYS + 0xfffff),
	148	.flags = IORESOURCE_MEM,
	149	},
	150	[1] = {
	151	.start = MAINSTONE_IRQ(3),
	152	.end = MAINSTONE_IRQ(3),
	153	.flags = IORESOURCE_IRQ,
	154	}
	155	};
	156
	157	static struct platform_device smc91x_device = {
	158	.name = "smc91x",
	159	.id = 0,
	160	.num_resources = ARRAY_SIZE(smc91x_resources),
	161	.resource = smc91x_resources,
	162	};
	163
f7cbb7fc	164	static int mst_audio_startup(struct snd_pcm_substream substream, void priv)
1da177e4 LT	165	{
	166	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	167	MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
	168	return 0;
	169	}
	170
f7cbb7fc	171	static void mst_audio_shutdown(struct snd_pcm_substream substream, void priv)
1da177e4 LT	172	{
	173	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	174	MST_MSCWR2 \|= MST_MSCWR2_AC97_SPKROFF;
	175	}
	176
	177	static long mst_audio_suspend_mask;
	178
	179	static void mst_audio_suspend(void *priv)
	180	{
	181	mst_audio_suspend_mask = MST_MSCWR2;
	182	MST_MSCWR2 \|= MST_MSCWR2_AC97_SPKROFF;
	183	}
	184
	185	static void mst_audio_resume(void *priv)
	186	{
	187	MST_MSCWR2 &= mst_audio_suspend_mask \| ~MST_MSCWR2_AC97_SPKROFF;
	188	}
	189
	190	static pxa2xx_audio_ops_t mst_audio_ops = {
	191	.startup = mst_audio_startup,
	192	.shutdown = mst_audio_shutdown,
	193	.suspend = mst_audio_suspend,
	194	.resume = mst_audio_resume,
	195	};
	196
	197	static struct platform_device mst_audio_device = {
	198	.name = "pxa2xx-ac97",
	199	.id = -1,
	200	.dev = { .platform_data = &mst_audio_ops },
	201	};
	202
74ec71e1 TP	203	static struct resource flash_resources[] = {
	204	[0] = {
	205	.start = PXA_CS0_PHYS,
	206	.end = PXA_CS0_PHYS + SZ_64M - 1,
	207	.flags = IORESOURCE_MEM,
	208	},
	209	[1] = {
	210	.start = PXA_CS1_PHYS,
	211	.end = PXA_CS1_PHYS + SZ_64M - 1,
	212	.flags = IORESOURCE_MEM,
	213	},
	214	};
	215
	216	static struct mtd_partition mainstoneflash0_partitions[] = {
	217	{
	218	.name = "Bootloader",
	219	.size = 0x00040000,
	220	.offset = 0,
	221	.mask_flags = MTD_WRITEABLE /* force read-only */
	222	},{
	223	.name = "Kernel",
	224	.size = 0x00400000,
	225	.offset = 0x00040000,
	226	},{
	227	.name = "Filesystem",
	228	.size = MTDPART_SIZ_FULL,
	229	.offset = 0x00440000
	230	}
	231	};
	232
	233	static struct flash_platform_data mst_flash_data[2] = {
	234	{
	235	.map_name = "cfi_probe",
	236	.parts = mainstoneflash0_partitions,
	237	.nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
	238	}, {
	239	.map_name = "cfi_probe",
	240	.parts = NULL,
	241	.nr_parts = 0,
	242	}
	243	};
	244
	245	static struct platform_device mst_flash_device[2] = {
	246	{
	247	.name = "pxa2xx-flash",
	248	.id = 0,
	249	.dev = {
	250	.platform_data = &mst_flash_data[0],
	251	},
	252	.resource = &flash_resources[0],
	253	.num_resources = 1,
	254	},
	255	{
	256	.name = "pxa2xx-flash",
	257	.id = 1,
	258	.dev = {
	259	.platform_data = &mst_flash_data[1],
	260	},
	261	.resource = &flash_resources[1],
	262	.num_resources = 1,
	263	},
	264	};
	265
1da177e4 LT	266	static void mainstone_backlight_power(int on)
	267	{
	268	if (on) {
	269	pxa_gpio_mode(GPIO16_PWM0_MD);
7053acbd	270	pxa_set_cken(CKEN_PWM0, 1);
1da177e4 LT	271	PWM_CTRL0 = 0;
	272	PWM_PWDUTY0 = 0x3ff;
	273	PWM_PERVAL0 = 0x3ff;
	274	} else {
	275	PWM_CTRL0 = 0;
	276	PWM_PWDUTY0 = 0x0;
	277	PWM_PERVAL0 = 0x3FF;
7053acbd	278	pxa_set_cken(CKEN_PWM0, 0);
1da177e4 LT	279	}
	280	}
	281
d14b272b	282	static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
1da177e4 LT	283	.pixclock = 50000,
	284	.xres = 640,
	285	.yres = 480,
	286	.bpp = 16,
	287	.hsync_len = 1,
	288	.left_margin = 0x9f,
	289	.right_margin = 1,
	290	.vsync_len = 44,
	291	.upper_margin = 0,
	292	.lower_margin = 0,
	293	.sync = FB_SYNC_HOR_HIGH_ACT\|FB_SYNC_VERT_HIGH_ACT,
1da177e4 LT	294	};
1da177e4 LT	295
d14b272b	296	static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
1da177e4 LT	297	.pixclock = 110000,
	298	.xres = 240,
	299	.yres = 320,
	300	.bpp = 16,
	301	.hsync_len = 4,
	302	.left_margin = 8,
	303	.right_margin = 20,
	304	.vsync_len = 3,
	305	.upper_margin = 1,
	306	.lower_margin = 10,
	307	.sync = FB_SYNC_HOR_HIGH_ACT\|FB_SYNC_VERT_HIGH_ACT,
d14b272b RP	308	};
	309
	310	static struct pxafb_mach_info mainstone_pxafb_info = {
	311	.num_modes = 1,
1da177e4 LT	312	.lccr0 = LCCR0_Act,
	313	.lccr3 = LCCR3_PCP,
	314	.pxafb_backlight_power = mainstone_backlight_power,
	315	};
	316
40220c1a	317	static int mainstone_mci_init(struct device dev, irq_handler_t mstone_detect_int, void data)
1da177e4 LT	318	{
	319	int err;
	320
	321	/*
	322	* setup GPIO for PXA27x MMC controller
	323	*/
	324	pxa_gpio_mode(GPIO32_MMCCLK_MD);
	325	pxa_gpio_mode(GPIO112_MMCCMD_MD);
	326	pxa_gpio_mode(GPIO92_MMCDAT0_MD);
	327	pxa_gpio_mode(GPIO109_MMCDAT1_MD);
	328	pxa_gpio_mode(GPIO110_MMCDAT2_MD);
	329	pxa_gpio_mode(GPIO111_MMCDAT3_MD);
	330
	331	/* make sure SD/Memory Stick multiplexer's signals
	332	* are routed to MMC controller
	333	*/
	334	MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
	335
52e405ea	336	err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
1da177e4 LT	337	"MMC card detect", data);
	338	if (err) {
	339	printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
	340	return -1;
	341	}
	342
	343	return 0;
	344	}
	345
	346	static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
	347	{
	348	struct pxamci_platform_data* p_d = dev->platform_data;
	349
	350	if (( 1 << vdd) & p_d->ocr_mask) {
	351	printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
	352	MST_MSCWR1 \|= MST_MSCWR1_MMC_ON;
	353	MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
	354	} else {
	355	printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
	356	MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
	357	}
	358	}
	359
	360	static void mainstone_mci_exit(struct device dev, void data)
	361	{
	362	free_irq(MAINSTONE_MMC_IRQ, data);
	363	}
	364
	365	static struct pxamci_platform_data mainstone_mci_platform_data = {
	366	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	367	.init = mainstone_mci_init,
	368	.setpower = mainstone_mci_setpower,
	369	.exit = mainstone_mci_exit,
	370	};
	371
6f475c01 NP	372	static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
	373	{
	374	unsigned long flags;
	375
	376	local_irq_save(flags);
	377	if (mode & IR_SIRMODE) {
	378	MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
	379	} else if (mode & IR_FIRMODE) {
	380	MST_MSCWR1 \|= MST_MSCWR1_IRDA_FIR;
	381	}
	382	if (mode & IR_OFF) {
	383	MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) \| MST_MSCWR1_IRDA_OFF;
	384	} else {
	385	MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) \| MST_MSCWR1_IRDA_FULL;
	386	}
	387	local_irq_restore(flags);
	388	}
	389
	390	static struct pxaficp_platform_data mainstone_ficp_platform_data = {
	391	.transceiver_cap = IR_SIRMODE \| IR_FIRMODE \| IR_OFF,
	392	.transceiver_mode = mainstone_irda_transceiver_mode,
	393	};
	394
74ec71e1 TP	395	static struct platform_device *platform_devices[] __initdata = {
	396	&smc91x_device,
	397	&mst_audio_device,
	398	&mst_flash_device[0],
	399	&mst_flash_device[1],
	400	};
	401
81f280e2 RP	402	static int mainstone_ohci_init(struct device *dev)
	403	{
	404	/* setup Port1 GPIO pin. */
	405	pxa_gpio_mode( 88 \| GPIO_ALT_FN_1_IN); /* USBHPWR1 */
	406	pxa_gpio_mode( 89 \| GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
	407
	408	/* Set the Power Control Polarity Low and Power Sense
	409	Polarity Low to active low. */
	410	UHCHR = (UHCHR \| UHCHR_PCPL \| UHCHR_PSPL) &
	411	~(UHCHR_SSEP1 \| UHCHR_SSEP2 \| UHCHR_SSEP3 \| UHCHR_SSE);
	412
	413	return 0;
	414	}
	415
	416	static struct pxaohci_platform_data mainstone_ohci_platform_data = {
	417	.port_mode = PMM_PERPORT_MODE,
	418	.init = mainstone_ohci_init,
	419	};
	420
1da177e4 LT	421	static void __init mainstone_init(void)
1da177e4 LT	422	{
74ec71e1 TP	423	int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
	424
	425	mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
	426	mst_flash_data[1].width = 4;
	427
	428	/* Compensate for SW7 which swaps the flash banks */
	429	mst_flash_data[SW7].name = "processor-flash";
	430	mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
	431
	432	printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
	433	mst_flash_data[0].name);
	434
5b2e98cd JH	435	/* system bus arbiter setting
	436	* - Core_Park
	437	* - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	438	*/
	439	ARB_CNTRL = ARB_CORE_PARK \| 0x234;
	440
1da177e4 LT	441	/*
	442	* On Mainstone, we route AC97_SYSCLK via GPIO45 to
	443	* the audio daughter card
	444	*/
	445	pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
	446
39cbd489 RK	447	GPSR(GPIO48_nPOE) =
	448	GPIO_bit(GPIO48_nPOE) \|
	449	GPIO_bit(GPIO49_nPWE) \|
	450	GPIO_bit(GPIO50_nPIOR) \|
	451	GPIO_bit(GPIO51_nPIOW) \|
	452	GPIO_bit(GPIO85_nPCE_1) \|
	453	GPIO_bit(GPIO54_nPCE_2);
	454
	455	pxa_gpio_mode(GPIO48_nPOE_MD);
	456	pxa_gpio_mode(GPIO49_nPWE_MD);
	457	pxa_gpio_mode(GPIO50_nPIOR_MD);
	458	pxa_gpio_mode(GPIO51_nPIOW_MD);
	459	pxa_gpio_mode(GPIO85_nPCE_1_MD);
	460	pxa_gpio_mode(GPIO54_nPCE_2_MD);
	461	pxa_gpio_mode(GPIO79_pSKTSEL_MD);
	462	pxa_gpio_mode(GPIO55_nPREG_MD);
	463	pxa_gpio_mode(GPIO56_nPWAIT_MD);
	464	pxa_gpio_mode(GPIO57_nIOIS16_MD);
	465
74ec71e1	466	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
1da177e4 LT	467
	468	/* reading Mainstone's "Virtual Configuration Register"
	469	might be handy to select LCD type here */
	470	if (0)
d14b272b	471	mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
1da177e4	472	else
d14b272b RP	473	mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
	474
	475	set_pxa_fb_info(&mainstone_pxafb_info);
1da177e4 LT	476
1da177e4 LT	477	pxa_set_mci_info(&mainstone_mci_platform_data);
6f475c01	478	pxa_set_ficp_info(&mainstone_ficp_platform_data);
81f280e2	479	pxa_set_ohci_info(&mainstone_ohci_platform_data);
1da177e4 LT	480	}
	481
	482
	483	static struct map_desc mainstone_io_desc[] __initdata = {
6f9182eb DS	484	{ /* CPLD */
	485	.virtual = MST_FPGA_VIRT,
	486	.pfn = __phys_to_pfn(MST_FPGA_PHYS),
	487	.length = 0x00100000,
	488	.type = MT_DEVICE
	489	}
1da177e4 LT	490	};
	491
	492	static void __init mainstone_map_io(void)
	493	{
	494	pxa_map_io();
	495	iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
	496
	497	/* initialize sleep mode regs (wake-up sources, etc) */
	498	PGSR0 = 0x00008800;
	499	PGSR1 = 0x00000002;
	500	PGSR2 = 0x0001FC00;
	501	PGSR3 = 0x00001F81;
	502	PWER = 0xC0000002;
	503	PRER = 0x00000002;
	504	PFER = 0x00000002;
8775420d TP	505	/* for use I SRAM as framebuffer. */
	506	PSLR \|= 0xF04;
	507	PCFR = 0x66;
	508	/* For Keypad wakeup. */
	509	KPC &=~KPC_ASACT;
	510	KPC \|=KPC_AS;
	511	PKWR = 0x000FD000;
	512	/* Need read PKWR back after set it. */
	513	PKWR;
1da177e4 LT	514	}
	515
	516	MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
e9dea0c6	517	/* Maintainer: MontaVista Software Inc. */
e9dea0c6	518	.phys_io = 0x40000000,
a7d14f87	519	.boot_params = 0xa0000100, /* BLOB boot parameter setting */
68070bde	520	.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
e9dea0c6 RK	521	.map_io = mainstone_map_io,
e9dea0c6 RK	522	.init_irq = mainstone_init_irq,
1da177e4	523	.timer = &pxa_timer,
e9dea0c6	524	.init_machine = mainstone_init,
1da177e4	525	MACHINE_END