[net-next-2.6.git] / arch / arm / mach-pxa / include / mach / hardware.h

/*
 *  arch/arm/mach-pxa/include/mach/hardware.h
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H

/*
 * We requires absolute addresses.
 */
#define PCIO_BASE		0

/*
 * Workarounds for at least 2 errata so far require this.
 * The mapping is set in mach-pxa/generic.c.
 */
#define UNCACHED_PHYS_0		0xff000000
#define UNCACHED_ADDR		UNCACHED_PHYS_0

/*
 * Intel PXA2xx internal register mapping:
 *
 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
 *
 * Note that not all PXA2xx chips implement all those addresses, and the
 * kernel only maps the minimum needed range of this mapping.
 */
#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))

#ifndef __ASSEMBLY__

# define __REG(x)	(*((volatile u32 *)io_p2v(x)))

/* With indexed regs we don't want to feed the index through io_p2v()
   especially if it is a variable, otherwise horrible code will result. */
# define __REG2(x,y)	\
	(*(volatile u32 *)((u32)&__REG(x) + (y)))

# define __PREG(x)	(io_v2p((u32)&(x)))

#else

# define __REG(x)	io_p2v(x)
# define __PREG(x)	io_v2p(x)

#endif

#ifndef __ASSEMBLY__

#include <asm/cputype.h>

/*
 *   CPU     Stepping     CPU_ID         JTAG_ID
 *
 *  PXA210	B0	0x69052922	0x2926C013
 *  PXA210	B1	0x69052923	0x3926C013
 *  PXA210	B2	0x69052924	0x4926C013
 *  PXA210	C0	0x69052D25	0x5926C013
 *
 *  PXA250	A0	0x69052100	0x09264013
 *  PXA250	A1	0x69052101	0x19264013
 *  PXA250	B0	0x69052902	0x29264013
 *  PXA250	B1	0x69052903	0x39264013
 *  PXA250	B2	0x69052904	0x49264013
 *  PXA250	C0	0x69052D05	0x59264013
 *
 *  PXA255	A0	0x69052D06	0x69264013
 *
 *  PXA26x	A0	0x69052903	0x39264013
 *  PXA26x	B0	0x69052D05	0x59264013
 *
 *  PXA27x	A0	0x69054110	0x09265013
 *  PXA27x	A1	0x69054111	0x19265013
 *  PXA27x	B0	0x69054112	0x29265013
 *  PXA27x	B1	0x69054113	0x39265013
 *  PXA27x	C0	0x69054114	0x49265013
 *  PXA27x	C5	0x69054117	0x79265013
 *
 *  PXA30x	A0	0x69056880	0x0E648013
 *  PXA30x	A1	0x69056881	0x1E648013
 *  PXA31x	A0	0x69056890	0x0E649013
 *  PXA31x	A1	0x69056891	0x1E649013
 *  PXA31x	A2	0x69056892	0x2E649013
 *  PXA32x	B1	0x69056825	0x5E642013
 *  PXA32x	B2	0x69056826	0x6E642013
 *
 *  PXA930	B0	0x69056835	0x5E643013
 *  PXA930	B1	0x69056837	0x7E643013
 *  PXA930	B2	0x69056838	0x8E643013
 *
 *  PXA935	A0	0x56056931	0x1E653013
 *  PXA935	B0	0x56056936	0x6E653013
 */
#ifdef CONFIG_PXA25x
#define __cpu_is_pxa210(id)				\
	({						\
		unsigned int _id = (id) & 0xf3f0;	\
		_id == 0x2120;				\
	})

#define __cpu_is_pxa250(id)				\
	({						\
		unsigned int _id = (id) & 0xf3ff;	\
		_id <= 0x2105;				\
	})

#define __cpu_is_pxa255(id)				\
	({						\
		unsigned int _id = (id) & 0xffff;	\
		_id == 0x2d06;				\
	})

#define __cpu_is_pxa25x(id)				\
	({						\
		unsigned int _id = (id) & 0xf300;	\
		_id == 0x2100;				\
	})
#else
#define __cpu_is_pxa210(id)	(0)
#define __cpu_is_pxa250(id)	(0)
#define __cpu_is_pxa255(id)	(0)
#define __cpu_is_pxa25x(id)	(0)
#endif

#ifdef CONFIG_PXA27x
#define __cpu_is_pxa27x(id)				\
	({						\
		unsigned int _id = (id) >> 4 & 0xfff;	\
		_id == 0x411;				\
	})
#else
#define __cpu_is_pxa27x(id)	(0)
#endif

#ifdef CONFIG_CPU_PXA300
#define __cpu_is_pxa300(id)				\
	({						\
		unsigned int _id = (id) >> 4 & 0xfff;	\
		_id == 0x688;				\
	 })
#else
#define __cpu_is_pxa300(id)	(0)
#endif

#ifdef CONFIG_CPU_PXA310
#define __cpu_is_pxa310(id)				\
	({						\
		unsigned int _id = (id) >> 4 & 0xfff;	\
		_id == 0x689;				\
	 })
#else
#define __cpu_is_pxa310(id)	(0)
#endif

#ifdef CONFIG_CPU_PXA320
#define __cpu_is_pxa320(id)				\
	({						\
		unsigned int _id = (id) >> 4 & 0xfff;	\
		_id == 0x603 || _id == 0x682;		\
	 })
#else
#define __cpu_is_pxa320(id)	(0)
#endif

#ifdef CONFIG_CPU_PXA930
#define __cpu_is_pxa930(id)				\
	({						\
		unsigned int _id = (id) >> 4 & 0xfff;	\
		_id == 0x683;				\
	 })
#else
#define __cpu_is_pxa930(id)	(0)
#endif

#ifdef CONFIG_CPU_PXA935
#define __cpu_is_pxa935(id)				\
	({						\
		unsigned int _id = (id) >> 4 & 0xfff;	\
		_id == 0x693;				\
	 })
#else
#define __cpu_is_pxa935(id)	(0)
#endif

#ifdef CONFIG_CPU_PXA950
#define __cpu_is_pxa950(id)                             \
	({                                              \
		unsigned int _id = (id) >> 4 & 0xfff;	\
		id == 0x697;				\
	 })
#else
#define __cpu_is_pxa950(id)	(0)
#endif

#define cpu_is_pxa210()					\
	({						\
		__cpu_is_pxa210(read_cpuid_id());	\
	})

#define cpu_is_pxa250()					\
	({						\
		__cpu_is_pxa250(read_cpuid_id());	\
	})

#define cpu_is_pxa255()                                 \
	({                                              \
		__cpu_is_pxa255(read_cpuid_id());       \
	})

#define cpu_is_pxa25x()					\
	({						\
		__cpu_is_pxa25x(read_cpuid_id());	\
	})

#define cpu_is_pxa27x()					\
	({						\
		__cpu_is_pxa27x(read_cpuid_id());	\
	})

#define cpu_is_pxa300()					\
	({						\
		__cpu_is_pxa300(read_cpuid_id());	\
	 })

#define cpu_is_pxa310()					\
	({						\
		__cpu_is_pxa310(read_cpuid_id());	\
	 })

#define cpu_is_pxa320()					\
	({						\
		__cpu_is_pxa320(read_cpuid_id());	\
	 })

#define cpu_is_pxa930()					\
	({						\
		unsigned int id = read_cpuid(CPUID_ID);	\
		__cpu_is_pxa930(id);			\
	 })

#define cpu_is_pxa935()					\
	({						\
		unsigned int id = read_cpuid(CPUID_ID);	\
		__cpu_is_pxa935(id);			\
	 })

#define cpu_is_pxa950()					\
	({						\
		unsigned int id = read_cpuid(CPUID_ID);	\
		__cpu_is_pxa950(id);			\
	 })


/*
 * CPUID Core Generation Bit
 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
 * == 0x3 for pxa300/pxa310/pxa320
 */
#define __cpu_is_pxa2xx(id)				\
	({						\
		unsigned int _id = (id) >> 13 & 0x7;	\
		_id <= 0x2;				\
	 })

#define __cpu_is_pxa3xx(id)				\
	({						\
		unsigned int _id = (id) >> 13 & 0x7;	\
		_id == 0x3;				\
	 })

#define __cpu_is_pxa9xx(id)				\
	({						\
		unsigned int _id = (id) >> 4 & 0xfff;	\
		_id == 0x683 || _id == 0x693;		\
	 })

#define cpu_is_pxa2xx()					\
	({						\
		__cpu_is_pxa2xx(read_cpuid_id());	\
	 })

#define cpu_is_pxa3xx()					\
	({						\
		__cpu_is_pxa3xx(read_cpuid_id());	\
	 })

#define cpu_is_pxa9xx()					\
	({						\
		__cpu_is_pxa9xx(read_cpuid_id());	\
	 })
/*
 * return current memory and LCD clock frequency in units of 10kHz
 */
extern unsigned int get_memclk_frequency_10khz(void);

/* return the clock tick rate of the OS timer */
extern unsigned long get_clock_tick_rate(void);
#endif

#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
#define PCIBIOS_MIN_IO		0
#define PCIBIOS_MIN_MEM		0
#define pcibios_assign_all_busses()	1
#define HAVE_ARCH_PCI_SET_DMA_MASK	1
#endif


#endif  /* _ASM_ARCH_HARDWARE_H */
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/mach-pxa/include/mach/hardware.h
1da177e4 LT	3	*
	4	* Author: Nicolas Pitre
	5	* Created: Jun 15, 2001
	6	* Copyright: MontaVista Software Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __ASM_ARCH_HARDWARE_H
	14	#define __ASM_ARCH_HARDWARE_H
	15
	16	/*
	17	* We requires absolute addresses.
	18	*/
	19	#define PCIO_BASE 0
	20
	21	/*
	22	* Workarounds for at least 2 errata so far require this.
	23	* The mapping is set in mach-pxa/generic.c.
	24	*/
	25	#define UNCACHED_PHYS_0 0xff000000
	26	#define UNCACHED_ADDR UNCACHED_PHYS_0
	27
	28	/*
	29	* Intel PXA2xx internal register mapping:
	30	*
	31	* 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
	32	* 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
	33	* 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
	34	* 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
	35	* 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
	36	* 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
	37	* 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
	38	*
	39	* Note that not all PXA2xx chips implement all those addresses, and the
	40	* kernel only maps the minimum needed range of this mapping.
	41	*/
	42	#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
	43	#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
	44
	45	#ifndef __ASSEMBLY__
	46
63a4b52c	47	# define __REG(x) (((volatile u32 )io_p2v(x)))
1da177e4 LT	48
	49	/* With indexed regs we don't want to feed the index through io_p2v()
	50	especially if it is a variable, otherwise horrible code will result. */
61c8c158	51	# define __REG2(x,y) \
63a4b52c	52	((volatile u32 )((u32)&__REG(x) + (y)))
1da177e4 LT	53
	54	# define __PREG(x) (io_v2p((u32)&(x)))
	55
	56	#else
	57
	58	# define __REG(x) io_p2v(x)
	59	# define __PREG(x) io_v2p(x)
	60
	61	#endif
	62
	63	#ifndef __ASSEMBLY__
	64
0ba8b9b2 RK	65	#include <asm/cputype.h>
0ba8b9b2 RK	66
0ffcbfd5 EM	67	/*
	68	* CPU Stepping CPU_ID JTAG_ID
	69	*
	70	* PXA210 B0 0x69052922 0x2926C013
	71	* PXA210 B1 0x69052923 0x3926C013
	72	* PXA210 B2 0x69052924 0x4926C013
	73	* PXA210 C0 0x69052D25 0x5926C013
	74	*
	75	* PXA250 A0 0x69052100 0x09264013
	76	* PXA250 A1 0x69052101 0x19264013
	77	* PXA250 B0 0x69052902 0x29264013
	78	* PXA250 B1 0x69052903 0x39264013
	79	* PXA250 B2 0x69052904 0x49264013
	80	* PXA250 C0 0x69052D05 0x59264013
	81	*
	82	* PXA255 A0 0x69052D06 0x69264013
	83	*
	84	* PXA26x A0 0x69052903 0x39264013
	85	* PXA26x B0 0x69052D05 0x59264013
	86	*
	87	* PXA27x A0 0x69054110 0x09265013
	88	* PXA27x A1 0x69054111 0x19265013
	89	* PXA27x B0 0x69054112 0x29265013
	90	* PXA27x B1 0x69054113 0x39265013
	91	* PXA27x C0 0x69054114 0x49265013
	92	* PXA27x C5 0x69054117 0x79265013
	93	*
	94	* PXA30x A0 0x69056880 0x0E648013
	95	* PXA30x A1 0x69056881 0x1E648013
	96	* PXA31x A0 0x69056890 0x0E649013
	97	* PXA31x A1 0x69056891 0x1E649013
	98	* PXA31x A2 0x69056892 0x2E649013
	99	* PXA32x B1 0x69056825 0x5E642013
	100	* PXA32x B2 0x69056826 0x6E642013
	101	*
	102	* PXA930 B0 0x69056835 0x5E643013
	103	* PXA930 B1 0x69056837 0x7E643013
	104	* PXA930 B2 0x69056838 0x8E643013
f1c6cd62 EM	105	*
	106	* PXA935 A0 0x56056931 0x1E653013
	107	* PXA935 B0 0x56056936 0x6E653013
0ffcbfd5	108	*/
36d8b17b	109	#ifdef CONFIG_PXA25x
0ffcbfd5	110	#define __cpu_is_pxa210(id) \
b23170c0	111	({ \
0ffcbfd5 EM	112	unsigned int _id = (id) & 0xf3f0; \
0ffcbfd5 EM	113	_id == 0x2120; \
b23170c0 RK	114	})
b23170c0 RK	115
0ffcbfd5 EM	116	#define __cpu_is_pxa250(id) \
	117	({ \
	118	unsigned int _id = (id) & 0xf3ff; \
	119	_id <= 0x2105; \
	120	})
	121
	122	#define __cpu_is_pxa255(id) \
	123	({ \
	124	unsigned int _id = (id) & 0xffff; \
	125	_id == 0x2d06; \
	126	})
aa9ae8eb	127
b23170c0 RK	128	#define __cpu_is_pxa25x(id) \
b23170c0 RK	129	({ \
0ffcbfd5 EM	130	unsigned int _id = (id) & 0xf300; \
0ffcbfd5 EM	131	_id == 0x2100; \
b23170c0	132	})
36d8b17b	133	#else
0ffcbfd5 EM	134	#define __cpu_is_pxa210(id) (0)
0ffcbfd5 EM	135	#define __cpu_is_pxa250(id) (0)
aa9ae8eb	136	#define __cpu_is_pxa255(id) (0)
36d8b17b RK	137	#define __cpu_is_pxa25x(id) (0)
36d8b17b RK	138	#endif
b23170c0	139
36d8b17b	140	#ifdef CONFIG_PXA27x
b23170c0 RK	141	#define __cpu_is_pxa27x(id) \
	142	({ \
	143	unsigned int _id = (id) >> 4 & 0xfff; \
	144	_id == 0x411; \
	145	})
36d8b17b RK	146	#else
	147	#define __cpu_is_pxa27x(id) (0)
	148	#endif
b23170c0	149
36d8b17b	150	#ifdef CONFIG_CPU_PXA300
cd272ab0	151	#define __cpu_is_pxa300(id) \
	152	({ \
	153	unsigned int _id = (id) >> 4 & 0xfff; \
	154	_id == 0x688; \
	155	})
36d8b17b RK	156	#else
	157	#define __cpu_is_pxa300(id) (0)
	158	#endif
cd272ab0	159
36d8b17b	160	#ifdef CONFIG_CPU_PXA310
cd272ab0	161	#define __cpu_is_pxa310(id) \
	162	({ \
	163	unsigned int _id = (id) >> 4 & 0xfff; \
	164	_id == 0x689; \
	165	})
36d8b17b RK	166	#else
	167	#define __cpu_is_pxa310(id) (0)
	168	#endif
cd272ab0	169
36d8b17b	170	#ifdef CONFIG_CPU_PXA320
cd272ab0	171	#define __cpu_is_pxa320(id) \
	172	({ \
	173	unsigned int _id = (id) >> 4 & 0xfff; \
	174	_id == 0x603 \|\| _id == 0x682; \
	175	})
36d8b17b RK	176	#else
	177	#define __cpu_is_pxa320(id) (0)
	178	#endif
cd272ab0	179
5d31e435 EM	180	#ifdef CONFIG_CPU_PXA930
	181	#define __cpu_is_pxa930(id) \
	182	({ \
	183	unsigned int _id = (id) >> 4 & 0xfff; \
f1c6cd62	184	_id == 0x683; \
5d31e435 EM	185	})
	186	#else
	187	#define __cpu_is_pxa930(id) (0)
	188	#endif
	189
f1c6cd62 EM	190	#ifdef CONFIG_CPU_PXA935
	191	#define __cpu_is_pxa935(id) \
	192	({ \
	193	unsigned int _id = (id) >> 4 & 0xfff; \
	194	_id == 0x693; \
	195	})
	196	#else
	197	#define __cpu_is_pxa935(id) (0)
	198	#endif
	199
4646dd27 HZ	200	#ifdef CONFIG_CPU_PXA950
	201	#define __cpu_is_pxa950(id) \
	202	({ \
	203	unsigned int _id = (id) >> 4 & 0xfff; \
	204	id == 0x697; \
	205	})
	206	#else
	207	#define __cpu_is_pxa950(id) (0)
	208	#endif
	209
0ffcbfd5	210	#define cpu_is_pxa210() \
b23170c0	211	({ \
0ffcbfd5 EM	212	__cpu_is_pxa210(read_cpuid_id()); \
	213	})
	214
	215	#define cpu_is_pxa250() \
b23170c0	216	({ \
0ffcbfd5	217	__cpu_is_pxa250(read_cpuid_id()); \
b23170c0 RK	218	})
b23170c0 RK	219
aa9ae8eb IM	220	#define cpu_is_pxa255() \
	221	({ \
	222	__cpu_is_pxa255(read_cpuid_id()); \
	223	})
	224
b23170c0 RK	225	#define cpu_is_pxa25x() \
b23170c0 RK	226	({ \
198a6d5a	227	__cpu_is_pxa25x(read_cpuid_id()); \
b23170c0 RK	228	})
	229
	230	#define cpu_is_pxa27x() \
	231	({ \
198a6d5a	232	__cpu_is_pxa27x(read_cpuid_id()); \
b23170c0 RK	233	})
b23170c0 RK	234
cd272ab0	235	#define cpu_is_pxa300() \
cd272ab0	236	({ \
198a6d5a	237	__cpu_is_pxa300(read_cpuid_id()); \
cd272ab0	238	})
	239
	240	#define cpu_is_pxa310() \
	241	({ \
198a6d5a	242	__cpu_is_pxa310(read_cpuid_id()); \
cd272ab0	243	})
	244
	245	#define cpu_is_pxa320() \
	246	({ \
198a6d5a	247	__cpu_is_pxa320(read_cpuid_id()); \
cd272ab0	248	})
cd272ab0	249
5d31e435 EM	250	#define cpu_is_pxa930() \
	251	({ \
	252	unsigned int id = read_cpuid(CPUID_ID); \
	253	__cpu_is_pxa930(id); \
	254	})
	255
f1c6cd62 EM	256	#define cpu_is_pxa935() \
	257	({ \
	258	unsigned int id = read_cpuid(CPUID_ID); \
	259	__cpu_is_pxa935(id); \
	260	})
	261
4646dd27 HZ	262	#define cpu_is_pxa950() \
	263	({ \
	264	unsigned int id = read_cpuid(CPUID_ID); \
	265	__cpu_is_pxa950(id); \
	266	})
	267
	268
cd272ab0	269	/*
	270	* CPUID Core Generation Bit
	271	* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
	272	* == 0x3 for pxa300/pxa310/pxa320
	273	*/
	274	#define __cpu_is_pxa2xx(id) \
	275	({ \
	276	unsigned int _id = (id) >> 13 & 0x7; \
	277	_id <= 0x2; \
	278	})
	279
	280	#define __cpu_is_pxa3xx(id) \
	281	({ \
	282	unsigned int _id = (id) >> 13 & 0x7; \
	283	_id == 0x3; \
	284	})
	285
f1c6cd62 EM	286	#define __cpu_is_pxa9xx(id) \
	287	({ \
	288	unsigned int _id = (id) >> 4 & 0xfff; \
	289	_id == 0x683 \|\| _id == 0x693; \
	290	})
	291
cd272ab0	292	#define cpu_is_pxa2xx() \
cd272ab0	293	({ \
198a6d5a	294	__cpu_is_pxa2xx(read_cpuid_id()); \
cd272ab0	295	})
	296
	297	#define cpu_is_pxa3xx() \
	298	({ \
198a6d5a	299	__cpu_is_pxa3xx(read_cpuid_id()); \
cd272ab0	300	})
cd272ab0	301
f1c6cd62 EM	302	#define cpu_is_pxa9xx() \
	303	({ \
	304	__cpu_is_pxa9xx(read_cpuid_id()); \
	305	})
1da177e4 LT	306	/*
	307	* return current memory and LCD clock frequency in units of 10kHz
	308	*/
	309	extern unsigned int get_memclk_frequency_10khz(void);
1da177e4	310
6769717d EM	311	/* return the clock tick rate of the OS timer */
6769717d EM	312	extern unsigned long get_clock_tick_rate(void);
1da177e4 LT	313	#endif
1da177e4 LT	314
3696a8a4 MR	315	#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
	316	#define PCIBIOS_MIN_IO 0
	317	#define PCIBIOS_MIN_MEM 0
	318	#define pcibios_assign_all_busses() 1
67fbc231	319	#define HAVE_ARCH_PCI_SET_DMA_MASK 1
3696a8a4 MR	320	#endif
3696a8a4 MR	321
67fbc231	322
1da177e4	323	#endif /* _ASM_ARCH_HARDWARE_H */