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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-pxa/include/mach/hardware.h |
1da177e4 LT |
3 | * |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_HARDWARE_H | |
14 | #define __ASM_ARCH_HARDWARE_H | |
15 | ||
16 | /* | |
17 | * We requires absolute addresses. | |
18 | */ | |
19 | #define PCIO_BASE 0 | |
20 | ||
21 | /* | |
22 | * Workarounds for at least 2 errata so far require this. | |
23 | * The mapping is set in mach-pxa/generic.c. | |
24 | */ | |
25 | #define UNCACHED_PHYS_0 0xff000000 | |
26 | #define UNCACHED_ADDR UNCACHED_PHYS_0 | |
27 | ||
28 | /* | |
29 | * Intel PXA2xx internal register mapping: | |
30 | * | |
31 | * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff | |
32 | * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff | |
33 | * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff | |
34 | * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff | |
35 | * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff | |
36 | * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff | |
37 | * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff | |
38 | * | |
39 | * Note that not all PXA2xx chips implement all those addresses, and the | |
40 | * kernel only maps the minimum needed range of this mapping. | |
41 | */ | |
42 | #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) | |
43 | #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) | |
44 | ||
45 | #ifndef __ASSEMBLY__ | |
46 | ||
63a4b52c | 47 | # define __REG(x) (*((volatile u32 *)io_p2v(x))) |
1da177e4 LT |
48 | |
49 | /* With indexed regs we don't want to feed the index through io_p2v() | |
50 | especially if it is a variable, otherwise horrible code will result. */ | |
61c8c158 | 51 | # define __REG2(x,y) \ |
63a4b52c | 52 | (*(volatile u32 *)((u32)&__REG(x) + (y))) |
1da177e4 LT |
53 | |
54 | # define __PREG(x) (io_v2p((u32)&(x))) | |
55 | ||
56 | #else | |
57 | ||
58 | # define __REG(x) io_p2v(x) | |
59 | # define __PREG(x) io_v2p(x) | |
60 | ||
61 | #endif | |
62 | ||
63 | #ifndef __ASSEMBLY__ | |
64 | ||
36d8b17b | 65 | #ifdef CONFIG_PXA25x |
b23170c0 RK |
66 | #define __cpu_is_pxa21x(id) \ |
67 | ({ \ | |
68 | unsigned int _id = (id) >> 4 & 0xf3f; \ | |
69 | _id == 0x212; \ | |
70 | }) | |
71 | ||
aa9ae8eb IM |
72 | #define __cpu_is_pxa255(id) \ |
73 | ({ \ | |
74 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
75 | _id == 0x2d0; \ | |
76 | }) | |
77 | ||
b23170c0 RK |
78 | #define __cpu_is_pxa25x(id) \ |
79 | ({ \ | |
80 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
81 | _id == 0x2d0 || _id == 0x290; \ | |
82 | }) | |
36d8b17b RK |
83 | #else |
84 | #define __cpu_is_pxa21x(id) (0) | |
aa9ae8eb | 85 | #define __cpu_is_pxa255(id) (0) |
36d8b17b RK |
86 | #define __cpu_is_pxa25x(id) (0) |
87 | #endif | |
b23170c0 | 88 | |
36d8b17b | 89 | #ifdef CONFIG_PXA27x |
b23170c0 RK |
90 | #define __cpu_is_pxa27x(id) \ |
91 | ({ \ | |
92 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
93 | _id == 0x411; \ | |
94 | }) | |
36d8b17b RK |
95 | #else |
96 | #define __cpu_is_pxa27x(id) (0) | |
97 | #endif | |
b23170c0 | 98 | |
36d8b17b | 99 | #ifdef CONFIG_CPU_PXA300 |
cd272ab0 | 100 | #define __cpu_is_pxa300(id) \ |
101 | ({ \ | |
102 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
103 | _id == 0x688; \ | |
104 | }) | |
36d8b17b RK |
105 | #else |
106 | #define __cpu_is_pxa300(id) (0) | |
107 | #endif | |
cd272ab0 | 108 | |
36d8b17b | 109 | #ifdef CONFIG_CPU_PXA310 |
cd272ab0 | 110 | #define __cpu_is_pxa310(id) \ |
111 | ({ \ | |
112 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
113 | _id == 0x689; \ | |
114 | }) | |
36d8b17b RK |
115 | #else |
116 | #define __cpu_is_pxa310(id) (0) | |
117 | #endif | |
cd272ab0 | 118 | |
36d8b17b | 119 | #ifdef CONFIG_CPU_PXA320 |
cd272ab0 | 120 | #define __cpu_is_pxa320(id) \ |
121 | ({ \ | |
122 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
123 | _id == 0x603 || _id == 0x682; \ | |
124 | }) | |
36d8b17b RK |
125 | #else |
126 | #define __cpu_is_pxa320(id) (0) | |
127 | #endif | |
cd272ab0 | 128 | |
5d31e435 EM |
129 | #ifdef CONFIG_CPU_PXA930 |
130 | #define __cpu_is_pxa930(id) \ | |
131 | ({ \ | |
132 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
133 | _id == 0x683; \ | |
134 | }) | |
135 | #else | |
136 | #define __cpu_is_pxa930(id) (0) | |
137 | #endif | |
138 | ||
b23170c0 RK |
139 | #define cpu_is_pxa21x() \ |
140 | ({ \ | |
198a6d5a | 141 | __cpu_is_pxa21x(read_cpuid_id()); \ |
b23170c0 RK |
142 | }) |
143 | ||
aa9ae8eb IM |
144 | #define cpu_is_pxa255() \ |
145 | ({ \ | |
146 | __cpu_is_pxa255(read_cpuid_id()); \ | |
147 | }) | |
148 | ||
b23170c0 RK |
149 | #define cpu_is_pxa25x() \ |
150 | ({ \ | |
198a6d5a | 151 | __cpu_is_pxa25x(read_cpuid_id()); \ |
b23170c0 RK |
152 | }) |
153 | ||
154 | #define cpu_is_pxa27x() \ | |
155 | ({ \ | |
198a6d5a | 156 | __cpu_is_pxa27x(read_cpuid_id()); \ |
b23170c0 RK |
157 | }) |
158 | ||
cd272ab0 | 159 | #define cpu_is_pxa300() \ |
160 | ({ \ | |
198a6d5a | 161 | __cpu_is_pxa300(read_cpuid_id()); \ |
cd272ab0 | 162 | }) |
163 | ||
164 | #define cpu_is_pxa310() \ | |
165 | ({ \ | |
198a6d5a | 166 | __cpu_is_pxa310(read_cpuid_id()); \ |
cd272ab0 | 167 | }) |
168 | ||
169 | #define cpu_is_pxa320() \ | |
170 | ({ \ | |
198a6d5a | 171 | __cpu_is_pxa320(read_cpuid_id()); \ |
cd272ab0 | 172 | }) |
173 | ||
5d31e435 EM |
174 | #define cpu_is_pxa930() \ |
175 | ({ \ | |
176 | unsigned int id = read_cpuid(CPUID_ID); \ | |
177 | __cpu_is_pxa930(id); \ | |
178 | }) | |
179 | ||
cd272ab0 | 180 | /* |
181 | * CPUID Core Generation Bit | |
182 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x | |
183 | * == 0x3 for pxa300/pxa310/pxa320 | |
184 | */ | |
185 | #define __cpu_is_pxa2xx(id) \ | |
186 | ({ \ | |
187 | unsigned int _id = (id) >> 13 & 0x7; \ | |
188 | _id <= 0x2; \ | |
189 | }) | |
190 | ||
191 | #define __cpu_is_pxa3xx(id) \ | |
192 | ({ \ | |
193 | unsigned int _id = (id) >> 13 & 0x7; \ | |
194 | _id == 0x3; \ | |
195 | }) | |
196 | ||
197 | #define cpu_is_pxa2xx() \ | |
198 | ({ \ | |
198a6d5a | 199 | __cpu_is_pxa2xx(read_cpuid_id()); \ |
cd272ab0 | 200 | }) |
201 | ||
202 | #define cpu_is_pxa3xx() \ | |
203 | ({ \ | |
198a6d5a | 204 | __cpu_is_pxa3xx(read_cpuid_id()); \ |
cd272ab0 | 205 | }) |
206 | ||
1da177e4 LT |
207 | /* |
208 | * Handy routine to set GPIO alternate functions | |
209 | */ | |
3deac046 PZ |
210 | extern int pxa_gpio_mode( int gpio_mode ); |
211 | ||
212 | /* | |
213 | * Return GPIO level, nonzero means high, zero is low | |
214 | */ | |
215 | extern int pxa_gpio_get_value(unsigned gpio); | |
216 | ||
217 | /* | |
218 | * Set output GPIO level | |
219 | */ | |
220 | extern void pxa_gpio_set_value(unsigned gpio, int value); | |
1da177e4 | 221 | |
1da177e4 LT |
222 | /* |
223 | * return current memory and LCD clock frequency in units of 10kHz | |
224 | */ | |
225 | extern unsigned int get_memclk_frequency_10khz(void); | |
1da177e4 LT |
226 | |
227 | #endif | |
228 | ||
3696a8a4 MR |
229 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) |
230 | #define PCIBIOS_MIN_IO 0 | |
231 | #define PCIBIOS_MIN_MEM 0 | |
232 | #define pcibios_assign_all_busses() 1 | |
233 | #endif | |
234 | ||
1da177e4 | 235 | #endif /* _ASM_ARCH_HARDWARE_H */ |