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OMAP3: PM: Prevent hang in prcm_interrupt_handler
[net-next-2.6.git] / arch / arm / mach-omap2 / pm34xx.c
CommitLineData
8bd22949
KH		 1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2005 Texas Instruments, Inc.
9 * Richard Woodruff <r-woodruff2@ti.com>
10 *
11 * Based on pm.c for omap1
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/pm.h>
19#include <linux/suspend.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/err.h>
24#include <linux/gpio.h>
25
26#include <mach/sram.h>
27#include <mach/clockdomain.h>
28#include <mach/powerdomain.h>
29#include <mach/control.h>
4af4016c 30#include <mach/serial.h>
8bd22949
KH		 31
32#include "cm.h"
33#include "cm-regbits-34xx.h"
34#include "prm-regbits-34xx.h"
35
36#include "prm.h"
37#include "pm.h"
38
39struct power_state {
40 struct powerdomain *pwrdm;
41 u32 next_state;
10f90ed2 42#ifdef CONFIG_SUSPEND
8bd22949 43 u32 saved_state;
10f90ed2 44#endif
8bd22949
KH		 45 struct list_head node;
46};
47
48static LIST_HEAD(pwrst_list);
49
50static void (*_omap_sram_idle)(u32 *addr, int save_state);
51
52static struct powerdomain *mpu_pwrdm;
53
77da2d91
JH		 54/*
55 * PRCM Interrupt Handler Helper Function
56 *
57 * The purpose of this function is to clear any wake-up events latched
58 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
59 * may occur whilst attempting to clear a PM_WKST_x register and thus
60 * set another bit in this register. A while loop is used to ensure
61 * that any peripheral wake-up events occurring while attempting to
62 * clear the PM_WKST_x are detected and cleared.
63 */
64static void prcm_clear_mod_irqs(s16 module, u8 regs)
8bd22949 65{
77da2d91
JH		 66 u32 wkst, fclk, iclk;
67 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
68 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
69 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
8bd22949 70
77da2d91 71 wkst = prm_read_mod_reg(module, wkst_off);
8bd22949 72 if (wkst) {
77da2d91
JH		 73 iclk = cm_read_mod_reg(module, iclk_off);
74 fclk = cm_read_mod_reg(module, fclk_off);
75 while (wkst) {
76 cm_set_mod_reg_bits(wkst, module, iclk_off);
77 cm_set_mod_reg_bits(wkst, module, fclk_off);
78 prm_write_mod_reg(wkst, module, wkst_off);
79 wkst = prm_read_mod_reg(module, wkst_off);
80 }
81 cm_write_mod_reg(iclk, module, iclk_off);
82 cm_write_mod_reg(fclk, module, fclk_off);
8bd22949 83 }
77da2d91 84}
8bd22949 85
77da2d91
JH		 86/*
87 * PRCM Interrupt Handler
88 *
89 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
90 * interrupts from the PRCM for the MPU. These bits must be cleared in
91 * order to clear the PRCM interrupt. The PRCM interrupt handler is
92 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
93 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
94 * register indicates that a wake-up event is pending for the MPU and
95 * this bit can only be cleared if the all the wake-up events latched
96 * in the various PM_WKST_x registers have been cleared. The interrupt
97 * handler is implemented using a do-while loop so that if a wake-up
98 * event occurred during the processing of the prcm interrupt handler
99 * (setting a bit in the corresponding PM_WKST_x register and thus
100 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
101 * this would be handled.
102 */
103static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
104{
105 u32 irqstatus_mpu;
106
107 do {
108 prcm_clear_mod_irqs(WKUP_MOD, 1);
109 prcm_clear_mod_irqs(CORE_MOD, 1);
110 prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
111 if (omap_rev() > OMAP3430_REV_ES1_0) {
112 prcm_clear_mod_irqs(CORE_MOD, 3);
113 prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
8bd22949 114 }
8bd22949 115
77da2d91
JH		 116 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
117 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
118 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
119 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
8bd22949 120
77da2d91 121 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
8bd22949
KH		 122
123 return IRQ_HANDLED;
124}
125
126static void omap_sram_idle(void)
127{
128 /* Variable to tell what needs to be saved and restored
129 * in omap_sram_idle*/
130 /* save_state = 0 => Nothing to save and restored */
131 /* save_state = 1 => Only L1 and logic lost */
132 /* save_state = 2 => Only L2 lost */
133 /* save_state = 3 => L1, L2 and logic lost */
134 int save_state = 0, mpu_next_state;
135
136 if (!_omap_sram_idle)
137 return;
138
139 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
140 switch (mpu_next_state) {
141 case PWRDM_POWER_RET:
142 /* No need to save context */
143 save_state = 0;
144 break;
145 default:
146 /* Invalid state */
147 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
148 return;
149 }
fe617af7
PDS		 150 pwrdm_pre_transition();
151
8bd22949 152 omap2_gpio_prepare_for_retention();
4af4016c
KH		 153 omap_uart_prepare_idle(0);
154 omap_uart_prepare_idle(1);
155 omap_uart_prepare_idle(2);
8bd22949
KH		 156
157 _omap_sram_idle(NULL, save_state);
158 cpu_init();
159
4af4016c
KH		 160 omap_uart_resume_idle(2);
161 omap_uart_resume_idle(1);
162 omap_uart_resume_idle(0);
8bd22949 163 omap2_gpio_resume_after_retention();
fe617af7
PDS		 164
165 pwrdm_post_transition();
166
8bd22949
KH		 167}
168
169/*
170 * Check if functional clocks are enabled before entering
171 * sleep. This function could be behind CONFIG_PM_DEBUG
172 * when all drivers are configuring their sysconfig registers
173 * properly and using their clocks properly.
174 */
175static int omap3_fclks_active(void)
176{
177 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
178 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
179
180 fck_core1 = cm_read_mod_reg(CORE_MOD,
181 CM_FCLKEN1);
182 if (omap_rev() > OMAP3430_REV_ES1_0) {
183 fck_core3 = cm_read_mod_reg(CORE_MOD,
184 OMAP3430ES2_CM_FCLKEN3);
185 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
186 CM_FCLKEN);
187 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
188 CM_FCLKEN);
189 } else
190 fck_sgx = cm_read_mod_reg(GFX_MOD,
191 OMAP3430ES2_CM_FCLKEN3);
192 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
193 CM_FCLKEN);
194 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
195 CM_FCLKEN);
196 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
197 CM_FCLKEN);
4af4016c
KH		 198
199 /* Ignore UART clocks. These are handled by UART core (serial.c) */
200 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
201 fck_per &= ~OMAP3430_EN_UART3;
202
8bd22949
KH		 203 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
204 fck_cam | fck_per | fck_usbhost)
205 return 1;
206 return 0;
207}
208
209static int omap3_can_sleep(void)
210{
4af4016c
KH		 211 if (!omap_uart_can_sleep())
212 return 0;
8bd22949
KH		 213 if (omap3_fclks_active())
214 return 0;
215 return 1;
216}
217
218/* This sets pwrdm state (other than mpu & core. Currently only ON &
219 * RET are supported. Function is assuming that clkdm doesn't have
220 * hw_sup mode enabled. */
221static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
222{
223 u32 cur_state;
224 int sleep_switch = 0;
225 int ret = 0;
226
227 if (pwrdm == NULL || IS_ERR(pwrdm))
228 return -EINVAL;
229
230 while (!(pwrdm->pwrsts & (1 << state))) {
231 if (state == PWRDM_POWER_OFF)
232 return ret;
233 state--;
234 }
235
236 cur_state = pwrdm_read_next_pwrst(pwrdm);
237 if (cur_state == state)
238 return ret;
239
240 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
241 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
242 sleep_switch = 1;
243 pwrdm_wait_transition(pwrdm);
244 }
245
246 ret = pwrdm_set_next_pwrst(pwrdm, state);
247 if (ret) {
248 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
249 pwrdm->name);
250 goto err;
251 }
252
253 if (sleep_switch) {
254 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
255 pwrdm_wait_transition(pwrdm);
fe617af7 256 pwrdm_state_switch(pwrdm);
8bd22949
KH		 257 }
258
259err:
260 return ret;
261}
262
263static void omap3_pm_idle(void)
264{
265 local_irq_disable();
266 local_fiq_disable();
267
268 if (!omap3_can_sleep())
269 goto out;
270
271 if (omap_irq_pending())
272 goto out;
273
274 omap_sram_idle();
275
276out:
277 local_fiq_enable();
278 local_irq_enable();
279}
280
10f90ed2 281#ifdef CONFIG_SUSPEND
2466211e
TK		 282static suspend_state_t suspend_state;
283
8bd22949
KH		 284static int omap3_pm_prepare(void)
285{
286 disable_hlt();
287 return 0;
288}
289
290static int omap3_pm_suspend(void)
291{
292 struct power_state *pwrst;
293 int state, ret = 0;
294
295 /* Read current next_pwrsts */
296 list_for_each_entry(pwrst, &pwrst_list, node)
297 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
298 /* Set ones wanted by suspend */
299 list_for_each_entry(pwrst, &pwrst_list, node) {
300 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
301 goto restore;
302 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
303 goto restore;
304 }
305
4af4016c 306 omap_uart_prepare_suspend();
8bd22949
KH		 307 omap_sram_idle();
308
309restore:
310 /* Restore next_pwrsts */
311 list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949
KH		 312 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
313 if (state > pwrst->next_state) {
314 printk(KERN_INFO "Powerdomain (%s) didn't enter "
315 "target state %d\n",
316 pwrst->pwrdm->name, pwrst->next_state);
317 ret = -1;
318 }
6c5f8039 319 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949
KH		 320 }
321 if (ret)
322 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
323 else
324 printk(KERN_INFO "Successfully put all powerdomains "
325 "to target state\n");
326
327 return ret;
328}
329
2466211e 330static int omap3_pm_enter(suspend_state_t unused)
8bd22949
KH		 331{
332 int ret = 0;
333
2466211e 334 switch (suspend_state) {
8bd22949
KH		 335 case PM_SUSPEND_STANDBY:
336 case PM_SUSPEND_MEM:
337 ret = omap3_pm_suspend();
338 break;
339 default:
340 ret = -EINVAL;
341 }
342
343 return ret;
344}
345
346static void omap3_pm_finish(void)
347{
348 enable_hlt();
349}
350
2466211e
TK		 351/* Hooks to enable / disable UART interrupts during suspend */
352static int omap3_pm_begin(suspend_state_t state)
353{
354 suspend_state = state;
355 omap_uart_enable_irqs(0);
356 return 0;
357}
358
359static void omap3_pm_end(void)
360{
361 suspend_state = PM_SUSPEND_ON;
362 omap_uart_enable_irqs(1);
363 return;
364}
365
8bd22949 366static struct platform_suspend_ops omap_pm_ops = {
2466211e
TK		 367 .begin = omap3_pm_begin,
368 .end = omap3_pm_end,
8bd22949
KH		 369 .prepare = omap3_pm_prepare,
370 .enter = omap3_pm_enter,
371 .finish = omap3_pm_finish,
372 .valid = suspend_valid_only_mem,
373};
10f90ed2 374#endif /* CONFIG_SUSPEND */
8bd22949 375
1155e426
KH		 376
377/**
378 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
379 * retention
380 *
381 * In cases where IVA2 is activated by bootcode, it may prevent
382 * full-chip retention or off-mode because it is not idle. This
383 * function forces the IVA2 into idle state so it can go
384 * into retention/off and thus allow full-chip retention/off.
385 *
386 **/
387static void __init omap3_iva_idle(void)
388{
389 /* ensure IVA2 clock is disabled */
390 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
391
392 /* if no clock activity, nothing else to do */
393 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
394 OMAP3430_CLKACTIVITY_IVA2_MASK))
395 return;
396
397 /* Reset IVA2 */
398 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
399 OMAP3430_RST2_IVA2 |
400 OMAP3430_RST3_IVA2,
401 OMAP3430_IVA2_MOD, RM_RSTCTRL);
402
403 /* Enable IVA2 clock */
404 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
405 OMAP3430_IVA2_MOD, CM_FCLKEN);
406
407 /* Set IVA2 boot mode to 'idle' */
408 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
409 OMAP343X_CONTROL_IVA2_BOOTMOD);
410
411 /* Un-reset IVA2 */
412 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
413
414 /* Disable IVA2 clock */
415 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
416
417 /* Reset IVA2 */
418 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
419 OMAP3430_RST2_IVA2 |
420 OMAP3430_RST3_IVA2,
421 OMAP3430_IVA2_MOD, RM_RSTCTRL);
422}
423
8111b221 424static void __init omap3_d2d_idle(void)
8bd22949 425{
8111b221
KH		 426 u16 mask, padconf;
427
428 /* In a stand alone OMAP3430 where there is not a stacked
429 * modem for the D2D Idle Ack and D2D MStandby must be pulled
430 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
431 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
432 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
433 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
434 padconf |= mask;
435 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
436
437 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
438 padconf |= mask;
439 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
440
8bd22949
KH		 441 /* reset modem */
442 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
443 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
444 CORE_MOD, RM_RSTCTRL);
445 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
8111b221 446}
8bd22949 447
8111b221
KH		 448static void __init prcm_setup_regs(void)
449{
8bd22949
KH		 450 /* XXX Reset all wkdeps. This should be done when initializing
451 * powerdomains */
452 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
453 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
454 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
455 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
456 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
457 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
458 if (omap_rev() > OMAP3430_REV_ES1_0) {
459 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
460 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
461 } else
462 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
463
464 /*
465 * Enable interface clock autoidle for all modules.
466 * Note that in the long run this should be done by clockfw
467 */
468 cm_write_mod_reg(
8111b221 469 OMAP3430_AUTO_MODEM |
8bd22949
KH		 470 OMAP3430ES2_AUTO_MMC3 |
471 OMAP3430ES2_AUTO_ICR |
472 OMAP3430_AUTO_AES2 |
473 OMAP3430_AUTO_SHA12 |
474 OMAP3430_AUTO_DES2 |
475 OMAP3430_AUTO_MMC2 |
476 OMAP3430_AUTO_MMC1 |
477 OMAP3430_AUTO_MSPRO |
478 OMAP3430_AUTO_HDQ |
479 OMAP3430_AUTO_MCSPI4 |
480 OMAP3430_AUTO_MCSPI3 |
481 OMAP3430_AUTO_MCSPI2 |
482 OMAP3430_AUTO_MCSPI1 |
483 OMAP3430_AUTO_I2C3 |
484 OMAP3430_AUTO_I2C2 |
485 OMAP3430_AUTO_I2C1 |
486 OMAP3430_AUTO_UART2 |
487 OMAP3430_AUTO_UART1 |
488 OMAP3430_AUTO_GPT11 |
489 OMAP3430_AUTO_GPT10 |
490 OMAP3430_AUTO_MCBSP5 |
491 OMAP3430_AUTO_MCBSP1 |
492 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
493 OMAP3430_AUTO_MAILBOXES |
494 OMAP3430_AUTO_OMAPCTRL |
495 OMAP3430ES1_AUTO_FSHOSTUSB |
496 OMAP3430_AUTO_HSOTGUSB |
8111b221 497 OMAP3430_AUTO_SAD2D |
8bd22949
KH		 498 OMAP3430_AUTO_SSI,
499 CORE_MOD, CM_AUTOIDLE1);
500
501 cm_write_mod_reg(
502 OMAP3430_AUTO_PKA |
503 OMAP3430_AUTO_AES1 |
504 OMAP3430_AUTO_RNG |
505 OMAP3430_AUTO_SHA11 |
506 OMAP3430_AUTO_DES1,
507 CORE_MOD, CM_AUTOIDLE2);
508
509 if (omap_rev() > OMAP3430_REV_ES1_0) {
510 cm_write_mod_reg(
8111b221 511 OMAP3430_AUTO_MAD2D |
8bd22949
KH		 512 OMAP3430ES2_AUTO_USBTLL,
513 CORE_MOD, CM_AUTOIDLE3);
514 }
515
516 cm_write_mod_reg(
517 OMAP3430_AUTO_WDT2 |
518 OMAP3430_AUTO_WDT1 |
519 OMAP3430_AUTO_GPIO1 |
520 OMAP3430_AUTO_32KSYNC |
521 OMAP3430_AUTO_GPT12 |
522 OMAP3430_AUTO_GPT1 ,
523 WKUP_MOD, CM_AUTOIDLE);
524
525 cm_write_mod_reg(
526 OMAP3430_AUTO_DSS,
527 OMAP3430_DSS_MOD,
528 CM_AUTOIDLE);
529
530 cm_write_mod_reg(
531 OMAP3430_AUTO_CAM,
532 OMAP3430_CAM_MOD,
533 CM_AUTOIDLE);
534
535 cm_write_mod_reg(
536 OMAP3430_AUTO_GPIO6 |
537 OMAP3430_AUTO_GPIO5 |
538 OMAP3430_AUTO_GPIO4 |
539 OMAP3430_AUTO_GPIO3 |
540 OMAP3430_AUTO_GPIO2 |
541 OMAP3430_AUTO_WDT3 |
542 OMAP3430_AUTO_UART3 |
543 OMAP3430_AUTO_GPT9 |
544 OMAP3430_AUTO_GPT8 |
545 OMAP3430_AUTO_GPT7 |
546 OMAP3430_AUTO_GPT6 |
547 OMAP3430_AUTO_GPT5 |
548 OMAP3430_AUTO_GPT4 |
549 OMAP3430_AUTO_GPT3 |
550 OMAP3430_AUTO_GPT2 |
551 OMAP3430_AUTO_MCBSP4 |
552 OMAP3430_AUTO_MCBSP3 |
553 OMAP3430_AUTO_MCBSP2,
554 OMAP3430_PER_MOD,
555 CM_AUTOIDLE);
556
557 if (omap_rev() > OMAP3430_REV_ES1_0) {
558 cm_write_mod_reg(
559 OMAP3430ES2_AUTO_USBHOST,
560 OMAP3430ES2_USBHOST_MOD,
561 CM_AUTOIDLE);
562 }
563
564 /*
565 * Set all plls to autoidle. This is needed until autoidle is
566 * enabled by clockfw
567 */
568 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
569 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
570 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
571 MPU_MOD,
572 CM_AUTOIDLE2);
573 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
574 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
575 PLL_MOD,
576 CM_AUTOIDLE);
577 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
578 PLL_MOD,
579 CM_AUTOIDLE2);
580
581 /*
582 * Enable control of expternal oscillator through
583 * sys_clkreq. In the long run clock framework should
584 * take care of this.
585 */
586 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
587 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
588 OMAP3430_GR_MOD,
589 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
590
591 /* setup wakup source */
592 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
593 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
594 WKUP_MOD, PM_WKEN);
595 /* No need to write EN_IO, that is always enabled */
596 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
597 OMAP3430_EN_GPT12,
598 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
599 /* For some reason IO doesn't generate wakeup event even if
600 * it is selected to mpu wakeup goup */
601 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
602 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
1155e426 603
d3fd3290
KH		 604 /* Don't attach IVA interrupts */
605 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
606 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
607 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
608 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
609
b1340d17
KH		 610 /* Clear any pending 'reset' flags */
611 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
612 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
613 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
614 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
615 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
616 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
617 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
618
014c46db
KH		 619 /* Clear any pending PRCM interrupts */
620 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
621
040fed05
KH		 622 /* Don't attach IVA interrupts */
623 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
624 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
625 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
626 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
627
3a07ae30
KH		 628 /* Clear any pending 'reset' flags */
629 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
630 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
631 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
632 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
633 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
634 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
635 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
636
3a6667ac
KH		 637 /* Clear any pending PRCM interrupts */
638 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
639
1155e426 640 omap3_iva_idle();
8111b221 641 omap3_d2d_idle();
8bd22949
KH		 642}
643
68d4778c
TK		 644int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
645{
646 struct power_state *pwrst;
647
648 list_for_each_entry(pwrst, &pwrst_list, node) {
649 if (pwrst->pwrdm == pwrdm)
650 return pwrst->next_state;
651 }
652 return -EINVAL;
653}
654
655int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
656{
657 struct power_state *pwrst;
658
659 list_for_each_entry(pwrst, &pwrst_list, node) {
660 if (pwrst->pwrdm == pwrdm) {
661 pwrst->next_state = state;
662 return 0;
663 }
664 }
665 return -EINVAL;
666}
667
a23456e9 668static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
8bd22949
KH		 669{
670 struct power_state *pwrst;
671
672 if (!pwrdm->pwrsts)
673 return 0;
674
d3d381c6 675 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949
KH		 676 if (!pwrst)
677 return -ENOMEM;
678 pwrst->pwrdm = pwrdm;
679 pwrst->next_state = PWRDM_POWER_RET;
680 list_add(&pwrst->node, &pwrst_list);
681
682 if (pwrdm_has_hdwr_sar(pwrdm))
683 pwrdm_enable_hdwr_sar(pwrdm);
684
685 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
686}
687
688/*
689 * Enable hw supervised mode for all clockdomains if it's
690 * supported. Initiate sleep transition for other clockdomains, if
691 * they are not used
692 */
a23456e9 693static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
8bd22949
KH		 694{
695 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
696 omap2_clkdm_allow_idle(clkdm);
697 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
698 atomic_read(&clkdm->usecount) == 0)
699 omap2_clkdm_sleep(clkdm);
700 return 0;
701}
702
7cc515f7 703static int __init omap3_pm_init(void)
8bd22949
KH		 704{
705 struct power_state *pwrst, *tmp;
706 int ret;
707
708 if (!cpu_is_omap34xx())
709 return -ENODEV;
710
711 printk(KERN_ERR "Power Management for TI OMAP3.\n");
712
713 /* XXX prcm_setup_regs needs to be before enabling hw
714 * supervised mode for powerdomains */
715 prcm_setup_regs();
716
717 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
718 (irq_handler_t)prcm_interrupt_handler,
719 IRQF_DISABLED, "prcm", NULL);
720 if (ret) {
721 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
722 INT_34XX_PRCM_MPU_IRQ);
723 goto err1;
724 }
725
a23456e9 726 ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949
KH		 727 if (ret) {
728 printk(KERN_ERR "Failed to setup powerdomains\n");
729 goto err2;
730 }
731
a23456e9 732 (void) clkdm_for_each(clkdms_setup, NULL);
8bd22949
KH		 733
734 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
735 if (mpu_pwrdm == NULL) {
736 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
737 goto err2;
738 }
739
740 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
741 omap34xx_cpu_suspend_sz);
742
10f90ed2 743#ifdef CONFIG_SUSPEND
8bd22949 744 suspend_set_ops(&omap_pm_ops);
10f90ed2 745#endif /* CONFIG_SUSPEND */
8bd22949
KH		 746
747 pm_idle = omap3_pm_idle;
748
749err1:
750 return ret;
751err2:
752 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
753 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
754 list_del(&pwrst->node);
755 kfree(pwrst);
756 }
757 return ret;
758}
759
760late_initcall(omap3_pm_init);
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