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OMAP4: hwmod: Add initial data for OMAP4430 ES1 & ES2
[net-next-2.6.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
1dbae815
TL		 20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
fced80c7 23#include <linux/io.h>
2f135eaf 24#include <linux/clk.h>
91773a00 25#include <linux/omapfb.h>
1dbae815 26
120db2cb 27#include <asm/tlb.h>
120db2cb
TL		 28
29#include <asm/mach/map.h>
30
ce491cf8
TL		 31#include <plat/sram.h>
32#include <plat/sdrc.h>
33#include <plat/gpmc.h>
34#include <plat/serial.h>
646e3ed1 35
e80a9729 36#include "clock2xxx.h"
657ebfad 37#include "clock3xxx.h"
e80a9729 38#include "clock44xx.h"
1dbae815 39
ce491cf8
TL		 40#include <plat/omap-pm.h>
41#include <plat/powerdomain.h>
9717100f 42#include "powerdomains.h"
1dbae815 43
ce491cf8 44#include <plat/clockdomain.h>
801954d3 45#include "clockdomains.h"
6f88e9bc 46
ce491cf8 47#include <plat/omap_hwmod.h>
02bfc030 48
1dbae815
TL		 49/*
50 * The machine specific code may provide the extra mapping besides the
51 * default mapping provided here.
52 */
cc26b3b0 53
088ef950 54#ifdef CONFIG_ARCH_OMAP2
cc26b3b0 55static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 56 {
57 .virtual = L3_24XX_VIRT,
58 .pfn = __phys_to_pfn(L3_24XX_PHYS),
59 .length = L3_24XX_SIZE,
60 .type = MT_DEVICE
61 },
09f21ed4 62 {
cc26b3b0
SMK		 63 .virtual = L4_24XX_VIRT,
64 .pfn = __phys_to_pfn(L4_24XX_PHYS),
65 .length = L4_24XX_SIZE,
66 .type = MT_DEVICE
09f21ed4 67 },
cc26b3b0
SMK		 68};
69
70#ifdef CONFIG_ARCH_OMAP2420
71static struct map_desc omap242x_io_desc[] __initdata = {
72 {
7adb9987
PW		 73 .virtual = DSP_MEM_2420_VIRT,
74 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
75 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 76 .type = MT_DEVICE
77 },
78 {
7adb9987
PW		 79 .virtual = DSP_IPI_2420_VIRT,
80 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
81 .length = DSP_IPI_2420_SIZE,
cc26b3b0 82 .type = MT_DEVICE
09f21ed4 83 },
cc26b3b0 84 {
7adb9987
PW		 85 .virtual = DSP_MMU_2420_VIRT,
86 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
87 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 88 .type = MT_DEVICE
89 },
90};
91
92#endif
93
72d0f1c3 94#ifdef CONFIG_ARCH_OMAP2430
cc26b3b0 95static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 96 {
97 .virtual = L4_WK_243X_VIRT,
98 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
99 .length = L4_WK_243X_SIZE,
100 .type = MT_DEVICE
101 },
102 {
103 .virtual = OMAP243X_GPMC_VIRT,
104 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
105 .length = OMAP243X_GPMC_SIZE,
106 .type = MT_DEVICE
107 },
cc26b3b0
SMK		 108 {
109 .virtual = OMAP243X_SDRC_VIRT,
110 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
111 .length = OMAP243X_SDRC_SIZE,
112 .type = MT_DEVICE
113 },
114 {
115 .virtual = OMAP243X_SMS_VIRT,
116 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
117 .length = OMAP243X_SMS_SIZE,
118 .type = MT_DEVICE
119 },
120};
72d0f1c3 121#endif
72d0f1c3 122#endif
cc26b3b0 123
a8eb7ca0 124#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 125static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 126 {
cc26b3b0
SMK		 127 .virtual = L3_34XX_VIRT,
128 .pfn = __phys_to_pfn(L3_34XX_PHYS),
129 .length = L3_34XX_SIZE,
c40fae95
TL		 130 .type = MT_DEVICE
131 },
132 {
cc26b3b0
SMK		 133 .virtual = L4_34XX_VIRT,
134 .pfn = __phys_to_pfn(L4_34XX_PHYS),
135 .length = L4_34XX_SIZE,
c40fae95
TL		 136 .type = MT_DEVICE
137 },
cc26b3b0
SMK		 138 {
139 .virtual = OMAP34XX_GPMC_VIRT,
140 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
141 .length = OMAP34XX_GPMC_SIZE,
1dbae815 142 .type = MT_DEVICE
cc26b3b0
SMK		 143 },
144 {
145 .virtual = OMAP343X_SMS_VIRT,
146 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
147 .length = OMAP343X_SMS_SIZE,
148 .type = MT_DEVICE
149 },
150 {
151 .virtual = OMAP343X_SDRC_VIRT,
152 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
153 .length = OMAP343X_SDRC_SIZE,
1dbae815 154 .type = MT_DEVICE
cc26b3b0
SMK		 155 },
156 {
157 .virtual = L4_PER_34XX_VIRT,
158 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
159 .length = L4_PER_34XX_SIZE,
160 .type = MT_DEVICE
161 },
162 {
163 .virtual = L4_EMU_34XX_VIRT,
164 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
165 .length = L4_EMU_34XX_SIZE,
166 .type = MT_DEVICE
167 },
a4f57b81
TL		 168#if defined(CONFIG_DEBUG_LL) && \
169 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
170 {
171 .virtual = ZOOM_UART_VIRT,
172 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
173 .length = SZ_1M,
174 .type = MT_DEVICE
175 },
176#endif
1dbae815 177};
cc26b3b0 178#endif
44169075
SS		 179#ifdef CONFIG_ARCH_OMAP4
180static struct map_desc omap44xx_io_desc[] __initdata = {
181 {
182 .virtual = L3_44XX_VIRT,
183 .pfn = __phys_to_pfn(L3_44XX_PHYS),
184 .length = L3_44XX_SIZE,
185 .type = MT_DEVICE,
186 },
187 {
188 .virtual = L4_44XX_VIRT,
189 .pfn = __phys_to_pfn(L4_44XX_PHYS),
190 .length = L4_44XX_SIZE,
191 .type = MT_DEVICE,
192 },
44169075
SS		 193 {
194 .virtual = OMAP44XX_GPMC_VIRT,
195 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
196 .length = OMAP44XX_GPMC_SIZE,
197 .type = MT_DEVICE,
198 },
f5d2d659
SS		 199 {
200 .virtual = OMAP44XX_EMIF1_VIRT,
201 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
202 .length = OMAP44XX_EMIF1_SIZE,
203 .type = MT_DEVICE,
204 },
205 {
206 .virtual = OMAP44XX_EMIF2_VIRT,
207 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
208 .length = OMAP44XX_EMIF2_SIZE,
209 .type = MT_DEVICE,
210 },
211 {
212 .virtual = OMAP44XX_DMM_VIRT,
213 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
214 .length = OMAP44XX_DMM_SIZE,
215 .type = MT_DEVICE,
216 },
44169075
SS		 217 {
218 .virtual = L4_PER_44XX_VIRT,
219 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
220 .length = L4_PER_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_EMU_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
226 .length = L4_EMU_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
229};
230#endif
1dbae815 231
6fbd55d0
TL		 232static void __init _omap2_map_common_io(void)
233{
234 /* Normally devicemaps_init() would flush caches and tlb after
235 * mdesc->map_io(), but we must also do it here because of the CPU
236 * revision check below.
237 */
238 local_flush_tlb_all();
239 flush_cache_all();
240
241 omap2_check_revision();
242 omap_sram_init();
6fbd55d0
TL		 243}
244
245#ifdef CONFIG_ARCH_OMAP2420
8185e468 246void __init omap242x_map_common_io(void)
1dbae815 247{
cc26b3b0
SMK		 248 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
249 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0
TL		 250 _omap2_map_common_io();
251}
cc26b3b0
SMK		 252#endif
253
6fbd55d0 254#ifdef CONFIG_ARCH_OMAP2430
8185e468 255void __init omap243x_map_common_io(void)
6fbd55d0 256{
cc26b3b0
SMK		 257 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
258 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0
TL		 259 _omap2_map_common_io();
260}
cc26b3b0
SMK		 261#endif
262
a8eb7ca0 263#ifdef CONFIG_ARCH_OMAP3
8185e468 264void __init omap34xx_map_common_io(void)
6fbd55d0 265{
cc26b3b0 266 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0
TL		 267 _omap2_map_common_io();
268}
cc26b3b0 269#endif
120db2cb 270
6fbd55d0 271#ifdef CONFIG_ARCH_OMAP4
8185e468 272void __init omap44xx_map_common_io(void)
6fbd55d0 273{
44169075 274 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
6fbd55d0 275 _omap2_map_common_io();
120db2cb 276}
6fbd55d0 277#endif
120db2cb 278
2f135eaf
PW		 279/*
280 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
281 *
282 * Sets the CORE DPLL3 M2 divider to the same value that it's at
283 * currently. This has the effect of setting the SDRC SDRAM AC timing
284 * registers to the values currently defined by the kernel. Currently
285 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
286 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
287 * or passes along the return value of clk_set_rate().
288 */
289static int __init _omap2_init_reprogram_sdrc(void)
290{
291 struct clk *dpll3_m2_ck;
292 int v = -EINVAL;
293 long rate;
294
295 if (!cpu_is_omap34xx())
296 return 0;
297
298 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
299 if (!dpll3_m2_ck)
300 return -EINVAL;
301
302 rate = clk_get_rate(dpll3_m2_ck);
303 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
304 v = clk_set_rate(dpll3_m2_ck, rate);
305 if (v)
306 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
307
308 clk_put(dpll3_m2_ck);
309
310 return v;
311}
312
58cda884
JP		 313void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
314 struct omap_sdrc_params *sdrc_cs1)
120db2cb 315{
97d60162
PW		 316 u8 skip_setup_idle = 0;
317
3a759f09 318 pwrdm_init(powerdomains_omap);
55ed9694 319 clkdm_init(clockdomains_omap, clkdm_autodeps);
7359154e
PW		 320 if (cpu_is_omap242x())
321 omap2420_hwmod_init();
322 else if (cpu_is_omap243x())
323 omap2430_hwmod_init();
324 else if (cpu_is_omap34xx())
325 omap3xxx_hwmod_init();
55d2cb08
BC		 326 else if (cpu_is_omap44xx())
327 omap44xx_hwmod_init();
328
7359154e 329 /* The OPP tables have to be registered before a clk init */
c0407a96 330 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
e80a9729 331
81b34fbe
PW		 332 if (cpu_is_omap2420())
333 omap2420_clk_init();
334 else if (cpu_is_omap2430())
335 omap2430_clk_init();
e80a9729
PW		 336 else if (cpu_is_omap34xx())
337 omap3xxx_clk_init();
338 else if (cpu_is_omap44xx())
339 omap4xxx_clk_init();
340 else
341 pr_err("Could not init clock framework - unknown CPU\n");
342
b3c6df3a 343 omap_serial_early_init();
97d60162
PW		 344
345#ifndef CONFIG_PM_RUNTIME
346 skip_setup_idle = 1;
347#endif
55d2cb08 348 omap_hwmod_late_init(skip_setup_idle);
aa4b1f6e
KH		 349 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
350 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
351 _omap2_init_reprogram_sdrc();
352 }
4bbbc1ad 353 gpmc_init();
1dbae815 354}
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