[net-next-2.6.git] / arch / arm / mach-mx3 / mach-mx31_3ds.c

/*
 *  Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/platform_device.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/board-mx31_3ds.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/mxc_nand.h>
#include <mach/spi.h>
#include "devices.h"

/*!
 * @file mx31_3ds.c
 *
 * @brief This file contains the board-specific initialization routines.
 *
 * @ingroup System
 */

static int mx31_3ds_pins[] = {
	/* UART1 */
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
	/* SPI 1 */
	MX31_PIN_CSPI2_SCLK__SCLK,
	MX31_PIN_CSPI2_MOSI__MOSI,
	MX31_PIN_CSPI2_MISO__MISO,
	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI2_SS0__SS0,
	MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
	/* MC13783 IRQ */
	IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
};

/* Regulators */
static struct regulator_init_data pwgtx_init = {
	.constraints = {
		.boot_on	= 1,
		.always_on	= 1,
	},
};

static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
	{
		.id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
		.init_data = &pwgtx_init,
	}, {
		.id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
		.init_data = &pwgtx_init,
	},
};

/* MC13783 */
static struct mc13783_platform_data mc13783_pdata __initdata = {
	.regulators = mx31_3ds_regulators,
	.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
	.flags  = MC13783_USE_REGULATOR,
};

/* SPI */
static int spi1_internal_chipselect[] = {
	MXC_SPI_CS(0),
	MXC_SPI_CS(2),
};

static struct spi_imx_master spi1_pdata = {
	.chipselect	= spi1_internal_chipselect,
	.num_chipselect	= ARRAY_SIZE(spi1_internal_chipselect),
};

static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
	{
		.modalias	= "mc13783",
		.max_speed_hz	= 1000000,
		.bus_num	= 1,
		.chip_select	= 1, /* SS2 */
		.platform_data	= &mc13783_pdata,
		.irq		= IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
		.mode = SPI_CS_HIGH,
	},
};

/*
 * NAND Flash
 */
static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
	.width		= 1,
	.hw_ecc		= 1,
#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
	.flash_bbt	= 1,
#endif
};

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

/*
 * Support for the SMSC9217 on the Debug board.
 */

static struct smsc911x_platform_config smsc911x_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct resource smsc911x_resources[] = {
	{
		.start		= LAN9217_BASE_ADDR,
		.end		= LAN9217_BASE_ADDR + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= EXPIO_INT_ENET,
		.end		= EXPIO_INT_ENET,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device smsc911x_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_config,
	},
};

/*
 * Routines for the CPLD on the debug board. It contains a CPLD handling
 * LEDs, switches, interrupts for Ethernet.
 */

static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
{
	uint32_t imr_val;
	uint32_t int_valid;
	uint32_t expio_irq;

	imr_val = __raw_readw(CPLD_INT_MASK_REG);
	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;

	expio_irq = MXC_EXP_IO_BASE;
	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
		if ((int_valid & 1) == 0)
			continue;
		generic_handle_irq(expio_irq);
	}
}

/*
 * Disable an expio pin's interrupt by setting the bit in the imr.
 * @param irq           an expio virtual irq number
 */
static void expio_mask_irq(uint32_t irq)
{
	uint16_t reg;
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* mask the interrupt */
	reg = __raw_readw(CPLD_INT_MASK_REG);
	reg |= 1 << expio;
	__raw_writew(reg, CPLD_INT_MASK_REG);
}

/*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 * @param irq           an expanded io virtual irq number
 */
static void expio_ack_irq(uint32_t irq)
{
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* clear the interrupt status */
	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
	__raw_writew(0, CPLD_INT_RESET_REG);
	/* mask the interrupt */
	expio_mask_irq(irq);
}

/*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
 * @param irq           a expio virtual irq number
 */
static void expio_unmask_irq(uint32_t irq)
{
	uint16_t reg;
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* unmask the interrupt */
	reg = __raw_readw(CPLD_INT_MASK_REG);
	reg &= ~(1 << expio);
	__raw_writew(reg, CPLD_INT_MASK_REG);
}

static struct irq_chip expio_irq_chip = {
	.ack = expio_ack_irq,
	.mask = expio_mask_irq,
	.unmask = expio_unmask_irq,
};

static int __init mx31_3ds_init_expio(void)
{
	int i;
	int ret;

	/* Check if there's a debug board connected */
	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
		/* No Debug board found */
		return -ENODEV;
	}

	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
		__raw_readw(CPLD_CODE_VER_REG));

	/*
	 * Configure INT line as GPIO input
	 */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
	if (ret)
		pr_warning("could not get LAN irq gpio\n");
	else
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));

	/* Disable the interrupts and clear the status */
	__raw_writew(0, CPLD_INT_MASK_REG);
	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
	__raw_writew(0, CPLD_INT_RESET_REG);
	__raw_writew(0x1F, CPLD_INT_MASK_REG);
	for (i = MXC_EXP_IO_BASE;
	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	     i++) {
		set_irq_chip(i, &expio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);

	return 0;
}

/*
 * This structure defines the MX31 memory map.
 */
static struct map_desc mx31_3ds_io_desc[] __initdata = {
	{
		.virtual = MX31_CS5_BASE_ADDR_VIRT,
		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
		.length = MX31_CS5_SIZE,
		.type = MT_DEVICE,
	},
};

/*
 * Set up static virtual mappings.
 */
static void __init mx31_3ds_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
}

/*!
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
				      "mx31_3ds");

	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);

	mxc_register_device(&mxc_spi_device1, &spi1_pdata);
	spi_register_board_info(mx31_3ds_spi_devs,
						ARRAY_SIZE(mx31_3ds_spi_devs));

	if (!mx31_3ds_init_expio())
		platform_device_register(&smsc911x_device);
}

static void __init mx31_3ds_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31_3ds_timer = {
	.init	= mx31_3ds_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_MX31_3DS data structure.
 */
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.phys_io	= MX31_AIPS1_BASE_ADDR,
	.io_pg_offst	= (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31_3ds_map_io,
	.init_irq       = mx31_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &mx31_3ds_timer,
MACHINE_END
Commit	Line	Data
1553a1ec FE	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#include <linux/types.h>
	20	#include <linux/init.h>
	21	#include <linux/clk.h>
	22	#include <linux/irq.h>
135cad36	23	#include <linux/gpio.h>
2b0c3677 ML	24	#include <linux/smsc911x.h>
2b0c3677 ML	25	#include <linux/platform_device.h>
ae7a3f13 AP	26	#include <linux/mfd/mc13783.h>
	27	#include <linux/spi/spi.h>
	28	#include <linux/regulator/machine.h>
1553a1ec FE	29
	30	#include <mach/hardware.h>
	31	#include <asm/mach-types.h>
	32	#include <asm/mach/arch.h>
	33	#include <asm/mach/time.h>
	34	#include <asm/memory.h>
	35	#include <asm/mach/map.h>
	36	#include <mach/common.h>
11a332ad	37	#include <mach/board-mx31_3ds.h>
1553a1ec FE	38	#include <mach/imx-uart.h>
1553a1ec FE	39	#include <mach/iomux-mx3.h>
a1b67b95	40	#include <mach/mxc_nand.h>
a1ac4424	41	#include <mach/spi.h>
1553a1ec FE	42	#include "devices.h"
	43
	44	/*!
11a332ad	45	* @file mx31_3ds.c
1553a1ec FE	46	*
	47	* @brief This file contains the board-specific initialization routines.
	48	*
	49	* @ingroup System
	50	*/
	51
11a332ad	52	static int mx31_3ds_pins[] = {
153fa1d8	53	/* UART1 */
63d97667 VL	54	MX31_PIN_CTS1__CTS1,
	55	MX31_PIN_RTS1__RTS1,
	56	MX31_PIN_TXD1__TXD1,
135cad36 ML	57	MX31_PIN_RXD1__RXD1,
135cad36 ML	58	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
a1ac4424 AP	59	/* SPI 1 */
	60	MX31_PIN_CSPI2_SCLK__SCLK,
	61	MX31_PIN_CSPI2_MOSI__MOSI,
	62	MX31_PIN_CSPI2_MISO__MISO,
	63	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	64	MX31_PIN_CSPI2_SS0__SS0,
	65	MX31_PIN_CSPI2_SS2__SS2, /CS for MC13783 /
ae7a3f13 AP	66	/* MC13783 IRQ */
	67	IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
	68	};
	69
	70	/* Regulators */
	71	static struct regulator_init_data pwgtx_init = {
	72	.constraints = {
	73	.boot_on = 1,
	74	.always_on = 1,
	75	},
	76	};
	77
	78	static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
	79	{
	80	.id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
	81	.init_data = &pwgtx_init,
	82	}, {
	83	.id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
	84	.init_data = &pwgtx_init,
	85	},
	86	};
	87
	88	/* MC13783 */
	89	static struct mc13783_platform_data mc13783_pdata __initdata = {
	90	.regulators = mx31_3ds_regulators,
	91	.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
	92	.flags = MC13783_USE_REGULATOR,
a1ac4424 AP	93	};
	94
	95	/* SPI */
	96	static int spi1_internal_chipselect[] = {
	97	MXC_SPI_CS(0),
	98	MXC_SPI_CS(2),
	99	};
	100
	101	static struct spi_imx_master spi1_pdata = {
	102	.chipselect = spi1_internal_chipselect,
	103	.num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667 VL	104	};
63d97667 VL	105
ae7a3f13 AP	106	static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
	107	{
	108	.modalias = "mc13783",
	109	.max_speed_hz = 1000000,
	110	.bus_num = 1,
	111	.chip_select = 1, /* SS2 */
	112	.platform_data = &mc13783_pdata,
	113	.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	114	.mode = SPI_CS_HIGH,
	115	},
	116	};
	117
a1b67b95 AP	118	/*
	119	* NAND Flash
	120	*/
	121	static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
	122	.width = 1,
	123	.hw_ecc = 1,
	124	#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
	125	.flash_bbt = 1,
	126	#endif
	127	};
	128
153fa1d8 ML	129	static struct imxuart_platform_data uart_pdata = {
	130	.flags = IMXUART_HAVE_RTSCTS,
	131	};
1553a1ec	132
2b0c3677 ML	133	/*
	134	* Support for the SMSC9217 on the Debug board.
	135	*/
	136
	137	static struct smsc911x_platform_config smsc911x_config = {
	138	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	139	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	140	.flags = SMSC911X_USE_16BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	141	.phy_interface = PHY_INTERFACE_MODE_MII,
	142	};
	143
	144	static struct resource smsc911x_resources[] = {
	145	{
	146	.start = LAN9217_BASE_ADDR,
	147	.end = LAN9217_BASE_ADDR + 0xff,
	148	.flags = IORESOURCE_MEM,
	149	}, {
	150	.start = EXPIO_INT_ENET,
	151	.end = EXPIO_INT_ENET,
	152	.flags = IORESOURCE_IRQ,
	153	},
	154	};
	155
	156	static struct platform_device smsc911x_device = {
	157	.name = "smsc911x",
	158	.id = -1,
	159	.num_resources = ARRAY_SIZE(smsc911x_resources),
	160	.resource = smsc911x_resources,
	161	.dev = {
	162	.platform_data = &smsc911x_config,
	163	},
	164	};
	165
135cad36 ML	166	/*
	167	* Routines for the CPLD on the debug board. It contains a CPLD handling
	168	* LEDs, switches, interrupts for Ethernet.
	169	*/
	170
11a332ad	171	static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
135cad36 ML	172	{
	173	uint32_t imr_val;
	174	uint32_t int_valid;
	175	uint32_t expio_irq;
	176
	177	imr_val = __raw_readw(CPLD_INT_MASK_REG);
	178	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
	179
	180	expio_irq = MXC_EXP_IO_BASE;
	181	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
	182	if ((int_valid & 1) == 0)
	183	continue;
	184	generic_handle_irq(expio_irq);
	185	}
	186	}
	187
	188	/*
	189	* Disable an expio pin's interrupt by setting the bit in the imr.
	190	* @param irq an expio virtual irq number
	191	*/
	192	static void expio_mask_irq(uint32_t irq)
	193	{
	194	uint16_t reg;
	195	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	196
	197	/* mask the interrupt */
	198	reg = __raw_readw(CPLD_INT_MASK_REG);
	199	reg \|= 1 << expio;
	200	__raw_writew(reg, CPLD_INT_MASK_REG);
	201	}
	202
	203	/*
	204	* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
	205	* @param irq an expanded io virtual irq number
	206	*/
	207	static void expio_ack_irq(uint32_t irq)
	208	{
	209	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	210
	211	/* clear the interrupt status */
	212	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
	213	__raw_writew(0, CPLD_INT_RESET_REG);
	214	/* mask the interrupt */
	215	expio_mask_irq(irq);
	216	}
	217
	218	/*
	219	* Enable a expio pin's interrupt by clearing the bit in the imr.
	220	* @param irq a expio virtual irq number
	221	*/
	222	static void expio_unmask_irq(uint32_t irq)
	223	{
	224	uint16_t reg;
	225	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	226
	227	/* unmask the interrupt */
	228	reg = __raw_readw(CPLD_INT_MASK_REG);
	229	reg &= ~(1 << expio);
	230	__raw_writew(reg, CPLD_INT_MASK_REG);
	231	}
	232
	233	static struct irq_chip expio_irq_chip = {
	234	.ack = expio_ack_irq,
	235	.mask = expio_mask_irq,
236	.unmask = expio_unmask_irq,
237	};
238
11a332ad	239	static int __init mx31_3ds_init_expio(void)
135cad36 ML	240	{
	241	int i;
	242	int ret;
	243
	244	/* Check if there's a debug board connected */
	245	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) \|\|
	246	(__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) \|\|
	247	(__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
	248	/* No Debug board found */
	249	return -ENODEV;
	250	}
	251
11a332ad	252	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
135cad36 ML	253	__raw_readw(CPLD_CODE_VER_REG));
	254
	255	/*
	256	* Configure INT line as GPIO input
	257	*/
	258	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
	259	if (ret)
	260	pr_warning("could not get LAN irq gpio\n");
	261	else
	262	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	263
	264	/* Disable the interrupts and clear the status */
	265	__raw_writew(0, CPLD_INT_MASK_REG);
	266	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
	267	__raw_writew(0, CPLD_INT_RESET_REG);
	268	__raw_writew(0x1F, CPLD_INT_MASK_REG);
	269	for (i = MXC_EXP_IO_BASE;
	270	i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	271	i++) {
	272	set_irq_chip(i, &expio_irq_chip);
	273	set_irq_handler(i, handle_level_irq);
	274	set_irq_flags(i, IRQF_VALID);
	275	}
	276	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
11a332ad	277	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
135cad36 ML	278
	279	return 0;
	280	}
	281
	282	/*
	283	* This structure defines the MX31 memory map.
	284	*/
11a332ad	285	static struct map_desc mx31_3ds_io_desc[] __initdata = {
135cad36	286	{
f568dd7f UKK	287	.virtual = MX31_CS5_BASE_ADDR_VIRT,
	288	.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
	289	.length = MX31_CS5_SIZE,
135cad36 ML	290	.type = MT_DEVICE,
	291	},
	292	};
	293
	294	/*
	295	* Set up static virtual mappings.
	296	*/
11a332ad	297	static void __init mx31_3ds_map_io(void)
135cad36 ML	298	{
135cad36 ML	299	mx31_map_io();
11a332ad	300	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
135cad36 ML	301	}
135cad36 ML	302
1553a1ec FE	303	/*!
	304	* Board specific initialization.
	305	*/
	306	static void __init mxc_board_init(void)
	307	{
11a332ad AP	308	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
11a332ad AP	309	"mx31_3ds");
153fa1d8 ML	310
153fa1d8 ML	311	mxc_register_device(&mxc_uart_device0, &uart_pdata);
a1b67b95	312	mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
ae7a3f13	313
a1ac4424	314	mxc_register_device(&mxc_spi_device1, &spi1_pdata);
ae7a3f13 AP	315	spi_register_board_info(mx31_3ds_spi_devs,
ae7a3f13 AP	316	ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36	317
11a332ad	318	if (!mx31_3ds_init_expio())
2b0c3677	319	platform_device_register(&smsc911x_device);
1553a1ec FE	320	}
1553a1ec FE	321
11a332ad	322	static void __init mx31_3ds_timer_init(void)
1553a1ec	323	{
30c730f8	324	mx31_clocks_init(26000000);
1553a1ec FE	325	}
1553a1ec FE	326
11a332ad AP	327	static struct sys_timer mx31_3ds_timer = {
11a332ad AP	328	.init = mx31_3ds_timer_init,
1553a1ec FE	329	};
	330
	331	/*
	332	* The following uses standard kernel macros defined in arch.h in order to
11a332ad	333	* initialize __mach_desc_MX31_3DS data structure.
1553a1ec FE	334	*/
	335	MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
	336	/* Maintainer: Freescale Semiconductor, Inc. */
f568dd7f	337	.phys_io = MX31_AIPS1_BASE_ADDR,
321ed164	338	.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
34101237	339	.boot_params = MX3x_PHYS_OFFSET + 0x100,
11a332ad	340	.map_io = mx31_3ds_map_io,
c5aa0ad0	341	.init_irq = mx31_init_irq,
1553a1ec	342	.init_machine = mxc_board_init,
11a332ad	343	.timer = &mx31_3ds_timer,
1553a1ec	344	MACHINE_END