[net-next-2.6.git] / arch / arm / mach-mx3 / mach-mx31_3ds.c

/*
 *  Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/platform_device.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/board-mx31_3ds.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/mxc_nand.h>
#include <mach/spi.h>
#include "devices.h"

/*!
 * @file mx31_3ds.c
 *
 * @brief This file contains the board-specific initialization routines.
 *
 * @ingroup System
 */

static int mx31_3ds_pins[] = {
	/* UART1 */
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
	/* SPI 1 */
	MX31_PIN_CSPI2_SCLK__SCLK,
	MX31_PIN_CSPI2_MOSI__MOSI,
	MX31_PIN_CSPI2_MISO__MISO,
	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI2_SS0__SS0,
	MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
};

/* SPI */
static int spi1_internal_chipselect[] = {
	MXC_SPI_CS(0),
	MXC_SPI_CS(2),
};

static struct spi_imx_master spi1_pdata = {
	.chipselect	= spi1_internal_chipselect,
	.num_chipselect	= ARRAY_SIZE(spi1_internal_chipselect),
};

/*
 * NAND Flash
 */
static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
	.width		= 1,
	.hw_ecc		= 1,
#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
	.flash_bbt	= 1,
#endif
};

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

/*
 * Support for the SMSC9217 on the Debug board.
 */

static struct smsc911x_platform_config smsc911x_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct resource smsc911x_resources[] = {
	{
		.start		= LAN9217_BASE_ADDR,
		.end		= LAN9217_BASE_ADDR + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= EXPIO_INT_ENET,
		.end		= EXPIO_INT_ENET,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device smsc911x_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_config,
	},
};

/*
 * Routines for the CPLD on the debug board. It contains a CPLD handling
 * LEDs, switches, interrupts for Ethernet.
 */

static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
{
	uint32_t imr_val;
	uint32_t int_valid;
	uint32_t expio_irq;

	imr_val = __raw_readw(CPLD_INT_MASK_REG);
	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;

	expio_irq = MXC_EXP_IO_BASE;
	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
		if ((int_valid & 1) == 0)
			continue;
		generic_handle_irq(expio_irq);
	}
}

/*
 * Disable an expio pin's interrupt by setting the bit in the imr.
 * @param irq           an expio virtual irq number
 */
static void expio_mask_irq(uint32_t irq)
{
	uint16_t reg;
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* mask the interrupt */
	reg = __raw_readw(CPLD_INT_MASK_REG);
	reg |= 1 << expio;
	__raw_writew(reg, CPLD_INT_MASK_REG);
}

/*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 * @param irq           an expanded io virtual irq number
 */
static void expio_ack_irq(uint32_t irq)
{
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* clear the interrupt status */
	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
	__raw_writew(0, CPLD_INT_RESET_REG);
	/* mask the interrupt */
	expio_mask_irq(irq);
}

/*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
 * @param irq           a expio virtual irq number
 */
static void expio_unmask_irq(uint32_t irq)
{
	uint16_t reg;
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* unmask the interrupt */
	reg = __raw_readw(CPLD_INT_MASK_REG);
	reg &= ~(1 << expio);
	__raw_writew(reg, CPLD_INT_MASK_REG);
}

static struct irq_chip expio_irq_chip = {
	.ack = expio_ack_irq,
	.mask = expio_mask_irq,
	.unmask = expio_unmask_irq,
};

static int __init mx31_3ds_init_expio(void)
{
	int i;
	int ret;

	/* Check if there's a debug board connected */
	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
		/* No Debug board found */
		return -ENODEV;
	}

	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
		__raw_readw(CPLD_CODE_VER_REG));

	/*
	 * Configure INT line as GPIO input
	 */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
	if (ret)
		pr_warning("could not get LAN irq gpio\n");
	else
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));

	/* Disable the interrupts and clear the status */
	__raw_writew(0, CPLD_INT_MASK_REG);
	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
	__raw_writew(0, CPLD_INT_RESET_REG);
	__raw_writew(0x1F, CPLD_INT_MASK_REG);
	for (i = MXC_EXP_IO_BASE;
	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	     i++) {
		set_irq_chip(i, &expio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);

	return 0;
}

/*
 * This structure defines the MX31 memory map.
 */
static struct map_desc mx31_3ds_io_desc[] __initdata = {
	{
		.virtual = MX31_CS5_BASE_ADDR_VIRT,
		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
		.length = MX31_CS5_SIZE,
		.type = MT_DEVICE,
	},
};

/*
 * Set up static virtual mappings.
 */
static void __init mx31_3ds_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
}

/*!
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
				      "mx31_3ds");

	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
	mxc_register_device(&mxc_spi_device1, &spi1_pdata);

	if (!mx31_3ds_init_expio())
		platform_device_register(&smsc911x_device);
}

static void __init mx31_3ds_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31_3ds_timer = {
	.init	= mx31_3ds_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_MX31_3DS data structure.
 */
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.phys_io	= MX31_AIPS1_BASE_ADDR,
	.io_pg_offst	= (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31_3ds_map_io,
	.init_irq       = mx31_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &mx31_3ds_timer,
MACHINE_END
Commit	Line	Data
1553a1ec FE	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#include <linux/types.h>
	20	#include <linux/init.h>
	21	#include <linux/clk.h>
	22	#include <linux/irq.h>
135cad36	23	#include <linux/gpio.h>
2b0c3677 ML	24	#include <linux/smsc911x.h>
2b0c3677 ML	25	#include <linux/platform_device.h>
1553a1ec FE	26
	27	#include <mach/hardware.h>
	28	#include <asm/mach-types.h>
	29	#include <asm/mach/arch.h>
	30	#include <asm/mach/time.h>
	31	#include <asm/memory.h>
	32	#include <asm/mach/map.h>
	33	#include <mach/common.h>
11a332ad	34	#include <mach/board-mx31_3ds.h>
1553a1ec FE	35	#include <mach/imx-uart.h>
1553a1ec FE	36	#include <mach/iomux-mx3.h>
a1b67b95	37	#include <mach/mxc_nand.h>
a1ac4424	38	#include <mach/spi.h>
1553a1ec FE	39	#include "devices.h"
	40
	41	/*!
11a332ad	42	* @file mx31_3ds.c
1553a1ec FE	43	*
	44	* @brief This file contains the board-specific initialization routines.
	45	*
	46	* @ingroup System
	47	*/
	48
11a332ad	49	static int mx31_3ds_pins[] = {
153fa1d8	50	/* UART1 */
63d97667 VL	51	MX31_PIN_CTS1__CTS1,
	52	MX31_PIN_RTS1__RTS1,
	53	MX31_PIN_TXD1__TXD1,
135cad36 ML	54	MX31_PIN_RXD1__RXD1,
135cad36 ML	55	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
a1ac4424 AP	56	/* SPI 1 */
	57	MX31_PIN_CSPI2_SCLK__SCLK,
	58	MX31_PIN_CSPI2_MOSI__MOSI,
	59	MX31_PIN_CSPI2_MISO__MISO,
	60	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	61	MX31_PIN_CSPI2_SS0__SS0,
	62	MX31_PIN_CSPI2_SS2__SS2, /CS for MC13783 /
	63	};
	64
	65	/* SPI */
	66	static int spi1_internal_chipselect[] = {
	67	MXC_SPI_CS(0),
	68	MXC_SPI_CS(2),
	69	};
	70
	71	static struct spi_imx_master spi1_pdata = {
	72	.chipselect = spi1_internal_chipselect,
	73	.num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667 VL	74	};
63d97667 VL	75
a1b67b95 AP	76	/*
	77	* NAND Flash
	78	*/
	79	static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
	80	.width = 1,
	81	.hw_ecc = 1,
	82	#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
	83	.flash_bbt = 1,
	84	#endif
	85	};
	86
153fa1d8 ML	87	static struct imxuart_platform_data uart_pdata = {
	88	.flags = IMXUART_HAVE_RTSCTS,
	89	};
1553a1ec	90
2b0c3677 ML	91	/*
	92	* Support for the SMSC9217 on the Debug board.
	93	*/
	94
	95	static struct smsc911x_platform_config smsc911x_config = {
	96	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	97	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	98	.flags = SMSC911X_USE_16BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	99	.phy_interface = PHY_INTERFACE_MODE_MII,
	100	};
	101
	102	static struct resource smsc911x_resources[] = {
	103	{
	104	.start = LAN9217_BASE_ADDR,
	105	.end = LAN9217_BASE_ADDR + 0xff,
	106	.flags = IORESOURCE_MEM,
	107	}, {
	108	.start = EXPIO_INT_ENET,
	109	.end = EXPIO_INT_ENET,
	110	.flags = IORESOURCE_IRQ,
	111	},
	112	};
	113
	114	static struct platform_device smsc911x_device = {
	115	.name = "smsc911x",
	116	.id = -1,
	117	.num_resources = ARRAY_SIZE(smsc911x_resources),
	118	.resource = smsc911x_resources,
	119	.dev = {
	120	.platform_data = &smsc911x_config,
	121	},
	122	};
	123
135cad36 ML	124	/*
	125	* Routines for the CPLD on the debug board. It contains a CPLD handling
	126	* LEDs, switches, interrupts for Ethernet.
	127	*/
	128
11a332ad	129	static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
135cad36 ML	130	{
	131	uint32_t imr_val;
	132	uint32_t int_valid;
	133	uint32_t expio_irq;
	134
	135	imr_val = __raw_readw(CPLD_INT_MASK_REG);
	136	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
	137
	138	expio_irq = MXC_EXP_IO_BASE;
	139	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
	140	if ((int_valid & 1) == 0)
	141	continue;
	142	generic_handle_irq(expio_irq);
	143	}
	144	}
	145
	146	/*
	147	* Disable an expio pin's interrupt by setting the bit in the imr.
	148	* @param irq an expio virtual irq number
	149	*/
	150	static void expio_mask_irq(uint32_t irq)
	151	{
	152	uint16_t reg;
	153	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	154
	155	/* mask the interrupt */
	156	reg = __raw_readw(CPLD_INT_MASK_REG);
	157	reg \|= 1 << expio;
	158	__raw_writew(reg, CPLD_INT_MASK_REG);
	159	}
	160
	161	/*
	162	* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
	163	* @param irq an expanded io virtual irq number
	164	*/
	165	static void expio_ack_irq(uint32_t irq)
	166	{
	167	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	168
	169	/* clear the interrupt status */
	170	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
	171	__raw_writew(0, CPLD_INT_RESET_REG);
	172	/* mask the interrupt */
	173	expio_mask_irq(irq);
	174	}
	175
	176	/*
	177	* Enable a expio pin's interrupt by clearing the bit in the imr.
	178	* @param irq a expio virtual irq number
	179	*/
	180	static void expio_unmask_irq(uint32_t irq)
	181	{
	182	uint16_t reg;
	183	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	184
	185	/* unmask the interrupt */
	186	reg = __raw_readw(CPLD_INT_MASK_REG);
	187	reg &= ~(1 << expio);
	188	__raw_writew(reg, CPLD_INT_MASK_REG);
	189	}
	190
	191	static struct irq_chip expio_irq_chip = {
	192	.ack = expio_ack_irq,
	193	.mask = expio_mask_irq,
194	.unmask = expio_unmask_irq,
195	};
196
11a332ad	197	static int __init mx31_3ds_init_expio(void)
135cad36 ML	198	{
	199	int i;
	200	int ret;
	201
	202	/* Check if there's a debug board connected */
	203	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) \|\|
	204	(__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) \|\|
	205	(__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
	206	/* No Debug board found */
	207	return -ENODEV;
	208	}
	209
11a332ad	210	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
135cad36 ML	211	__raw_readw(CPLD_CODE_VER_REG));
	212
	213	/*
	214	* Configure INT line as GPIO input
	215	*/
	216	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
	217	if (ret)
	218	pr_warning("could not get LAN irq gpio\n");
	219	else
	220	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	221
	222	/* Disable the interrupts and clear the status */
	223	__raw_writew(0, CPLD_INT_MASK_REG);
	224	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
	225	__raw_writew(0, CPLD_INT_RESET_REG);
	226	__raw_writew(0x1F, CPLD_INT_MASK_REG);
	227	for (i = MXC_EXP_IO_BASE;
	228	i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	229	i++) {
	230	set_irq_chip(i, &expio_irq_chip);
	231	set_irq_handler(i, handle_level_irq);
	232	set_irq_flags(i, IRQF_VALID);
	233	}
	234	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
11a332ad	235	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
135cad36 ML	236
	237	return 0;
	238	}
	239
	240	/*
	241	* This structure defines the MX31 memory map.
	242	*/
11a332ad	243	static struct map_desc mx31_3ds_io_desc[] __initdata = {
135cad36	244	{
f568dd7f UKK	245	.virtual = MX31_CS5_BASE_ADDR_VIRT,
	246	.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
	247	.length = MX31_CS5_SIZE,
135cad36 ML	248	.type = MT_DEVICE,
	249	},
	250	};
	251
	252	/*
	253	* Set up static virtual mappings.
	254	*/
11a332ad	255	static void __init mx31_3ds_map_io(void)
135cad36 ML	256	{
135cad36 ML	257	mx31_map_io();
11a332ad	258	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
135cad36 ML	259	}
135cad36 ML	260
1553a1ec FE	261	/*!
	262	* Board specific initialization.
	263	*/
	264	static void __init mxc_board_init(void)
	265	{
11a332ad AP	266	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
11a332ad AP	267	"mx31_3ds");
153fa1d8 ML	268
153fa1d8 ML	269	mxc_register_device(&mxc_uart_device0, &uart_pdata);
a1b67b95	270	mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
a1ac4424	271	mxc_register_device(&mxc_spi_device1, &spi1_pdata);
135cad36	272
11a332ad	273	if (!mx31_3ds_init_expio())
2b0c3677	274	platform_device_register(&smsc911x_device);
1553a1ec FE	275	}
1553a1ec FE	276
11a332ad	277	static void __init mx31_3ds_timer_init(void)
1553a1ec	278	{
30c730f8	279	mx31_clocks_init(26000000);
1553a1ec FE	280	}
1553a1ec FE	281
11a332ad AP	282	static struct sys_timer mx31_3ds_timer = {
11a332ad AP	283	.init = mx31_3ds_timer_init,
1553a1ec FE	284	};
	285
	286	/*
	287	* The following uses standard kernel macros defined in arch.h in order to
11a332ad	288	* initialize __mach_desc_MX31_3DS data structure.
1553a1ec FE	289	*/
	290	MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
	291	/* Maintainer: Freescale Semiconductor, Inc. */
f568dd7f	292	.phys_io = MX31_AIPS1_BASE_ADDR,
321ed164	293	.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
34101237	294	.boot_params = MX3x_PHYS_OFFSET + 0x100,
11a332ad	295	.map_io = mx31_3ds_map_io,
c5aa0ad0	296	.init_irq = mx31_init_irq,
1553a1ec	297	.init_machine = mxc_board_init,
11a332ad	298	.timer = &mx31_3ds_timer,
1553a1ec	299	MACHINE_END