[net-next-2.6.git] / arch / arm / mach-mx3 / mach-mx31_3ds.c

/*
 *  Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/delay.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
#include <linux/fsl_devices.h>
#include <linux/input/matrix_keypad.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/3ds_debugboard.h>

#include "devices-imx31.h"
#include "devices.h"

/* Definitions for components on the Debug board */

/* Base address of CPLD controller on the Debug board */
#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)

/* LAN9217 ethernet base address */
#define LAN9217_BASE_ADDR		MX3x_CS5_BASE_ADDR

/* CPLD config and interrupt base address */
#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)

/* status, interrupt */
#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
/* magic word for debug CPLD */
#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
/* CPLD code version */
#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
/* magic word for debug CPLD */
#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)

/* CPLD IRQ line for external uart, external ethernet etc */
#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)

#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)

#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)

#define MXC_MAX_EXP_IO_LINES	16

/*
 * This file contains the board-specific initialization routines.
 */

static int mx31_3ds_pins[] = {
	/* UART1 */
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
	/* SPI 1 */
	MX31_PIN_CSPI2_SCLK__SCLK,
	MX31_PIN_CSPI2_MOSI__MOSI,
	MX31_PIN_CSPI2_MISO__MISO,
	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI2_SS0__SS0,
	MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
	/* MC13783 IRQ */
	IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
	/* USB OTG reset */
	IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
	/* USB OTG */
	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
	MX31_PIN_USBOTG_STP__USBOTG_STP,
	/*Keyboard*/
	MX31_PIN_KEY_ROW0_KEY_ROW0,
	MX31_PIN_KEY_ROW1_KEY_ROW1,
	MX31_PIN_KEY_ROW2_KEY_ROW2,
	MX31_PIN_KEY_COL0_KEY_COL0,
	MX31_PIN_KEY_COL1_KEY_COL1,
	MX31_PIN_KEY_COL2_KEY_COL2,
	MX31_PIN_KEY_COL3_KEY_COL3,
};

/*
 * Matrix keyboard
 */

static const uint32_t mx31_3ds_keymap[] = {
	KEY(0, 0, KEY_UP),
	KEY(0, 1, KEY_DOWN),
	KEY(1, 0, KEY_RIGHT),
	KEY(1, 1, KEY_LEFT),
	KEY(1, 2, KEY_ENTER),
	KEY(2, 0, KEY_F6),
	KEY(2, 1, KEY_F8),
	KEY(2, 2, KEY_F9),
	KEY(2, 3, KEY_F10),
};

static struct matrix_keymap_data mx31_3ds_keymap_data = {
	.keymap		= mx31_3ds_keymap,
	.keymap_size	= ARRAY_SIZE(mx31_3ds_keymap),
};

/* Regulators */
static struct regulator_init_data pwgtx_init = {
	.constraints = {
		.boot_on	= 1,
		.always_on	= 1,
	},
};

static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
	{
		.id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
		.init_data = &pwgtx_init,
	}, {
		.id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
		.init_data = &pwgtx_init,
	},
};

/* MC13783 */
static struct mc13783_platform_data mc13783_pdata __initdata = {
	.regulators = mx31_3ds_regulators,
	.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
	.flags  = MC13783_USE_REGULATOR,
};

/* SPI */
static int spi1_internal_chipselect[] = {
	MXC_SPI_CS(0),
	MXC_SPI_CS(2),
};

static const struct spi_imx_master spi1_pdata __initconst = {
	.chipselect	= spi1_internal_chipselect,
	.num_chipselect	= ARRAY_SIZE(spi1_internal_chipselect),
};

static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
	{
		.modalias	= "mc13783",
		.max_speed_hz	= 1000000,
		.bus_num	= 1,
		.chip_select	= 1, /* SS2 */
		.platform_data	= &mc13783_pdata,
		.irq		= IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
		.mode = SPI_CS_HIGH,
	},
};

/*
 * NAND Flash
 */
static const struct mxc_nand_platform_data
mx31_3ds_nand_board_info __initconst = {
	.width		= 1,
	.hw_ecc		= 1,
#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
	.flash_bbt	= 1,
#endif
};

/*
 * USB OTG
 */

#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
		     PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)

#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)

static int mx31_3ds_usbotg_init(void)
{
	int err;

	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);

	err = gpio_request(USBOTG_RST_B, "otgusb-reset");
	if (err) {
		pr_err("Failed to request the USB OTG reset gpio\n");
		return err;
	}

	err = gpio_direction_output(USBOTG_RST_B, 0);
	if (err) {
		pr_err("Failed to drive the USB OTG reset gpio\n");
		goto usbotg_free_reset;
	}

	mdelay(1);
	gpio_set_value(USBOTG_RST_B, 1);
	return 0;

usbotg_free_reset:
	gpio_free(USBOTG_RST_B);
	return err;
}

static struct fsl_usb2_platform_data usbotg_pdata = {
	.operating_mode = FSL_USB2_DR_DEVICE,
	.phy_mode	= FSL_USB2_PHY_ULPI,
};

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

/*
 * Set up static virtual mappings.
 */
static void __init mx31_3ds_map_io(void)
{
	mx31_map_io();
}

/*!
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
				      "mx31_3ds");

	imx31_add_imx_uart0(&uart_pdata);
	imx31_add_mxc_nand(&mx31_3ds_nand_board_info);

	imx31_add_spi_imx0(&spi1_pdata);
	spi_register_board_info(mx31_3ds_spi_devs,
						ARRAY_SIZE(mx31_3ds_spi_devs));

	mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);

	mx31_3ds_usbotg_init();
	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);

	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
		printk(KERN_WARNING "Init of the debugboard failed, all "
				    "devices on the board are unusable.\n");
}

static void __init mx31_3ds_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31_3ds_timer = {
	.init	= mx31_3ds_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_MX31_3DS data structure.
 */
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31_3ds_map_io,
	.init_irq       = mx31_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &mx31_3ds_timer,
MACHINE_END
Commit	Line	Data
1553a1ec FE	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
1553a1ec FE	13	*/
1553a1ec FE	14
a2ef4562	15	#include <linux/delay.h>
1553a1ec FE	16	#include <linux/types.h>
	17	#include <linux/init.h>
	18	#include <linux/clk.h>
	19	#include <linux/irq.h>
135cad36	20	#include <linux/gpio.h>
2b0c3677	21	#include <linux/platform_device.h>
ae7a3f13 AP	22	#include <linux/mfd/mc13783.h>
	23	#include <linux/spi/spi.h>
	24	#include <linux/regulator/machine.h>
a2ef4562	25	#include <linux/fsl_devices.h>
54c1f636	26	#include <linux/input/matrix_keypad.h>
1553a1ec FE	27
	28	#include <mach/hardware.h>
	29	#include <asm/mach-types.h>
	30	#include <asm/mach/arch.h>
	31	#include <asm/mach/time.h>
	32	#include <asm/memory.h>
	33	#include <asm/mach/map.h>
	34	#include <mach/common.h>
1553a1ec	35	#include <mach/iomux-mx3.h>
c5d38f08	36	#include <mach/3ds_debugboard.h>
a2ceeef5 UKK	37
a2ceeef5 UKK	38	#include "devices-imx31.h"
1553a1ec FE	39	#include "devices.h"
1553a1ec FE	40
b396dc45 UKK	41	/* Definitions for components on the Debug board */
	42
	43	/* Base address of CPLD controller on the Debug board */
	44	#define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
	45
	46	/* LAN9217 ethernet base address */
	47	#define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR
	48
	49	/* CPLD config and interrupt base address */
	50	#define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
	51
	52	/* status, interrupt */
	53	#define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
	54	#define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
	55	#define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
	56	/* magic word for debug CPLD */
	57	#define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
	58	#define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
	59	/* CPLD code version */
	60	#define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
	61	/* magic word for debug CPLD */
	62	#define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
	63
	64	/* CPLD IRQ line for external uart, external ethernet etc */
	65	#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
	66
	67	#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
	68	#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
	69
	70	#define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
	71
	72	#define MXC_MAX_EXP_IO_LINES 16
	73
	74	/*
	75	* This file contains the board-specific initialization routines.
1553a1ec FE	76	*/
1553a1ec FE	77
11a332ad	78	static int mx31_3ds_pins[] = {
153fa1d8	79	/* UART1 */
63d97667 VL	80	MX31_PIN_CTS1__CTS1,
	81	MX31_PIN_RTS1__RTS1,
	82	MX31_PIN_TXD1__TXD1,
135cad36 ML	83	MX31_PIN_RXD1__RXD1,
135cad36 ML	84	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
a1ac4424 AP	85	/* SPI 1 */
	86	MX31_PIN_CSPI2_SCLK__SCLK,
	87	MX31_PIN_CSPI2_MOSI__MOSI,
	88	MX31_PIN_CSPI2_MISO__MISO,
	89	MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
	90	MX31_PIN_CSPI2_SS0__SS0,
	91	MX31_PIN_CSPI2_SS2__SS2, /CS for MC13783 /
ae7a3f13 AP	92	/* MC13783 IRQ */
ae7a3f13 AP	93	IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562 ML	94	/* USB OTG reset */
	95	IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
	96	/* USB OTG */
	97	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
	98	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
	99	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
	100	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
	101	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
	102	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
	103	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
	104	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
	105	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
	106	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
	107	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
	108	MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636 AP	109	/Keyboard/
	110	MX31_PIN_KEY_ROW0_KEY_ROW0,
	111	MX31_PIN_KEY_ROW1_KEY_ROW1,
	112	MX31_PIN_KEY_ROW2_KEY_ROW2,
	113	MX31_PIN_KEY_COL0_KEY_COL0,
	114	MX31_PIN_KEY_COL1_KEY_COL1,
	115	MX31_PIN_KEY_COL2_KEY_COL2,
	116	MX31_PIN_KEY_COL3_KEY_COL3,
	117	};
	118
	119	/*
	120	* Matrix keyboard
	121	*/
	122
	123	static const uint32_t mx31_3ds_keymap[] = {
	124	KEY(0, 0, KEY_UP),
	125	KEY(0, 1, KEY_DOWN),
	126	KEY(1, 0, KEY_RIGHT),
	127	KEY(1, 1, KEY_LEFT),
	128	KEY(1, 2, KEY_ENTER),
	129	KEY(2, 0, KEY_F6),
	130	KEY(2, 1, KEY_F8),
	131	KEY(2, 2, KEY_F9),
	132	KEY(2, 3, KEY_F10),
	133	};
	134
	135	static struct matrix_keymap_data mx31_3ds_keymap_data = {
	136	.keymap = mx31_3ds_keymap,
	137	.keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13 AP	138	};
	139
	140	/* Regulators */
	141	static struct regulator_init_data pwgtx_init = {
	142	.constraints = {
	143	.boot_on = 1,
	144	.always_on = 1,
	145	},
	146	};
	147
	148	static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
	149	{
	150	.id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
	151	.init_data = &pwgtx_init,
	152	}, {
	153	.id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
	154	.init_data = &pwgtx_init,
	155	},
	156	};
	157
	158	/* MC13783 */
	159	static struct mc13783_platform_data mc13783_pdata __initdata = {
	160	.regulators = mx31_3ds_regulators,
	161	.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
	162	.flags = MC13783_USE_REGULATOR,
a1ac4424 AP	163	};
	164
	165	/* SPI */
	166	static int spi1_internal_chipselect[] = {
	167	MXC_SPI_CS(0),
	168	MXC_SPI_CS(2),
	169	};
	170
06606ff1	171	static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424 AP	172	.chipselect = spi1_internal_chipselect,
a1ac4424 AP	173	.num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667 VL	174	};
63d97667 VL	175
ae7a3f13 AP	176	static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
	177	{
	178	.modalias = "mc13783",
	179	.max_speed_hz = 1000000,
	180	.bus_num = 1,
	181	.chip_select = 1, /* SS2 */
	182	.platform_data = &mc13783_pdata,
	183	.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	184	.mode = SPI_CS_HIGH,
	185	},
	186	};
	187
a1b67b95 AP	188	/*
	189	* NAND Flash
	190	*/
a2ceeef5 UKK	191	static const struct mxc_nand_platform_data
a2ceeef5 UKK	192	mx31_3ds_nand_board_info __initconst = {
a1b67b95 AP	193	.width = 1,
	194	.hw_ecc = 1,
	195	#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
	196	.flash_bbt = 1,
	197	#endif
	198	};
	199
a2ef4562 ML	200	/*
	201	* USB OTG
	202	*/
	203
	204	#define USB_PAD_CFG (PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS_CMOS \| \
	205	PAD_CTL_ODE_CMOS \| PAD_CTL_100K_PU)
	206
	207	#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
	208
41f63475	209	static int mx31_3ds_usbotg_init(void)
a2ef4562	210	{
41f63475 FE	211	int err;
41f63475 FE	212
a2ef4562 ML	213	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
	214	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
	215	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
	216	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
	217	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
	218	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
	219	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
	220	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
	221	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
	222	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
	223	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
	224	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
	225
41f63475 FE	226	err = gpio_request(USBOTG_RST_B, "otgusb-reset");
	227	if (err) {
	228	pr_err("Failed to request the USB OTG reset gpio\n");
	229	return err;
	230	}
	231
	232	err = gpio_direction_output(USBOTG_RST_B, 0);
	233	if (err) {
	234	pr_err("Failed to drive the USB OTG reset gpio\n");
	235	goto usbotg_free_reset;
	236	}
	237
a2ef4562 ML	238	mdelay(1);
a2ef4562 ML	239	gpio_set_value(USBOTG_RST_B, 1);
41f63475 FE	240	return 0;
	241
	242	usbotg_free_reset:
	243	gpio_free(USBOTG_RST_B);
	244	return err;
a2ef4562 ML	245	}
	246
	247	static struct fsl_usb2_platform_data usbotg_pdata = {
	248	.operating_mode = FSL_USB2_DR_DEVICE,
	249	.phy_mode = FSL_USB2_PHY_ULPI,
	250	};
	251
16cf5c41	252	static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8 ML	253	.flags = IMXUART_HAVE_RTSCTS,
153fa1d8 ML	254	};
1553a1ec	255
135cad36 ML	256	/*
	257	* Set up static virtual mappings.
	258	*/
11a332ad	259	static void __init mx31_3ds_map_io(void)
135cad36 ML	260	{
135cad36 ML	261	mx31_map_io();
135cad36 ML	262	}
135cad36 ML	263
1553a1ec FE	264	/*!
	265	* Board specific initialization.
	266	*/
	267	static void __init mxc_board_init(void)
	268	{
11a332ad AP	269	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
11a332ad AP	270	"mx31_3ds");
153fa1d8	271
16cf5c41	272	imx31_add_imx_uart0(&uart_pdata);
a2ceeef5	273	imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13	274
06606ff1	275	imx31_add_spi_imx0(&spi1_pdata);
ae7a3f13 AP	276	spi_register_board_info(mx31_3ds_spi_devs,
ae7a3f13 AP	277	ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36	278
54c1f636 AP	279	mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
54c1f636 AP	280
a2ef4562 ML	281	mx31_3ds_usbotg_init();
	282	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
	283
c5d38f08 JW	284	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
	285	printk(KERN_WARNING "Init of the debugboard failed, all "
	286	"devices on the board are unusable.\n");
1553a1ec FE	287	}
1553a1ec FE	288
11a332ad	289	static void __init mx31_3ds_timer_init(void)
1553a1ec	290	{
30c730f8	291	mx31_clocks_init(26000000);
1553a1ec FE	292	}
1553a1ec FE	293
11a332ad AP	294	static struct sys_timer mx31_3ds_timer = {
11a332ad AP	295	.init = mx31_3ds_timer_init,
1553a1ec FE	296	};
	297
	298	/*
	299	* The following uses standard kernel macros defined in arch.h in order to
11a332ad	300	* initialize __mach_desc_MX31_3DS data structure.
1553a1ec FE	301	*/
	302	MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
	303	/* Maintainer: Freescale Semiconductor, Inc. */
34101237	304	.boot_params = MX3x_PHYS_OFFSET + 0x100,
11a332ad	305	.map_io = mx31_3ds_map_io,
c5aa0ad0	306	.init_irq = mx31_init_irq,
1553a1ec	307	.init_machine = mxc_board_init,
11a332ad	308	.timer = &mx31_3ds_timer,
1553a1ec	309	MACHINE_END