[net-next-2.6.git] / arch / arm / mach-mx3 / devices.c

/*
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
 * Boston, MA  02110-1301, USA.
 */

#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/common.h>
#include <mach/mx3_camera.h>

#include "devices.h"

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	{
		.chip.label = "gpio-0",
		.base = IO_ADDRESS(GPIO1_BASE_ADDR),
		.irq = MXC_INT_GPIO1,
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	}, {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO2_BASE_ADDR),
		.irq = MXC_INT_GPIO2,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	}, {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO3_BASE_ADDR),
		.irq = MXC_INT_GPIO3,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}
};

int __init imx3x_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
	{
		.start = MX31_MMC_SDHC1_BASE_ADDR,
		.end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX31_INT_MMC_SDHC1,
		.end = MX31_INT_MMC_SDHC1,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource mxcsdhc1_resources[] = {
	{
		.start = MX31_MMC_SDHC2_BASE_ADDR,
		.end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX31_INT_MMC_SDHC2,
		.end = MX31_INT_MMC_SDHC2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxcsdhc_device0 = {
	.name = "mxc-mmc",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	.resource = mxcsdhc0_resources,
};

struct platform_device mxcsdhc_device1 = {
	.name = "mxc-mmc",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	.resource = mxcsdhc1_resources,
};

static struct resource rnga_resources[] = {
	{
		.start = RNGA_BASE_ADDR,
		.end = RNGA_BASE_ADDR + 0x28,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_rnga_device = {
	.name = "mxc_rnga",
	.id = -1,
	.num_resources = 1,
	.resource = rnga_resources,
};
#endif /* CONFIG_ARCH_MX31 */

/* i.MX31 Image Processing Unit */

/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
	{
		.start = IPU_CTRL_BASE_ADDR,
		.end = IPU_CTRL_BASE_ADDR + 0x5F,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IPU_CTRL_BASE_ADDR + 0x88,
		.end = IPU_CTRL_BASE_ADDR + 0xB3,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_IPU_SYN,
		.end = MXC_INT_IPU_SYN,
		.flags = IORESOURCE_IRQ,
	}, {
		.start = MXC_INT_IPU_ERR,
		.end = MXC_INT_IPU_ERR,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mx3_ipu = {
	.name = "ipu-core",
	.id = -1,
	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	.resource = mx3_ipu_rsrc,
};

static struct resource fb_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0xB4,
		.end	= IPU_CTRL_BASE_ADDR + 0x1BF,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_fb = {
	.name		= "mx3_sdc_fb",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(fb_resources),
	.resource	= fb_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
       },
};

static struct resource camera_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0x60,
		.end	= IPU_CTRL_BASE_ADDR + 0x87,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_camera = {
	.name		= "mx3-camera",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(camera_resources),
	.resource	= camera_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

static struct resource otg_resources[] = {
	{
		.start	= MX31_OTG_BASE_ADDR,
		.end	= MX31_OTG_BASE_ADDR + 0x1ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_USB3,
		.end	= MXC_INT_USB3,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = DMA_BIT_MASK(32);

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = ~(u32)0;

static struct resource mxc_usbh1_resources[] = {
	{
		.start = MX31_OTG_BASE_ADDR + 0x200,
		.end = MX31_OTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB1,
		.end = MXC_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = ~(u32)0;

static struct resource mxc_usbh2_resources[] = {
	{
		.start = MX31_OTG_BASE_ADDR + 0x400,
		.end = MX31_OTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB2,
		.end = MXC_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};

static struct resource imx_wdt_resources[] = {
	{
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device imx_wdt_device0 = {
	.name           = "imx2-wdt",
	.id             = 0,
	.num_resources  = ARRAY_SIZE(imx_wdt_resources),
	.resource       = imx_wdt_resources,
};

static struct resource imx_rtc_resources[] = {
	{
		.start  = MX31_RTC_BASE_ADDR,
		.end    = MX31_RTC_BASE_ADDR + 0x3fff,
		.flags  = IORESOURCE_MEM,
	},
	{
		.start  = MX31_INT_RTC,
		.flags  = IORESOURCE_IRQ,
	},
};

struct platform_device imx_rtc_device0 = {
	.name           = "mxc_rtc",
	.id             = -1,
	.num_resources  = ARRAY_SIZE(imx_rtc_resources),
	.resource       = imx_rtc_resources,
};

static struct resource imx_kpp_resources[] = {
	{
		.start	= MX3x_KPP_BASE_ADDR,
		.end	= MX3x_KPP_BASE_ADDR + 0xf,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MX3x_INT_KPP,
		.end	= MX3x_INT_KPP,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device imx_kpp_device = {
	.name = "imx-keypad",
	.id = -1,
	.num_resources = ARRAY_SIZE(imx_kpp_resources),
	.resource = imx_kpp_resources,
};

static int __init mx3_devices_init(void)
{
#if defined(CONFIG_ARCH_MX31)
	if (cpu_is_mx31()) {
		imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
		imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
		mxc_register_device(&mxc_rnga_device, NULL);
	}
#endif
#if defined(CONFIG_ARCH_MX35)
	if (cpu_is_mx35()) {
		otg_resources[0].start = MX35_OTG_BASE_ADDR;
		otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
		otg_resources[1].start = MXC_INT_USBOTG;
		otg_resources[1].end = MXC_INT_USBOTG;
		mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
		mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
		mxc_usbh1_resources[1].start = MXC_INT_USBHS;
		mxc_usbh1_resources[1].end = MXC_INT_USBHS;
		imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
		imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
	}
#endif

	return 0;
}

subsys_initcall(mx3_devices_init);
Commit	Line	Data
e3d13ff4 SH	1	/*
	2	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor,
	17	* Boston, MA 02110-1301, USA.
	18	*/
	19
eb05bbeb	20	#include <linux/dma-mapping.h>
e3d13ff4 SH	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/serial.h>
07bd1a6c	24	#include <linux/gpio.h>
a09e64fb	25	#include <mach/hardware.h>
80b02c17	26	#include <mach/irqs.h>
45001e92	27	#include <mach/common.h>
9c70e227	28	#include <mach/mx3_camera.h>
e3d13ff4	29
87bbb197 SH	30	#include "devices.h"
87bbb197 SH	31
07bd1a6c JB	32	/* GPIO port description */
07bd1a6c JB	33	static struct mxc_gpio_port imx_gpio_ports[] = {
3f4f54b4	34	{
07bd1a6c JB	35	.chip.label = "gpio-0",
	36	.base = IO_ADDRESS(GPIO1_BASE_ADDR),
	37	.irq = MXC_INT_GPIO1,
9d631b83	38	.virtual_irq_start = MXC_GPIO_IRQ_START,
3f4f54b4	39	}, {
07bd1a6c JB	40	.chip.label = "gpio-1",
	41	.base = IO_ADDRESS(GPIO2_BASE_ADDR),
	42	.irq = MXC_INT_GPIO2,
9d631b83	43	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
3f4f54b4	44	}, {
07bd1a6c JB	45	.chip.label = "gpio-2",
	46	.base = IO_ADDRESS(GPIO3_BASE_ADDR),
	47	.irq = MXC_INT_GPIO3,
9d631b83	48	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
07bd1a6c JB	49	}
	50	};
	51
9a763bfb	52	int __init imx3x_register_gpios(void)
07bd1a6c JB	53	{
	54	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	55	}
a8405929 SH	56
	57	static struct resource mxc_w1_master_resources[] = {
	58	{
	59	.start = OWIRE_BASE_ADDR,
	60	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	61	.flags = IORESOURCE_MEM,
	62	},
	63	};
	64
	65	struct platform_device mxc_w1_master_device = {
	66	.name = "mxc_w1",
	67	.id = 0,
	68	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	69	.resource = mxc_w1_master_resources,
	70	};
cb96cf1a	71
2adc1d65 SH	72	#ifdef CONFIG_ARCH_MX31
	73	static struct resource mxcsdhc0_resources[] = {
	74	{
662a74b4 UKK	75	.start = MX31_MMC_SDHC1_BASE_ADDR,
662a74b4 UKK	76	.end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
2adc1d65 SH	77	.flags = IORESOURCE_MEM,
2adc1d65 SH	78	}, {
662a74b4 UKK	79	.start = MX31_INT_MMC_SDHC1,
662a74b4 UKK	80	.end = MX31_INT_MMC_SDHC1,
2adc1d65 SH	81	.flags = IORESOURCE_IRQ,
	82	},
	83	};
	84
	85	static struct resource mxcsdhc1_resources[] = {
	86	{
662a74b4 UKK	87	.start = MX31_MMC_SDHC2_BASE_ADDR,
662a74b4 UKK	88	.end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
2adc1d65 SH	89	.flags = IORESOURCE_MEM,
2adc1d65 SH	90	}, {
662a74b4 UKK	91	.start = MX31_INT_MMC_SDHC2,
662a74b4 UKK	92	.end = MX31_INT_MMC_SDHC2,
2adc1d65 SH	93	.flags = IORESOURCE_IRQ,
	94	},
	95	};
	96
	97	struct platform_device mxcsdhc_device0 = {
	98	.name = "mxc-mmc",
	99	.id = 0,
	100	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	101	.resource = mxcsdhc0_resources,
	102	};
	103
	104	struct platform_device mxcsdhc_device1 = {
	105	.name = "mxc-mmc",
	106	.id = 1,
	107	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	108	.resource = mxcsdhc1_resources,
	109	};
45001e92 ACA	110
	111	static struct resource rnga_resources[] = {
	112	{
	113	.start = RNGA_BASE_ADDR,
	114	.end = RNGA_BASE_ADDR + 0x28,
	115	.flags = IORESOURCE_MEM,
	116	},
	117	};
	118
	119	struct platform_device mxc_rnga_device = {
	120	.name = "mxc_rnga",
	121	.id = -1,
	122	.num_resources = 1,
	123	.resource = rnga_resources,
	124	};
2adc1d65 SH	125	#endif /* CONFIG_ARCH_MX31 */
2adc1d65 SH	126
ca489f8e VL	127	/* i.MX31 Image Processing Unit */
	128
	129	/* The resource order is important! */
	130	static struct resource mx3_ipu_rsrc[] = {
	131	{
	132	.start = IPU_CTRL_BASE_ADDR,
	133	.end = IPU_CTRL_BASE_ADDR + 0x5F,
	134	.flags = IORESOURCE_MEM,
	135	}, {
	136	.start = IPU_CTRL_BASE_ADDR + 0x88,
	137	.end = IPU_CTRL_BASE_ADDR + 0xB3,
	138	.flags = IORESOURCE_MEM,
	139	}, {
	140	.start = MXC_INT_IPU_SYN,
	141	.end = MXC_INT_IPU_SYN,
	142	.flags = IORESOURCE_IRQ,
	143	}, {
	144	.start = MXC_INT_IPU_ERR,
	145	.end = MXC_INT_IPU_ERR,
	146	.flags = IORESOURCE_IRQ,
	147	},
	148	};
	149
	150	struct platform_device mx3_ipu = {
	151	.name = "ipu-core",
	152	.id = -1,
	153	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	154	.resource = mx3_ipu_rsrc,
	155	};
	156
	157	static struct resource fb_resources[] = {
	158	{
	159	.start = IPU_CTRL_BASE_ADDR + 0xB4,
	160	.end = IPU_CTRL_BASE_ADDR + 0x1BF,
	161	.flags = IORESOURCE_MEM,
	162	},
	163	};
	164
	165	struct platform_device mx3_fb = {
	166	.name = "mx3_sdc_fb",
	167	.id = -1,
	168	.num_resources = ARRAY_SIZE(fb_resources),
	169	.resource = fb_resources,
	170	.dev = {
9c70e227	171	.coherent_dma_mask = DMA_BIT_MASK(32),
ca489f8e VL	172	},
ca489f8e VL	173	};
9536ff33	174
9c70e227 VL	175	static struct resource camera_resources[] = {
	176	{
	177	.start = IPU_CTRL_BASE_ADDR + 0x60,
	178	.end = IPU_CTRL_BASE_ADDR + 0x87,
	179	.flags = IORESOURCE_MEM,
	180	},
	181	};
	182
	183	struct platform_device mx3_camera = {
	184	.name = "mx3-camera",
	185	.id = 0,
	186	.num_resources = ARRAY_SIZE(camera_resources),
	187	.resource = camera_resources,
	188	.dev = {
	189	.coherent_dma_mask = DMA_BIT_MASK(32),
	190	},
	191	};
	192
eb05bbeb GL	193	static struct resource otg_resources[] = {
eb05bbeb GL	194	{
7bc07ebc SH	195	.start = MX31_OTG_BASE_ADDR,
7bc07ebc SH	196	.end = MX31_OTG_BASE_ADDR + 0x1ff,
eb05bbeb GL	197	.flags = IORESOURCE_MEM,
	198	}, {
	199	.start = MXC_INT_USB3,
	200	.end = MXC_INT_USB3,
	201	.flags = IORESOURCE_IRQ,
	202	},
	203	};
	204
	205	static u64 otg_dmamask = DMA_BIT_MASK(32);
	206
	207	/* OTG gadget device */
	208	struct platform_device mxc_otg_udc_device = {
	209	.name = "fsl-usb2-udc",
	210	.id = -1,
	211	.dev = {
	212	.dma_mask = &otg_dmamask,
	213	.coherent_dma_mask = DMA_BIT_MASK(32),
	214	},
	215	.resource = otg_resources,
	216	.num_resources = ARRAY_SIZE(otg_resources),
	217	};
	218
c13a482c DM	219	/* OTG host */
	220	struct platform_device mxc_otg_host = {
	221	.name = "mxc-ehci",
	222	.id = 0,
	223	.dev = {
	224	.coherent_dma_mask = 0xffffffff,
	225	.dma_mask = &otg_dmamask,
	226	},
	227	.resource = otg_resources,
	228	.num_resources = ARRAY_SIZE(otg_resources),
	229	};
	230
	231	/* USB host 1 */
	232
	233	static u64 usbh1_dmamask = ~(u32)0;
	234
	235	static struct resource mxc_usbh1_resources[] = {
	236	{
7bc07ebc SH	237	.start = MX31_OTG_BASE_ADDR + 0x200,
7bc07ebc SH	238	.end = MX31_OTG_BASE_ADDR + 0x3ff,
c13a482c DM	239	.flags = IORESOURCE_MEM,
	240	}, {
	241	.start = MXC_INT_USB1,
	242	.end = MXC_INT_USB1,
	243	.flags = IORESOURCE_IRQ,
	244	},
	245	};
	246
	247	struct platform_device mxc_usbh1 = {
	248	.name = "mxc-ehci",
	249	.id = 1,
	250	.dev = {
	251	.coherent_dma_mask = 0xffffffff,
	252	.dma_mask = &usbh1_dmamask,
	253	},
	254	.resource = mxc_usbh1_resources,
	255	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	256	};
	257
	258	/* USB host 2 */
	259	static u64 usbh2_dmamask = ~(u32)0;
	260
	261	static struct resource mxc_usbh2_resources[] = {
	262	{
7bc07ebc SH	263	.start = MX31_OTG_BASE_ADDR + 0x400,
7bc07ebc SH	264	.end = MX31_OTG_BASE_ADDR + 0x5ff,
c13a482c DM	265	.flags = IORESOURCE_MEM,
	266	}, {
	267	.start = MXC_INT_USB2,
	268	.end = MXC_INT_USB2,
	269	.flags = IORESOURCE_IRQ,
	270	},
	271	};
	272
	273	struct platform_device mxc_usbh2 = {
	274	.name = "mxc-ehci",
	275	.id = 2,
	276	.dev = {
	277	.coherent_dma_mask = 0xffffffff,
	278	.dma_mask = &usbh2_dmamask,
	279	},
	280	.resource = mxc_usbh2_resources,
	281	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
	282	};
	283
a7dc12ba VZ	284	static struct resource imx_wdt_resources[] = {
	285	{
	286	.flags = IORESOURCE_MEM,
	287	},
	288	};
	289
	290	struct platform_device imx_wdt_device0 = {
6d38c1cf	291	.name = "imx2-wdt",
a7dc12ba VZ	292	.id = 0,
	293	.num_resources = ARRAY_SIZE(imx_wdt_resources),
	294	.resource = imx_wdt_resources,
	295	};
	296
ded518c6 VZ	297	static struct resource imx_rtc_resources[] = {
	298	{
	299	.start = MX31_RTC_BASE_ADDR,
	300	.end = MX31_RTC_BASE_ADDR + 0x3fff,
	301	.flags = IORESOURCE_MEM,
	302	},
	303	{
	304	.start = MX31_INT_RTC,
	305	.flags = IORESOURCE_IRQ,
	306	},
	307	};
	308
	309	struct platform_device imx_rtc_device0 = {
	310	.name = "mxc_rtc",
	311	.id = -1,
	312	.num_resources = ARRAY_SIZE(imx_rtc_resources),
	313	.resource = imx_rtc_resources,
	314	};
	315
b1e89955 AP	316	static struct resource imx_kpp_resources[] = {
	317	{
	318	.start = MX3x_KPP_BASE_ADDR,
	319	.end = MX3x_KPP_BASE_ADDR + 0xf,
	320	.flags = IORESOURCE_MEM
	321	}, {
	322	.start = MX3x_INT_KPP,
	323	.end = MX3x_INT_KPP,
	324	.flags = IORESOURCE_IRQ,
	325	},
	326	};
	327
	328	struct platform_device imx_kpp_device = {
	329	.name = "imx-keypad",
	330	.id = -1,
	331	.num_resources = ARRAY_SIZE(imx_kpp_resources),
	332	.resource = imx_kpp_resources,
	333	};
	334
a7dc12ba	335	static int __init mx3_devices_init(void)
9536ff33	336	{
a2ceeef5	337	#if defined(CONFIG_ARCH_MX31)
9536ff33	338	if (cpu_is_mx31()) {
a7dc12ba VZ	339	imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
a7dc12ba VZ	340	imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
45001e92	341	mxc_register_device(&mxc_rnga_device, NULL);
9536ff33	342	}
a2ceeef5 UKK	343	#endif
a2ceeef5 UKK	344	#if defined(CONFIG_ARCH_MX35)
9536ff33	345	if (cpu_is_mx35()) {
7bc07ebc SH	346	otg_resources[0].start = MX35_OTG_BASE_ADDR;
	347	otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
	348	otg_resources[1].start = MXC_INT_USBOTG;
	349	otg_resources[1].end = MXC_INT_USBOTG;
	350	mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
	351	mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
	352	mxc_usbh1_resources[1].start = MXC_INT_USBHS;
	353	mxc_usbh1_resources[1].end = MXC_INT_USBHS;
a7dc12ba VZ	354	imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
a7dc12ba VZ	355	imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
9536ff33	356	}
a2ceeef5	357	#endif
9536ff33 SH	358
	359	return 0;
	360	}
	361
	362	subsys_initcall(mx3_devices_init);