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e3d13ff4 SH |
1 | /* |
2 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
17 | * Boston, MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/serial.h> | |
07bd1a6c | 23 | #include <linux/gpio.h> |
a09e64fb RK |
24 | #include <mach/hardware.h> |
25 | #include <mach/imx-uart.h> | |
e3d13ff4 SH |
26 | |
27 | static struct resource uart0[] = { | |
28 | { | |
29 | .start = UART1_BASE_ADDR, | |
30 | .end = UART1_BASE_ADDR + 0x0B5, | |
31 | .flags = IORESOURCE_MEM, | |
32 | }, { | |
33 | .start = MXC_INT_UART1, | |
34 | .end = MXC_INT_UART1, | |
35 | .flags = IORESOURCE_IRQ, | |
36 | }, | |
37 | }; | |
38 | ||
5cf09421 | 39 | struct platform_device mxc_uart_device0 = { |
e3d13ff4 SH |
40 | .name = "imx-uart", |
41 | .id = 0, | |
42 | .resource = uart0, | |
43 | .num_resources = ARRAY_SIZE(uart0), | |
44 | }; | |
45 | ||
46 | static struct resource uart1[] = { | |
47 | { | |
48 | .start = UART2_BASE_ADDR, | |
49 | .end = UART2_BASE_ADDR + 0x0B5, | |
50 | .flags = IORESOURCE_MEM, | |
51 | }, { | |
52 | .start = MXC_INT_UART2, | |
53 | .end = MXC_INT_UART2, | |
54 | .flags = IORESOURCE_IRQ, | |
55 | }, | |
56 | }; | |
57 | ||
5cf09421 | 58 | struct platform_device mxc_uart_device1 = { |
e3d13ff4 SH |
59 | .name = "imx-uart", |
60 | .id = 1, | |
61 | .resource = uart1, | |
62 | .num_resources = ARRAY_SIZE(uart1), | |
63 | }; | |
64 | ||
65 | static struct resource uart2[] = { | |
66 | { | |
67 | .start = UART3_BASE_ADDR, | |
68 | .end = UART3_BASE_ADDR + 0x0B5, | |
69 | .flags = IORESOURCE_MEM, | |
70 | }, { | |
71 | .start = MXC_INT_UART3, | |
72 | .end = MXC_INT_UART3, | |
73 | .flags = IORESOURCE_IRQ, | |
74 | }, | |
75 | }; | |
76 | ||
5cf09421 | 77 | struct platform_device mxc_uart_device2 = { |
e3d13ff4 SH |
78 | .name = "imx-uart", |
79 | .id = 2, | |
80 | .resource = uart2, | |
81 | .num_resources = ARRAY_SIZE(uart2), | |
82 | }; | |
83 | ||
84 | static struct resource uart3[] = { | |
85 | { | |
86 | .start = UART4_BASE_ADDR, | |
87 | .end = UART4_BASE_ADDR + 0x0B5, | |
88 | .flags = IORESOURCE_MEM, | |
89 | }, { | |
90 | .start = MXC_INT_UART4, | |
91 | .end = MXC_INT_UART4, | |
92 | .flags = IORESOURCE_IRQ, | |
93 | }, | |
94 | }; | |
95 | ||
5cf09421 | 96 | struct platform_device mxc_uart_device3 = { |
e3d13ff4 SH |
97 | .name = "imx-uart", |
98 | .id = 3, | |
99 | .resource = uart3, | |
100 | .num_resources = ARRAY_SIZE(uart3), | |
101 | }; | |
102 | ||
103 | static struct resource uart4[] = { | |
104 | { | |
105 | .start = UART5_BASE_ADDR, | |
106 | .end = UART5_BASE_ADDR + 0x0B5, | |
107 | .flags = IORESOURCE_MEM, | |
108 | }, { | |
109 | .start = MXC_INT_UART5, | |
110 | .end = MXC_INT_UART5, | |
111 | .flags = IORESOURCE_IRQ, | |
112 | }, | |
113 | }; | |
114 | ||
5cf09421 | 115 | struct platform_device mxc_uart_device4 = { |
e3d13ff4 SH |
116 | .name = "imx-uart", |
117 | .id = 4, | |
118 | .resource = uart4, | |
119 | .num_resources = ARRAY_SIZE(uart4), | |
120 | }; | |
121 | ||
07bd1a6c JB |
122 | /* GPIO port description */ |
123 | static struct mxc_gpio_port imx_gpio_ports[] = { | |
124 | [0] = { | |
125 | .chip.label = "gpio-0", | |
126 | .base = IO_ADDRESS(GPIO1_BASE_ADDR), | |
127 | .irq = MXC_INT_GPIO1, | |
9d631b83 | 128 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
07bd1a6c JB |
129 | }, |
130 | [1] = { | |
131 | .chip.label = "gpio-1", | |
132 | .base = IO_ADDRESS(GPIO2_BASE_ADDR), | |
133 | .irq = MXC_INT_GPIO2, | |
9d631b83 | 134 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
07bd1a6c JB |
135 | }, |
136 | [2] = { | |
137 | .chip.label = "gpio-2", | |
138 | .base = IO_ADDRESS(GPIO3_BASE_ADDR), | |
139 | .irq = MXC_INT_GPIO3, | |
9d631b83 | 140 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
07bd1a6c JB |
141 | } |
142 | }; | |
143 | ||
144 | int __init mxc_register_gpios(void) | |
145 | { | |
146 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | |
147 | } | |
a8405929 SH |
148 | |
149 | static struct resource mxc_w1_master_resources[] = { | |
150 | { | |
151 | .start = OWIRE_BASE_ADDR, | |
152 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | |
153 | .flags = IORESOURCE_MEM, | |
154 | }, | |
155 | }; | |
156 | ||
157 | struct platform_device mxc_w1_master_device = { | |
158 | .name = "mxc_w1", | |
159 | .id = 0, | |
160 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | |
161 | .resource = mxc_w1_master_resources, | |
162 | }; | |
cb96cf1a SH |
163 | |
164 | static struct resource mxc_nand_resources[] = { | |
165 | { | |
166 | .start = NFC_BASE_ADDR, | |
167 | .end = NFC_BASE_ADDR + 0xfff, | |
168 | .flags = IORESOURCE_MEM | |
169 | }, { | |
170 | .start = MXC_INT_NANDFC, | |
171 | .end = MXC_INT_NANDFC, | |
172 | .flags = IORESOURCE_IRQ | |
173 | }, | |
174 | }; | |
175 | ||
176 | struct platform_device mxc_nand_device = { | |
177 | .name = "mxc_nand", | |
178 | .id = 0, | |
179 | .num_resources = ARRAY_SIZE(mxc_nand_resources), | |
180 | .resource = mxc_nand_resources, | |
181 | }; |