[net-next-2.6.git] / arch / arm / mach-mx2 / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * SPI master controller
 *
 * - i.MX1: 2 channel (slighly different register setting)
 * - i.MX21: 2 channel
 * - i.MX27: 3 channel
 */
static struct resource mxc_spi_resources0[] = {
	{
	       .start = CSPI1_BASE_ADDR,
	       .end = CSPI1_BASE_ADDR + SZ_4K - 1,
	       .flags = IORESOURCE_MEM,
	}, {
	       .start = MXC_INT_CSPI1,
	       .end = MXC_INT_CSPI1,
	       .flags = IORESOURCE_IRQ,
	},
};

static struct resource mxc_spi_resources1[] = {
	{
		.start = CSPI2_BASE_ADDR,
		.end = CSPI2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_CSPI2,
		.end = MXC_INT_CSPI2,
		.flags = IORESOURCE_IRQ,
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_spi_resources2[] = {
	{
		.start = CSPI3_BASE_ADDR,
		.end = CSPI3_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_CSPI3,
		.end = MXC_INT_CSPI3,
		.flags = IORESOURCE_IRQ,
	},
};
#endif

struct platform_device mxc_spi_device0 = {
	.name = "spi_imx",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_spi_resources0),
	.resource = mxc_spi_resources0,
};

struct platform_device mxc_spi_device1 = {
	.name = "spi_imx",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_spi_resources1),
	.resource = mxc_spi_resources1,
};

#ifdef CONFIG_MACH_MX27
struct platform_device mxc_spi_device2 = {
	.name = "spi_imx",
	.id = 2,
	.num_resources = ARRAY_SIZE(mxc_spi_resources2),
	.resource = mxc_spi_resources2,
};
#endif

/*
 * General Purpose Timer
 * - i.MX21: 3 timers
 * - i.MX27: 6 timers
 */

/* We use gpt0 as system timer, so do not add a device for this one */

static struct resource timer1_resources[] = {
	{
		.start	= GPT2_BASE_ADDR,
		.end	= GPT2_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT2,
		.end     = MXC_INT_GPT2,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt1 = {
	.name = "imx_gpt",
	.id = 1,
	.num_resources = ARRAY_SIZE(timer1_resources),
	.resource = timer1_resources,
};

static struct resource timer2_resources[] = {
	{
		.start	= GPT3_BASE_ADDR,
		.end	= GPT3_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT3,
		.end     = MXC_INT_GPT3,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt2 = {
	.name = "imx_gpt",
	.id = 2,
	.num_resources = ARRAY_SIZE(timer2_resources),
	.resource = timer2_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource timer3_resources[] = {
	{
		.start	= GPT4_BASE_ADDR,
		.end	= GPT4_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT4,
		.end     = MXC_INT_GPT4,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt3 = {
	.name = "imx_gpt",
	.id = 3,
	.num_resources = ARRAY_SIZE(timer3_resources),
	.resource = timer3_resources,
};

static struct resource timer4_resources[] = {
	{
		.start	= GPT5_BASE_ADDR,
		.end	= GPT5_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT5,
		.end     = MXC_INT_GPT5,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt4 = {
	.name = "imx_gpt",
	.id = 4,
	.num_resources = ARRAY_SIZE(timer4_resources),
	.resource = timer4_resources,
};

static struct resource timer5_resources[] = {
	{
		.start	= GPT6_BASE_ADDR,
		.end	= GPT6_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT6,
		.end     = MXC_INT_GPT6,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt5 = {
	.name = "imx_gpt",
	.id = 5,
	.num_resources = ARRAY_SIZE(timer5_resources),
	.resource = timer5_resources,
};
#endif

/*
 * Watchdog:
 * - i.MX1
 * - i.MX21
 * - i.MX27
 */
static struct resource mxc_wdt_resources[] = {
	{
		.start	= WDOG_BASE_ADDR,
		.end	= WDOG_BASE_ADDR + 0x30,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "mxc_wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= NFC_BASE_ADDR,
		.end	= NFC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = LCDC_BASE_ADDR,
		.end   = LCDC_BASE_ADDR + 0xFFF,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_LCDC,
		.end   = MXC_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = 0xFFFFFFFF,
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start	= FEC_BASE_ADDR,
		.end	= FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static struct resource mxc_i2c_1_resources[] = {
	{
		.start	= I2C_BASE_ADDR,
		.end	= I2C_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_I2C,
		.end	= MXC_INT_I2C,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
	.resource = mxc_i2c_1_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_i2c_2_resources[] = {
	{
		.start	= I2C2_BASE_ADDR,
		.end	= I2C2_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_I2C2,
		.end	= MXC_INT_I2C2,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
	.resource = mxc_i2c_2_resources,
};
#endif

static struct resource mxc_pwm_resources[] = {
	{
		.start	= PWM_BASE_ADDR,
		.end	= PWM_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_PWM,
		.end     = MXC_INT_PWM,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources,
};

/*
 * Resource definition for the MXC SDHC
 */
static struct resource mxc_sdhc1_resources[] = {
	{
		.start = SDHC1_BASE_ADDR,
		.end   = SDHC1_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_SDHC1,
		.end   = MXC_INT_SDHC1,
		.flags = IORESOURCE_IRQ,
	}, {
		.start  = DMA_REQ_SDHC1,
		.end    = DMA_REQ_SDHC1,
		.flags  = IORESOURCE_DMA,
	},
};

static u64 mxc_sdhc1_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device0 = {
       .name           = "mxc-mmc",
       .id             = 0,
       .dev            = {
               .dma_mask = &mxc_sdhc1_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
       .resource       = mxc_sdhc1_resources,
};

static struct resource mxc_sdhc2_resources[] = {
	{
		.start = SDHC2_BASE_ADDR,
		.end   = SDHC2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_SDHC2,
		.end   = MXC_INT_SDHC2,
		.flags = IORESOURCE_IRQ,
	}, {
		.start  = DMA_REQ_SDHC2,
		.end    = DMA_REQ_SDHC2,
		.flags  = IORESOURCE_DMA,
	},
};

static u64 mxc_sdhc2_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device1 = {
       .name           = "mxc-mmc",
       .id             = 1,
       .dev            = {
               .dma_mask = &mxc_sdhc2_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
       .resource       = mxc_sdhc2_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
	{
		.start	= OTG_BASE_ADDR,
		.end	= OTG_BASE_ADDR + 0x1ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_USB3,
		.end	= MXC_INT_USB3,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = 0xffffffffUL;

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= 0xffffffffUL,
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = 0xffffffffUL;

static struct resource mxc_usbh1_resources[] = {
	{
		.start = OTG_BASE_ADDR + 0x200,
		.end = OTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB1,
		.end = MXC_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = 0xffffffffUL;

static struct resource mxc_usbh2_resources[] = {
	{
		.start = OTG_BASE_ADDR + 0x400,
		.end = OTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB2,
		.end = MXC_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif

static struct resource imx_ssi_resources0[] = {
	{
		.start	= SSI1_BASE_ADDR,
		.end	= SSI1_BASE_ADDR + 0x6F,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_SSI1,
		.end	= MXC_INT_SSI1,
		.flags	= IORESOURCE_IRQ,
	}, {
		.name	= "tx0",
		.start	= DMA_REQ_SSI1_TX0,
		.end	= DMA_REQ_SSI1_TX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx0",
		.start	= DMA_REQ_SSI1_RX0,
		.end	= DMA_REQ_SSI1_RX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "tx1",
		.start	= DMA_REQ_SSI1_TX1,
		.end	= DMA_REQ_SSI1_TX1,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx1",
		.start	= DMA_REQ_SSI1_RX1,
		.end	= DMA_REQ_SSI1_RX1,
		.flags	= IORESOURCE_DMA,
	},
};

static struct resource imx_ssi_resources1[] = {
	{
		.start	= SSI2_BASE_ADDR,
		.end	= SSI2_BASE_ADDR + 0x6F,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_SSI2,
		.end	= MXC_INT_SSI2,
		.flags	= IORESOURCE_IRQ,
	}, {
		.name	= "tx0",
		.start	= DMA_REQ_SSI2_TX0,
		.end	= DMA_REQ_SSI2_TX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx0",
		.start	= DMA_REQ_SSI2_RX0,
		.end	= DMA_REQ_SSI2_RX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "tx1",
		.start	= DMA_REQ_SSI2_TX1,
		.end	= DMA_REQ_SSI2_TX1,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx1",
		.start	= DMA_REQ_SSI2_RX1,
		.end	= DMA_REQ_SSI2_RX1,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device imx_ssi_device0 = {
	.name = "imx-ssi",
	.id = 0,
	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
	.resource = imx_ssi_resources0,
};

struct platform_device imx_ssi_device1 = {
	.name = "imx-ssi",
	.id = 1,
	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
	.resource = imx_ssi_resources1,
};

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	{
		.chip.label = "gpio-0",
		.irq = MXC_INT_GPIO,
		.base = IO_ADDRESS(GPIO_BASE_ADDR),
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	}, {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	}, {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}, {
		.chip.label = "gpio-3",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
	}, {
		.chip.label = "gpio-4",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
	}, {
		.chip.label = "gpio-5",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
	34
80b02c17	35	#include <mach/irqs.h>
a09e64fb	36	#include <mach/hardware.h>
058b7a6f	37	#include <mach/common.h>
1a02be0e	38	#include <mach/mmc.h>
058b7a6f HS	39
058b7a6f HS	40	#include "devices.h"
fc80a5e3	41
f420db84 SH	42	/*
	43	* SPI master controller
	44	*
	45	* - i.MX1: 2 channel (slighly different register setting)
	46	* - i.MX21: 2 channel
	47	* - i.MX27: 3 channel
	48	*/
	49	static struct resource mxc_spi_resources0[] = {
	50	{
	51	.start = CSPI1_BASE_ADDR,
	52	.end = CSPI1_BASE_ADDR + SZ_4K - 1,
	53	.flags = IORESOURCE_MEM,
	54	}, {
	55	.start = MXC_INT_CSPI1,
	56	.end = MXC_INT_CSPI1,
	57	.flags = IORESOURCE_IRQ,
	58	},
	59	};
	60
	61	static struct resource mxc_spi_resources1[] = {
	62	{
	63	.start = CSPI2_BASE_ADDR,
	64	.end = CSPI2_BASE_ADDR + SZ_4K - 1,
	65	.flags = IORESOURCE_MEM,
	66	}, {
	67	.start = MXC_INT_CSPI2,
	68	.end = MXC_INT_CSPI2,
	69	.flags = IORESOURCE_IRQ,
	70	},
	71	};
	72
	73	#ifdef CONFIG_MACH_MX27
	74	static struct resource mxc_spi_resources2[] = {
	75	{
	76	.start = CSPI3_BASE_ADDR,
	77	.end = CSPI3_BASE_ADDR + SZ_4K - 1,
	78	.flags = IORESOURCE_MEM,
	79	}, {
	80	.start = MXC_INT_CSPI3,
	81	.end = MXC_INT_CSPI3,
	82	.flags = IORESOURCE_IRQ,
	83	},
	84	};
	85	#endif
	86
	87	struct platform_device mxc_spi_device0 = {
	88	.name = "spi_imx",
	89	.id = 0,
	90	.num_resources = ARRAY_SIZE(mxc_spi_resources0),
	91	.resource = mxc_spi_resources0,
	92	};
	93
	94	struct platform_device mxc_spi_device1 = {
	95	.name = "spi_imx",
	96	.id = 1,
	97	.num_resources = ARRAY_SIZE(mxc_spi_resources1),
	98	.resource = mxc_spi_resources1,
	99	};
	100
	101	#ifdef CONFIG_MACH_MX27
	102	struct platform_device mxc_spi_device2 = {
	103	.name = "spi_imx",
	104	.id = 2,
	105	.num_resources = ARRAY_SIZE(mxc_spi_resources2),
106	.resource = mxc_spi_resources2,
107	};
108	#endif
109
fc80a5e3 JB	110	/*
fc80a5e3 JB	111	* General Purpose Timer
bf50bcc2 SH	112	* - i.MX21: 3 timers
bf50bcc2 SH	113	* - i.MX27: 6 timers
fc80a5e3 JB	114	*/
	115
	116	/* We use gpt0 as system timer, so do not add a device for this one */
	117
	118	static struct resource timer1_resources[] = {
bf50bcc2	119	{
fc80a5e3 JB	120	.start = GPT2_BASE_ADDR,
fc80a5e3 JB	121	.end = GPT2_BASE_ADDR + 0x17,
bf50bcc2 SH	122	.flags = IORESOURCE_MEM,
bf50bcc2 SH	123	}, {
fc80a5e3 JB	124	.start = MXC_INT_GPT2,
	125	.end = MXC_INT_GPT2,
	126	.flags = IORESOURCE_IRQ,
	127	}
	128	};
	129
	130	struct platform_device mxc_gpt1 = {
	131	.name = "imx_gpt",
	132	.id = 1,
	133	.num_resources = ARRAY_SIZE(timer1_resources),
bf50bcc2	134	.resource = timer1_resources,
fc80a5e3 JB	135	};
	136
	137	static struct resource timer2_resources[] = {
bf50bcc2	138	{
fc80a5e3 JB	139	.start = GPT3_BASE_ADDR,
fc80a5e3 JB	140	.end = GPT3_BASE_ADDR + 0x17,
bf50bcc2 SH	141	.flags = IORESOURCE_MEM,
bf50bcc2 SH	142	}, {
fc80a5e3 JB	143	.start = MXC_INT_GPT3,
	144	.end = MXC_INT_GPT3,
	145	.flags = IORESOURCE_IRQ,
	146	}
	147	};
	148
	149	struct platform_device mxc_gpt2 = {
	150	.name = "imx_gpt",
	151	.id = 2,
	152	.num_resources = ARRAY_SIZE(timer2_resources),
bf50bcc2	153	.resource = timer2_resources,
fc80a5e3 JB	154	};
	155
	156	#ifdef CONFIG_MACH_MX27
	157	static struct resource timer3_resources[] = {
bf50bcc2	158	{
fc80a5e3 JB	159	.start = GPT4_BASE_ADDR,
fc80a5e3 JB	160	.end = GPT4_BASE_ADDR + 0x17,
bf50bcc2 SH	161	.flags = IORESOURCE_MEM,
bf50bcc2 SH	162	}, {
fc80a5e3 JB	163	.start = MXC_INT_GPT4,
	164	.end = MXC_INT_GPT4,
	165	.flags = IORESOURCE_IRQ,
	166	}
	167	};
	168
	169	struct platform_device mxc_gpt3 = {
	170	.name = "imx_gpt",
	171	.id = 3,
	172	.num_resources = ARRAY_SIZE(timer3_resources),
bf50bcc2	173	.resource = timer3_resources,
fc80a5e3 JB	174	};
	175
	176	static struct resource timer4_resources[] = {
bf50bcc2	177	{
fc80a5e3 JB	178	.start = GPT5_BASE_ADDR,
fc80a5e3 JB	179	.end = GPT5_BASE_ADDR + 0x17,
bf50bcc2 SH	180	.flags = IORESOURCE_MEM,
bf50bcc2 SH	181	}, {
fc80a5e3 JB	182	.start = MXC_INT_GPT5,
	183	.end = MXC_INT_GPT5,
	184	.flags = IORESOURCE_IRQ,
	185	}
	186	};
	187
	188	struct platform_device mxc_gpt4 = {
	189	.name = "imx_gpt",
	190	.id = 4,
	191	.num_resources = ARRAY_SIZE(timer4_resources),
bf50bcc2	192	.resource = timer4_resources,
fc80a5e3 JB	193	};
	194
	195	static struct resource timer5_resources[] = {
bf50bcc2	196	{
fc80a5e3 JB	197	.start = GPT6_BASE_ADDR,
fc80a5e3 JB	198	.end = GPT6_BASE_ADDR + 0x17,
bf50bcc2 SH	199	.flags = IORESOURCE_MEM,
bf50bcc2 SH	200	}, {
fc80a5e3 JB	201	.start = MXC_INT_GPT6,
	202	.end = MXC_INT_GPT6,
	203	.flags = IORESOURCE_IRQ,
	204	}
	205	};
	206
	207	struct platform_device mxc_gpt5 = {
	208	.name = "imx_gpt",
	209	.id = 5,
	210	.num_resources = ARRAY_SIZE(timer5_resources),
bf50bcc2	211	.resource = timer5_resources,
fc80a5e3 JB	212	};
	213	#endif
	214
	215	/*
	216	* Watchdog:
	217	* - i.MX1
	218	* - i.MX21
	219	* - i.MX27
	220	*/
	221	static struct resource mxc_wdt_resources[] = {
	222	{
	223	.start = WDOG_BASE_ADDR,
	224	.end = WDOG_BASE_ADDR + 0x30,
	225	.flags = IORESOURCE_MEM,
	226	},
	227	};
	228
	229	struct platform_device mxc_wdt = {
	230	.name = "mxc_wdt",
	231	.id = 0,
	232	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	233	.resource = mxc_wdt_resources,
	234	};
	235
3d89baa7 SH	236	static struct resource mxc_w1_master_resources[] = {
	237	{
	238	.start = OWIRE_BASE_ADDR,
	239	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	240	.flags = IORESOURCE_MEM,
	241	},
	242	};
	243
	244	struct platform_device mxc_w1_master_device = {
	245	.name = "mxc_w1",
	246	.id = 0,
	247	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	248	.resource = mxc_w1_master_resources,
	249	};
	250
02870978 SH	251	static struct resource mxc_nand_resources[] = {
	252	{
	253	.start = NFC_BASE_ADDR,
	254	.end = NFC_BASE_ADDR + 0xfff,
bf50bcc2	255	.flags = IORESOURCE_MEM,
02870978 SH	256	}, {
	257	.start = MXC_INT_NANDFC,
	258	.end = MXC_INT_NANDFC,
bf50bcc2	259	.flags = IORESOURCE_IRQ,
02870978 SH	260	},
	261	};
	262
	263	struct platform_device mxc_nand_device = {
	264	.name = "mxc_nand",
	265	.id = 0,
	266	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	267	.resource = mxc_nand_resources,
	268	};
	269
e4813551 HS	270	/*
	271	* lcdc:
	272	* - i.MX1: the basic controller
	273	* - i.MX21: to be checked
	274	* - i.MX27: like i.MX1, with slightly variations
	275	*/
	276	static struct resource mxc_fb[] = {
	277	{
	278	.start = LCDC_BASE_ADDR,
	279	.end = LCDC_BASE_ADDR + 0xFFF,
	280	.flags = IORESOURCE_MEM,
bf50bcc2	281	}, {
e4813551 HS	282	.start = MXC_INT_LCDC,
	283	.end = MXC_INT_LCDC,
	284	.flags = IORESOURCE_IRQ,
	285	}
	286	};
	287
	288	/* mxc lcd driver */
	289	struct platform_device mxc_fb_device = {
	290	.name = "imx-fb",
	291	.id = 0,
	292	.num_resources = ARRAY_SIZE(mxc_fb),
	293	.resource = mxc_fb,
	294	.dev = {
	295	.coherent_dma_mask = 0xFFFFFFFF,
	296	},
	297	};
	298
879fea1b SH	299	#ifdef CONFIG_MACH_MX27
	300	static struct resource mxc_fec_resources[] = {
	301	{
	302	.start = FEC_BASE_ADDR,
	303	.end = FEC_BASE_ADDR + 0xfff,
bf50bcc2	304	.flags = IORESOURCE_MEM,
879fea1b SH	305	}, {
	306	.start = MXC_INT_FEC,
	307	.end = MXC_INT_FEC,
bf50bcc2	308	.flags = IORESOURCE_IRQ,
879fea1b SH	309	},
	310	};
	311
	312	struct platform_device mxc_fec_device = {
	313	.name = "fec",
	314	.id = 0,
	315	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	316	.resource = mxc_fec_resources,
	317	};
e4813551 HS	318	#endif
e4813551 HS	319
c5d4dbff	320	static struct resource mxc_i2c_1_resources[] = {
bf50bcc2	321	{
c5d4dbff SH	322	.start = I2C_BASE_ADDR,
c5d4dbff SH	323	.end = I2C_BASE_ADDR + 0x0fff,
bf50bcc2 SH	324	.flags = IORESOURCE_MEM,
bf50bcc2 SH	325	}, {
c5d4dbff SH	326	.start = MXC_INT_I2C,
c5d4dbff SH	327	.end = MXC_INT_I2C,
bf50bcc2	328	.flags = IORESOURCE_IRQ,
c5d4dbff SH	329	}
	330	};
	331
	332	struct platform_device mxc_i2c_device0 = {
	333	.name = "imx-i2c",
	334	.id = 0,
	335	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
bf50bcc2	336	.resource = mxc_i2c_1_resources,
c5d4dbff SH	337	};
	338
	339	#ifdef CONFIG_MACH_MX27
	340	static struct resource mxc_i2c_2_resources[] = {
bf50bcc2	341	{
c5d4dbff SH	342	.start = I2C2_BASE_ADDR,
c5d4dbff SH	343	.end = I2C2_BASE_ADDR + 0x0fff,
bf50bcc2 SH	344	.flags = IORESOURCE_MEM,
bf50bcc2 SH	345	}, {
c5d4dbff SH	346	.start = MXC_INT_I2C2,
c5d4dbff SH	347	.end = MXC_INT_I2C2,
bf50bcc2	348	.flags = IORESOURCE_IRQ,
c5d4dbff SH	349	}
	350	};
	351
	352	struct platform_device mxc_i2c_device1 = {
	353	.name = "imx-i2c",
	354	.id = 1,
	355	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
bf50bcc2	356	.resource = mxc_i2c_2_resources,
c5d4dbff SH	357	};
	358	#endif
	359
824b16e6	360	static struct resource mxc_pwm_resources[] = {
bf50bcc2	361	{
824b16e6 SH	362	.start = PWM_BASE_ADDR,
824b16e6 SH	363	.end = PWM_BASE_ADDR + 0x0fff,
bf50bcc2 SH	364	.flags = IORESOURCE_MEM,
bf50bcc2 SH	365	}, {
824b16e6 SH	366	.start = MXC_INT_PWM,
	367	.end = MXC_INT_PWM,
	368	.flags = IORESOURCE_IRQ,
	369	}
	370	};
	371
	372	struct platform_device mxc_pwm_device = {
	373	.name = "mxc_pwm",
	374	.id = 0,
	375	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
bf50bcc2	376	.resource = mxc_pwm_resources,
824b16e6 SH	377	};
824b16e6 SH	378
1a02be0e SH	379	/*
	380	* Resource definition for the MXC SDHC
	381	*/
	382	static struct resource mxc_sdhc1_resources[] = {
bf50bcc2 SH	383	{
	384	.start = SDHC1_BASE_ADDR,
	385	.end = SDHC1_BASE_ADDR + SZ_4K - 1,
	386	.flags = IORESOURCE_MEM,
	387	}, {
	388	.start = MXC_INT_SDHC1,
	389	.end = MXC_INT_SDHC1,
	390	.flags = IORESOURCE_IRQ,
	391	}, {
	392	.start = DMA_REQ_SDHC1,
	393	.end = DMA_REQ_SDHC1,
	394	.flags = IORESOURCE_DMA,
	395	},
1a02be0e SH	396	};
	397
	398	static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
	399
	400	struct platform_device mxc_sdhc_device0 = {
	401	.name = "mxc-mmc",
	402	.id = 0,
	403	.dev = {
	404	.dma_mask = &mxc_sdhc1_dmamask,
	405	.coherent_dma_mask = 0xffffffff,
	406	},
	407	.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
	408	.resource = mxc_sdhc1_resources,
	409	};
	410
	411	static struct resource mxc_sdhc2_resources[] = {
bf50bcc2 SH	412	{
	413	.start = SDHC2_BASE_ADDR,
	414	.end = SDHC2_BASE_ADDR + SZ_4K - 1,
	415	.flags = IORESOURCE_MEM,
	416	}, {
	417	.start = MXC_INT_SDHC2,
	418	.end = MXC_INT_SDHC2,
	419	.flags = IORESOURCE_IRQ,
	420	}, {
	421	.start = DMA_REQ_SDHC2,
	422	.end = DMA_REQ_SDHC2,
	423	.flags = IORESOURCE_DMA,
	424	},
1a02be0e SH	425	};
	426
	427	static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
	428
	429	struct platform_device mxc_sdhc_device1 = {
	430	.name = "mxc-mmc",
	431	.id = 1,
	432	.dev = {
	433	.dma_mask = &mxc_sdhc2_dmamask,
	434	.coherent_dma_mask = 0xffffffff,
	435	},
	436	.num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
	437	.resource = mxc_sdhc2_resources,
	438	};
	439
f6d2fa7d	440	#ifdef CONFIG_MACH_MX27
627fb3b9 M	441	static struct resource otg_resources[] = {
	442	{
	443	.start = OTG_BASE_ADDR,
	444	.end = OTG_BASE_ADDR + 0x1ff,
	445	.flags = IORESOURCE_MEM,
	446	}, {
	447	.start = MXC_INT_USB3,
	448	.end = MXC_INT_USB3,
	449	.flags = IORESOURCE_IRQ,
	450	},
	451	};
	452
	453	static u64 otg_dmamask = 0xffffffffUL;
	454
	455	/* OTG gadget device */
	456	struct platform_device mxc_otg_udc_device = {
	457	.name = "fsl-usb2-udc",
	458	.id = -1,
	459	.dev = {
	460	.dma_mask = &otg_dmamask,
	461	.coherent_dma_mask = 0xffffffffUL,
	462	},
	463	.resource = otg_resources,
	464	.num_resources = ARRAY_SIZE(otg_resources),
	465	};
	466
	467	/* OTG host */
	468	struct platform_device mxc_otg_host = {
	469	.name = "mxc-ehci",
	470	.id = 0,
	471	.dev = {
	472	.coherent_dma_mask = 0xffffffff,
	473	.dma_mask = &otg_dmamask,
	474	},
	475	.resource = otg_resources,
	476	.num_resources = ARRAY_SIZE(otg_resources),
	477	};
	478
	479	/* USB host 1 */
	480
	481	static u64 usbh1_dmamask = 0xffffffffUL;
	482
	483	static struct resource mxc_usbh1_resources[] = {
	484	{
	485	.start = OTG_BASE_ADDR + 0x200,
	486	.end = OTG_BASE_ADDR + 0x3ff,
	487	.flags = IORESOURCE_MEM,
	488	}, {
	489	.start = MXC_INT_USB1,
	490	.end = MXC_INT_USB1,
	491	.flags = IORESOURCE_IRQ,
	492	},
	493	};
	494
	495	struct platform_device mxc_usbh1 = {
	496	.name = "mxc-ehci",
	497	.id = 1,
	498	.dev = {
	499	.coherent_dma_mask = 0xffffffff,
	500	.dma_mask = &usbh1_dmamask,
	501	},
	502	.resource = mxc_usbh1_resources,
	503	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	504	};
505
506	/* USB host 2 */
507	static u64 usbh2_dmamask = 0xffffffffUL;
508
509	static struct resource mxc_usbh2_resources[] = {
510	{
511	.start = OTG_BASE_ADDR + 0x400,
512	.end = OTG_BASE_ADDR + 0x5ff,
513	.flags = IORESOURCE_MEM,
514	}, {
515	.start = MXC_INT_USB2,
516	.end = MXC_INT_USB2,
517	.flags = IORESOURCE_IRQ,
518	},
519	};
520
521	struct platform_device mxc_usbh2 = {
522	.name = "mxc-ehci",
523	.id = 2,
524	.dev = {
525	.coherent_dma_mask = 0xffffffff,
526	.dma_mask = &usbh2_dmamask,
527	},
528	.resource = mxc_usbh2_resources,
529	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
530	};
f6d2fa7d	531	#endif
627fb3b9	532
23291df4 SH	533	static struct resource imx_ssi_resources0[] = {
	534	{
	535	.start = SSI1_BASE_ADDR,
	536	.end = SSI1_BASE_ADDR + 0x6F,
	537	.flags = IORESOURCE_MEM,
	538	}, {
	539	.start = MXC_INT_SSI1,
	540	.end = MXC_INT_SSI1,
	541	.flags = IORESOURCE_IRQ,
	542	}, {
	543	.name = "tx0",
	544	.start = DMA_REQ_SSI1_TX0,
	545	.end = DMA_REQ_SSI1_TX0,
	546	.flags = IORESOURCE_DMA,
	547	}, {
	548	.name = "rx0",
	549	.start = DMA_REQ_SSI1_RX0,
	550	.end = DMA_REQ_SSI1_RX0,
	551	.flags = IORESOURCE_DMA,
	552	}, {
	553	.name = "tx1",
	554	.start = DMA_REQ_SSI1_TX1,
	555	.end = DMA_REQ_SSI1_TX1,
	556	.flags = IORESOURCE_DMA,
	557	}, {
	558	.name = "rx1",
	559	.start = DMA_REQ_SSI1_RX1,
	560	.end = DMA_REQ_SSI1_RX1,
	561	.flags = IORESOURCE_DMA,
	562	},
	563	};
	564
	565	static struct resource imx_ssi_resources1[] = {
	566	{
	567	.start = SSI2_BASE_ADDR,
	568	.end = SSI2_BASE_ADDR + 0x6F,
	569	.flags = IORESOURCE_MEM,
	570	}, {
	571	.start = MXC_INT_SSI2,
	572	.end = MXC_INT_SSI2,
	573	.flags = IORESOURCE_IRQ,
	574	}, {
	575	.name = "tx0",
	576	.start = DMA_REQ_SSI2_TX0,
	577	.end = DMA_REQ_SSI2_TX0,
	578	.flags = IORESOURCE_DMA,
	579	}, {
	580	.name = "rx0",
	581	.start = DMA_REQ_SSI2_RX0,
	582	.end = DMA_REQ_SSI2_RX0,
	583	.flags = IORESOURCE_DMA,
	584	}, {
	585	.name = "tx1",
	586	.start = DMA_REQ_SSI2_TX1,
	587	.end = DMA_REQ_SSI2_TX1,
	588	.flags = IORESOURCE_DMA,
	589	}, {
	590	.name = "rx1",
	591	.start = DMA_REQ_SSI2_RX1,
	592	.end = DMA_REQ_SSI2_RX1,
	593	.flags = IORESOURCE_DMA,
	594	},
	595	};
	596
597	struct platform_device imx_ssi_device0 = {
598	.name = "imx-ssi",
599	.id = 0,
600	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
601	.resource = imx_ssi_resources0,
602	};
603
604	struct platform_device imx_ssi_device1 = {
605	.name = "imx-ssi",
606	.id = 1,
607	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
608	.resource = imx_ssi_resources1,
609	};
610
fc80a5e3 JB	611	/* GPIO port description */
fc80a5e3 JB	612	static struct mxc_gpio_port imx_gpio_ports[] = {
bf50bcc2	613	{
fc80a5e3 JB	614	.chip.label = "gpio-0",
fc80a5e3 JB	615	.irq = MXC_INT_GPIO,
058b7a6f	616	.base = IO_ADDRESS(GPIO_BASE_ADDR),
9d631b83	617	.virtual_irq_start = MXC_GPIO_IRQ_START,
bf50bcc2	618	}, {
fc80a5e3	619	.chip.label = "gpio-1",
058b7a6f	620	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
9d631b83	621	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
bf50bcc2	622	}, {
fc80a5e3	623	.chip.label = "gpio-2",
058b7a6f	624	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
9d631b83	625	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
bf50bcc2	626	}, {
fc80a5e3	627	.chip.label = "gpio-3",
058b7a6f	628	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
9d631b83	629	.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
bf50bcc2	630	}, {
fc80a5e3	631	.chip.label = "gpio-4",
058b7a6f	632	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
9d631b83	633	.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
bf50bcc2	634	}, {
fc80a5e3	635	.chip.label = "gpio-5",
058b7a6f	636	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
9d631b83	637	.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
fc80a5e3 JB	638	}
	639	};
	640
	641	int __init mxc_register_gpios(void)
	642	{
	643	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	644	}