[net-next-2.6.git] / arch / arm / mach-mx2 / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * General Purpose Timer
 * - i.MX21: 3 timers
 * - i.MX27: 6 timers
 */

/* We use gpt0 as system timer, so do not add a device for this one */

static struct resource timer1_resources[] = {
	{
		.start	= GPT2_BASE_ADDR,
		.end	= GPT2_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT2,
		.end     = MXC_INT_GPT2,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt1 = {
	.name = "imx_gpt",
	.id = 1,
	.num_resources = ARRAY_SIZE(timer1_resources),
	.resource = timer1_resources,
};

static struct resource timer2_resources[] = {
	{
		.start	= GPT3_BASE_ADDR,
		.end	= GPT3_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT3,
		.end     = MXC_INT_GPT3,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt2 = {
	.name = "imx_gpt",
	.id = 2,
	.num_resources = ARRAY_SIZE(timer2_resources),
	.resource = timer2_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource timer3_resources[] = {
	{
		.start	= GPT4_BASE_ADDR,
		.end	= GPT4_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT4,
		.end     = MXC_INT_GPT4,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt3 = {
	.name = "imx_gpt",
	.id = 3,
	.num_resources = ARRAY_SIZE(timer3_resources),
	.resource = timer3_resources,
};

static struct resource timer4_resources[] = {
	{
		.start	= GPT5_BASE_ADDR,
		.end	= GPT5_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT5,
		.end     = MXC_INT_GPT5,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt4 = {
	.name = "imx_gpt",
	.id = 4,
	.num_resources = ARRAY_SIZE(timer4_resources),
	.resource = timer4_resources,
};

static struct resource timer5_resources[] = {
	{
		.start	= GPT6_BASE_ADDR,
		.end	= GPT6_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT6,
		.end     = MXC_INT_GPT6,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt5 = {
	.name = "imx_gpt",
	.id = 5,
	.num_resources = ARRAY_SIZE(timer5_resources),
	.resource = timer5_resources,
};
#endif

/*
 * Watchdog:
 * - i.MX1
 * - i.MX21
 * - i.MX27
 */
static struct resource mxc_wdt_resources[] = {
	{
		.start	= WDOG_BASE_ADDR,
		.end	= WDOG_BASE_ADDR + 0x30,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "mxc_wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= NFC_BASE_ADDR,
		.end	= NFC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = LCDC_BASE_ADDR,
		.end   = LCDC_BASE_ADDR + 0xFFF,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_LCDC,
		.end   = MXC_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = 0xFFFFFFFF,
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start	= FEC_BASE_ADDR,
		.end	= FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static struct resource mxc_i2c_1_resources[] = {
	{
		.start	= I2C_BASE_ADDR,
		.end	= I2C_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_I2C,
		.end	= MXC_INT_I2C,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
	.resource = mxc_i2c_1_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_i2c_2_resources[] = {
	{
		.start	= I2C2_BASE_ADDR,
		.end	= I2C2_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_I2C2,
		.end	= MXC_INT_I2C2,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
	.resource = mxc_i2c_2_resources,
};
#endif

static struct resource mxc_pwm_resources[] = {
	{
		.start	= PWM_BASE_ADDR,
		.end	= PWM_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_PWM,
		.end     = MXC_INT_PWM,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources,
};

/*
 * Resource definition for the MXC SDHC
 */
static struct resource mxc_sdhc1_resources[] = {
	{
		.start = SDHC1_BASE_ADDR,
		.end   = SDHC1_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_SDHC1,
		.end   = MXC_INT_SDHC1,
		.flags = IORESOURCE_IRQ,
	}, {
		.start  = DMA_REQ_SDHC1,
		.end    = DMA_REQ_SDHC1,
		.flags  = IORESOURCE_DMA,
	},
};

static u64 mxc_sdhc1_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device0 = {
       .name           = "mxc-mmc",
       .id             = 0,
       .dev            = {
               .dma_mask = &mxc_sdhc1_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
       .resource       = mxc_sdhc1_resources,
};

static struct resource mxc_sdhc2_resources[] = {
	{
		.start = SDHC2_BASE_ADDR,
		.end   = SDHC2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_SDHC2,
		.end   = MXC_INT_SDHC2,
		.flags = IORESOURCE_IRQ,
	}, {
		.start  = DMA_REQ_SDHC2,
		.end    = DMA_REQ_SDHC2,
		.flags  = IORESOURCE_DMA,
	},
};

static u64 mxc_sdhc2_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device1 = {
       .name           = "mxc-mmc",
       .id             = 1,
       .dev            = {
               .dma_mask = &mxc_sdhc2_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
       .resource       = mxc_sdhc2_resources,
};

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	{
		.chip.label = "gpio-0",
		.irq = MXC_INT_GPIO,
		.base = IO_ADDRESS(GPIO_BASE_ADDR),
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	}, {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	}, {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}, {
		.chip.label = "gpio-3",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
	}, {
		.chip.label = "gpio-4",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
	}, {
		.chip.label = "gpio-5",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
	34
80b02c17	35	#include <mach/irqs.h>
a09e64fb	36	#include <mach/hardware.h>
058b7a6f	37	#include <mach/common.h>
1a02be0e	38	#include <mach/mmc.h>
058b7a6f HS	39
058b7a6f HS	40	#include "devices.h"
fc80a5e3	41
fc80a5e3 JB	42	/*
fc80a5e3 JB	43	* General Purpose Timer
bf50bcc2 SH	44	* - i.MX21: 3 timers
bf50bcc2 SH	45	* - i.MX27: 6 timers
fc80a5e3 JB	46	*/
	47
	48	/* We use gpt0 as system timer, so do not add a device for this one */
	49
	50	static struct resource timer1_resources[] = {
bf50bcc2	51	{
fc80a5e3 JB	52	.start = GPT2_BASE_ADDR,
fc80a5e3 JB	53	.end = GPT2_BASE_ADDR + 0x17,
bf50bcc2 SH	54	.flags = IORESOURCE_MEM,
bf50bcc2 SH	55	}, {
fc80a5e3 JB	56	.start = MXC_INT_GPT2,
	57	.end = MXC_INT_GPT2,
	58	.flags = IORESOURCE_IRQ,
	59	}
	60	};
	61
	62	struct platform_device mxc_gpt1 = {
	63	.name = "imx_gpt",
	64	.id = 1,
	65	.num_resources = ARRAY_SIZE(timer1_resources),
bf50bcc2	66	.resource = timer1_resources,
fc80a5e3 JB	67	};
	68
	69	static struct resource timer2_resources[] = {
bf50bcc2	70	{
fc80a5e3 JB	71	.start = GPT3_BASE_ADDR,
fc80a5e3 JB	72	.end = GPT3_BASE_ADDR + 0x17,
bf50bcc2 SH	73	.flags = IORESOURCE_MEM,
bf50bcc2 SH	74	}, {
fc80a5e3 JB	75	.start = MXC_INT_GPT3,
	76	.end = MXC_INT_GPT3,
	77	.flags = IORESOURCE_IRQ,
	78	}
	79	};
	80
	81	struct platform_device mxc_gpt2 = {
	82	.name = "imx_gpt",
	83	.id = 2,
	84	.num_resources = ARRAY_SIZE(timer2_resources),
bf50bcc2	85	.resource = timer2_resources,
fc80a5e3 JB	86	};
	87
	88	#ifdef CONFIG_MACH_MX27
	89	static struct resource timer3_resources[] = {
bf50bcc2	90	{
fc80a5e3 JB	91	.start = GPT4_BASE_ADDR,
fc80a5e3 JB	92	.end = GPT4_BASE_ADDR + 0x17,
bf50bcc2 SH	93	.flags = IORESOURCE_MEM,
bf50bcc2 SH	94	}, {
fc80a5e3 JB	95	.start = MXC_INT_GPT4,
	96	.end = MXC_INT_GPT4,
	97	.flags = IORESOURCE_IRQ,
	98	}
	99	};
	100
	101	struct platform_device mxc_gpt3 = {
	102	.name = "imx_gpt",
	103	.id = 3,
	104	.num_resources = ARRAY_SIZE(timer3_resources),
bf50bcc2	105	.resource = timer3_resources,
fc80a5e3 JB	106	};
	107
	108	static struct resource timer4_resources[] = {
bf50bcc2	109	{
fc80a5e3 JB	110	.start = GPT5_BASE_ADDR,
fc80a5e3 JB	111	.end = GPT5_BASE_ADDR + 0x17,
bf50bcc2 SH	112	.flags = IORESOURCE_MEM,
bf50bcc2 SH	113	}, {
fc80a5e3 JB	114	.start = MXC_INT_GPT5,
	115	.end = MXC_INT_GPT5,
	116	.flags = IORESOURCE_IRQ,
	117	}
	118	};
	119
	120	struct platform_device mxc_gpt4 = {
	121	.name = "imx_gpt",
	122	.id = 4,
	123	.num_resources = ARRAY_SIZE(timer4_resources),
bf50bcc2	124	.resource = timer4_resources,
fc80a5e3 JB	125	};
	126
	127	static struct resource timer5_resources[] = {
bf50bcc2	128	{
fc80a5e3 JB	129	.start = GPT6_BASE_ADDR,
fc80a5e3 JB	130	.end = GPT6_BASE_ADDR + 0x17,
bf50bcc2 SH	131	.flags = IORESOURCE_MEM,
bf50bcc2 SH	132	}, {
fc80a5e3 JB	133	.start = MXC_INT_GPT6,
	134	.end = MXC_INT_GPT6,
	135	.flags = IORESOURCE_IRQ,
	136	}
	137	};
	138
	139	struct platform_device mxc_gpt5 = {
	140	.name = "imx_gpt",
	141	.id = 5,
	142	.num_resources = ARRAY_SIZE(timer5_resources),
bf50bcc2	143	.resource = timer5_resources,
fc80a5e3 JB	144	};
	145	#endif
	146
	147	/*
	148	* Watchdog:
	149	* - i.MX1
	150	* - i.MX21
	151	* - i.MX27
	152	*/
	153	static struct resource mxc_wdt_resources[] = {
	154	{
	155	.start = WDOG_BASE_ADDR,
	156	.end = WDOG_BASE_ADDR + 0x30,
	157	.flags = IORESOURCE_MEM,
	158	},
	159	};
	160
	161	struct platform_device mxc_wdt = {
	162	.name = "mxc_wdt",
	163	.id = 0,
	164	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	165	.resource = mxc_wdt_resources,
	166	};
	167
3d89baa7 SH	168	static struct resource mxc_w1_master_resources[] = {
	169	{
	170	.start = OWIRE_BASE_ADDR,
	171	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	172	.flags = IORESOURCE_MEM,
	173	},
	174	};
	175
	176	struct platform_device mxc_w1_master_device = {
	177	.name = "mxc_w1",
	178	.id = 0,
	179	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	180	.resource = mxc_w1_master_resources,
	181	};
	182
02870978 SH	183	static struct resource mxc_nand_resources[] = {
	184	{
	185	.start = NFC_BASE_ADDR,
	186	.end = NFC_BASE_ADDR + 0xfff,
bf50bcc2	187	.flags = IORESOURCE_MEM,
02870978 SH	188	}, {
	189	.start = MXC_INT_NANDFC,
	190	.end = MXC_INT_NANDFC,
bf50bcc2	191	.flags = IORESOURCE_IRQ,
02870978 SH	192	},
	193	};
	194
	195	struct platform_device mxc_nand_device = {
	196	.name = "mxc_nand",
	197	.id = 0,
	198	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	199	.resource = mxc_nand_resources,
	200	};
	201
e4813551 HS	202	/*
	203	* lcdc:
	204	* - i.MX1: the basic controller
	205	* - i.MX21: to be checked
	206	* - i.MX27: like i.MX1, with slightly variations
	207	*/
	208	static struct resource mxc_fb[] = {
	209	{
	210	.start = LCDC_BASE_ADDR,
	211	.end = LCDC_BASE_ADDR + 0xFFF,
	212	.flags = IORESOURCE_MEM,
bf50bcc2	213	}, {
e4813551 HS	214	.start = MXC_INT_LCDC,
	215	.end = MXC_INT_LCDC,
	216	.flags = IORESOURCE_IRQ,
	217	}
	218	};
	219
	220	/* mxc lcd driver */
	221	struct platform_device mxc_fb_device = {
	222	.name = "imx-fb",
	223	.id = 0,
	224	.num_resources = ARRAY_SIZE(mxc_fb),
	225	.resource = mxc_fb,
	226	.dev = {
	227	.coherent_dma_mask = 0xFFFFFFFF,
	228	},
	229	};
	230
879fea1b SH	231	#ifdef CONFIG_MACH_MX27
	232	static struct resource mxc_fec_resources[] = {
	233	{
	234	.start = FEC_BASE_ADDR,
	235	.end = FEC_BASE_ADDR + 0xfff,
bf50bcc2	236	.flags = IORESOURCE_MEM,
879fea1b SH	237	}, {
	238	.start = MXC_INT_FEC,
	239	.end = MXC_INT_FEC,
bf50bcc2	240	.flags = IORESOURCE_IRQ,
879fea1b SH	241	},
	242	};
	243
	244	struct platform_device mxc_fec_device = {
	245	.name = "fec",
	246	.id = 0,
	247	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	248	.resource = mxc_fec_resources,
	249	};
e4813551 HS	250	#endif
e4813551 HS	251
c5d4dbff	252	static struct resource mxc_i2c_1_resources[] = {
bf50bcc2	253	{
c5d4dbff SH	254	.start = I2C_BASE_ADDR,
c5d4dbff SH	255	.end = I2C_BASE_ADDR + 0x0fff,
bf50bcc2 SH	256	.flags = IORESOURCE_MEM,
bf50bcc2 SH	257	}, {
c5d4dbff SH	258	.start = MXC_INT_I2C,
c5d4dbff SH	259	.end = MXC_INT_I2C,
bf50bcc2	260	.flags = IORESOURCE_IRQ,
c5d4dbff SH	261	}
	262	};
	263
	264	struct platform_device mxc_i2c_device0 = {
	265	.name = "imx-i2c",
	266	.id = 0,
	267	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
bf50bcc2	268	.resource = mxc_i2c_1_resources,
c5d4dbff SH	269	};
	270
	271	#ifdef CONFIG_MACH_MX27
	272	static struct resource mxc_i2c_2_resources[] = {
bf50bcc2	273	{
c5d4dbff SH	274	.start = I2C2_BASE_ADDR,
c5d4dbff SH	275	.end = I2C2_BASE_ADDR + 0x0fff,
bf50bcc2 SH	276	.flags = IORESOURCE_MEM,
bf50bcc2 SH	277	}, {
c5d4dbff SH	278	.start = MXC_INT_I2C2,
c5d4dbff SH	279	.end = MXC_INT_I2C2,
bf50bcc2	280	.flags = IORESOURCE_IRQ,
c5d4dbff SH	281	}
	282	};
	283
	284	struct platform_device mxc_i2c_device1 = {
	285	.name = "imx-i2c",
	286	.id = 1,
	287	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
bf50bcc2	288	.resource = mxc_i2c_2_resources,
c5d4dbff SH	289	};
	290	#endif
	291
824b16e6	292	static struct resource mxc_pwm_resources[] = {
bf50bcc2	293	{
824b16e6 SH	294	.start = PWM_BASE_ADDR,
824b16e6 SH	295	.end = PWM_BASE_ADDR + 0x0fff,
bf50bcc2 SH	296	.flags = IORESOURCE_MEM,
bf50bcc2 SH	297	}, {
824b16e6 SH	298	.start = MXC_INT_PWM,
	299	.end = MXC_INT_PWM,
	300	.flags = IORESOURCE_IRQ,
	301	}
	302	};
	303
	304	struct platform_device mxc_pwm_device = {
	305	.name = "mxc_pwm",
	306	.id = 0,
	307	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
bf50bcc2	308	.resource = mxc_pwm_resources,
824b16e6 SH	309	};
824b16e6 SH	310
1a02be0e SH	311	/*
	312	* Resource definition for the MXC SDHC
	313	*/
	314	static struct resource mxc_sdhc1_resources[] = {
bf50bcc2 SH	315	{
	316	.start = SDHC1_BASE_ADDR,
	317	.end = SDHC1_BASE_ADDR + SZ_4K - 1,
	318	.flags = IORESOURCE_MEM,
	319	}, {
	320	.start = MXC_INT_SDHC1,
	321	.end = MXC_INT_SDHC1,
	322	.flags = IORESOURCE_IRQ,
	323	}, {
	324	.start = DMA_REQ_SDHC1,
	325	.end = DMA_REQ_SDHC1,
	326	.flags = IORESOURCE_DMA,
	327	},
1a02be0e SH	328	};
	329
	330	static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
	331
	332	struct platform_device mxc_sdhc_device0 = {
	333	.name = "mxc-mmc",
	334	.id = 0,
	335	.dev = {
	336	.dma_mask = &mxc_sdhc1_dmamask,
	337	.coherent_dma_mask = 0xffffffff,
	338	},
	339	.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
	340	.resource = mxc_sdhc1_resources,
	341	};
	342
	343	static struct resource mxc_sdhc2_resources[] = {
bf50bcc2 SH	344	{
	345	.start = SDHC2_BASE_ADDR,
	346	.end = SDHC2_BASE_ADDR + SZ_4K - 1,
	347	.flags = IORESOURCE_MEM,
	348	}, {
	349	.start = MXC_INT_SDHC2,
	350	.end = MXC_INT_SDHC2,
	351	.flags = IORESOURCE_IRQ,
	352	}, {
	353	.start = DMA_REQ_SDHC2,
	354	.end = DMA_REQ_SDHC2,
	355	.flags = IORESOURCE_DMA,
	356	},
1a02be0e SH	357	};
	358
	359	static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
	360
	361	struct platform_device mxc_sdhc_device1 = {
	362	.name = "mxc-mmc",
	363	.id = 1,
	364	.dev = {
	365	.dma_mask = &mxc_sdhc2_dmamask,
	366	.coherent_dma_mask = 0xffffffff,
	367	},
	368	.num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
	369	.resource = mxc_sdhc2_resources,
	370	};
	371
fc80a5e3 JB	372	/* GPIO port description */
fc80a5e3 JB	373	static struct mxc_gpio_port imx_gpio_ports[] = {
bf50bcc2	374	{
fc80a5e3 JB	375	.chip.label = "gpio-0",
fc80a5e3 JB	376	.irq = MXC_INT_GPIO,
058b7a6f	377	.base = IO_ADDRESS(GPIO_BASE_ADDR),
9d631b83	378	.virtual_irq_start = MXC_GPIO_IRQ_START,
bf50bcc2	379	}, {
fc80a5e3	380	.chip.label = "gpio-1",
058b7a6f	381	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
9d631b83	382	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
bf50bcc2	383	}, {
fc80a5e3	384	.chip.label = "gpio-2",
058b7a6f	385	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
9d631b83	386	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
bf50bcc2	387	}, {
fc80a5e3	388	.chip.label = "gpio-3",
058b7a6f	389	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
9d631b83	390	.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
bf50bcc2	391	}, {
fc80a5e3	392	.chip.label = "gpio-4",
058b7a6f	393	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
9d631b83	394	.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
bf50bcc2	395	}, {
fc80a5e3	396	.chip.label = "gpio-5",
058b7a6f	397	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
9d631b83	398	.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
fc80a5e3 JB	399	}
	400	};
	401
	402	int __init mxc_register_gpios(void)
	403	{
	404	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	405	}