[net-next-2.6.git] / arch / arm / mach-mx2 / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>

#include "devices.h"

/*
 * Resource definition for the MXC IrDA
 */
static struct resource mxc_irda_resources[] = {
	[0] = {
		.start   = UART3_BASE_ADDR,
		.end     = UART3_BASE_ADDR + SZ_4K - 1,
		.flags   = IORESOURCE_MEM,
	},
	[1] = {
		.start   = MXC_INT_UART3,
		.end     = MXC_INT_UART3,
		.flags   = IORESOURCE_IRQ,
	},
};

/* Platform Data for MXC IrDA */
struct platform_device mxc_irda_device = {
	.name = "mxc_irda",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_irda_resources),
	.resource = mxc_irda_resources,
};

/*
 * General Purpose Timer
 * - i.MX1: 2 timer (slighly different register handling)
 * - i.MX21: 3 timer
 * - i.MX27: 6 timer
 */

/* We use gpt0 as system timer, so do not add a device for this one */

static struct resource timer1_resources[] = {
	[0] = {
		.start	= GPT2_BASE_ADDR,
		.end	= GPT2_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT2,
		.end     = MXC_INT_GPT2,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt1 = {
	.name = "imx_gpt",
	.id = 1,
	.num_resources = ARRAY_SIZE(timer1_resources),
	.resource = timer1_resources
};

static struct resource timer2_resources[] = {
	[0] = {
		.start	= GPT3_BASE_ADDR,
		.end	= GPT3_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT3,
		.end     = MXC_INT_GPT3,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt2 = {
	.name = "imx_gpt",
	.id = 2,
	.num_resources = ARRAY_SIZE(timer2_resources),
	.resource = timer2_resources
};

#ifdef CONFIG_MACH_MX27
static struct resource timer3_resources[] = {
	[0] = {
		.start	= GPT4_BASE_ADDR,
		.end	= GPT4_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT4,
		.end     = MXC_INT_GPT4,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt3 = {
	.name = "imx_gpt",
	.id = 3,
	.num_resources = ARRAY_SIZE(timer3_resources),
	.resource = timer3_resources
};

static struct resource timer4_resources[] = {
	[0] = {
		.start	= GPT5_BASE_ADDR,
		.end	= GPT5_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT5,
		.end     = MXC_INT_GPT5,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt4 = {
	.name = "imx_gpt",
	.id = 4,
	.num_resources = ARRAY_SIZE(timer4_resources),
	.resource = timer4_resources
};

static struct resource timer5_resources[] = {
	[0] = {
		.start	= GPT6_BASE_ADDR,
		.end	= GPT6_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT6,
		.end     = MXC_INT_GPT6,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt5 = {
	.name = "imx_gpt",
	.id = 5,
	.num_resources = ARRAY_SIZE(timer5_resources),
	.resource = timer5_resources
};
#endif

/*
 * Watchdog:
 * - i.MX1
 * - i.MX21
 * - i.MX27
 */
static struct resource mxc_wdt_resources[] = {
	{
		.start	= WDOG_BASE_ADDR,
		.end	= WDOG_BASE_ADDR + 0x30,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "mxc_wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= NFC_BASE_ADDR,
		.end	= NFC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

#ifdef CONFIG_FB_IMX
/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = LCDC_BASE_ADDR,
		.end   = LCDC_BASE_ADDR + 0xFFF,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_LCDC,
		.end   = MXC_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = 0xFFFFFFFF,
	},
};
#endif

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start	= FEC_BASE_ADDR,
		.end	= FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	[0] = {
		.chip.label = "gpio-0",
		.irq = MXC_INT_GPIO,
		.base = IO_ADDRESS(GPIO_BASE_ADDR),
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	},
	[1] = {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	},
	[2] = {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	},
	[3] = {
		.chip.label = "gpio-3",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
	},
	[4] = {
		.chip.label = "gpio-4",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
	},
	[5] = {
		.chip.label = "gpio-5",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
	34
80b02c17	35	#include <mach/irqs.h>
a09e64fb	36	#include <mach/hardware.h>
058b7a6f HS	37	#include <mach/common.h>
	38
	39	#include "devices.h"
fc80a5e3 JB	40
	41	/*
	42	* Resource definition for the MXC IrDA
	43	*/
	44	static struct resource mxc_irda_resources[] = {
	45	[0] = {
	46	.start = UART3_BASE_ADDR,
	47	.end = UART3_BASE_ADDR + SZ_4K - 1,
	48	.flags = IORESOURCE_MEM,
	49	},
	50	[1] = {
	51	.start = MXC_INT_UART3,
	52	.end = MXC_INT_UART3,
	53	.flags = IORESOURCE_IRQ,
	54	},
	55	};
	56
	57	/* Platform Data for MXC IrDA */
	58	struct platform_device mxc_irda_device = {
	59	.name = "mxc_irda",
	60	.id = 0,
	61	.num_resources = ARRAY_SIZE(mxc_irda_resources),
	62	.resource = mxc_irda_resources,
	63	};
	64
	65	/*
	66	* General Purpose Timer
	67	* - i.MX1: 2 timer (slighly different register handling)
	68	* - i.MX21: 3 timer
	69	* - i.MX27: 6 timer
	70	*/
	71
	72	/* We use gpt0 as system timer, so do not add a device for this one */
	73
	74	static struct resource timer1_resources[] = {
	75	[0] = {
	76	.start = GPT2_BASE_ADDR,
	77	.end = GPT2_BASE_ADDR + 0x17,
	78	.flags = IORESOURCE_MEM
	79	},
	80	[1] = {
	81	.start = MXC_INT_GPT2,
	82	.end = MXC_INT_GPT2,
	83	.flags = IORESOURCE_IRQ,
	84	}
	85	};
	86
	87	struct platform_device mxc_gpt1 = {
	88	.name = "imx_gpt",
	89	.id = 1,
	90	.num_resources = ARRAY_SIZE(timer1_resources),
	91	.resource = timer1_resources
	92	};
	93
	94	static struct resource timer2_resources[] = {
	95	[0] = {
	96	.start = GPT3_BASE_ADDR,
	97	.end = GPT3_BASE_ADDR + 0x17,
	98	.flags = IORESOURCE_MEM
	99	},
	100	[1] = {
	101	.start = MXC_INT_GPT3,
	102	.end = MXC_INT_GPT3,
	103	.flags = IORESOURCE_IRQ,
104	}
105	};
106
107	struct platform_device mxc_gpt2 = {
108	.name = "imx_gpt",
109	.id = 2,
110	.num_resources = ARRAY_SIZE(timer2_resources),
111	.resource = timer2_resources
112	};
113
114	#ifdef CONFIG_MACH_MX27
115	static struct resource timer3_resources[] = {
116	[0] = {
117	.start = GPT4_BASE_ADDR,
118	.end = GPT4_BASE_ADDR + 0x17,
119	.flags = IORESOURCE_MEM
120	},
121	[1] = {
122	.start = MXC_INT_GPT4,
123	.end = MXC_INT_GPT4,
124	.flags = IORESOURCE_IRQ,
125	}
126	};
127
128	struct platform_device mxc_gpt3 = {
129	.name = "imx_gpt",
130	.id = 3,
131	.num_resources = ARRAY_SIZE(timer3_resources),
132	.resource = timer3_resources
133	};
134
135	static struct resource timer4_resources[] = {
136	[0] = {
137	.start = GPT5_BASE_ADDR,
138	.end = GPT5_BASE_ADDR + 0x17,
139	.flags = IORESOURCE_MEM
140	},
141	[1] = {
142	.start = MXC_INT_GPT5,
143	.end = MXC_INT_GPT5,
144	.flags = IORESOURCE_IRQ,
145	}
146	};
147
148	struct platform_device mxc_gpt4 = {
149	.name = "imx_gpt",
150	.id = 4,
151	.num_resources = ARRAY_SIZE(timer4_resources),
152	.resource = timer4_resources
153	};
154
155	static struct resource timer5_resources[] = {
156	[0] = {
157	.start = GPT6_BASE_ADDR,
158	.end = GPT6_BASE_ADDR + 0x17,
159	.flags = IORESOURCE_MEM
160	},
161	[1] = {
162	.start = MXC_INT_GPT6,
163	.end = MXC_INT_GPT6,
164	.flags = IORESOURCE_IRQ,
165	}
166	};
167
168	struct platform_device mxc_gpt5 = {
169	.name = "imx_gpt",
170	.id = 5,
171	.num_resources = ARRAY_SIZE(timer5_resources),
172	.resource = timer5_resources
173	};
174	#endif
175
176	/*
177	* Watchdog:
178	* - i.MX1
179	* - i.MX21
180	* - i.MX27
181	*/
182	static struct resource mxc_wdt_resources[] = {
183	{
184	.start = WDOG_BASE_ADDR,
185	.end = WDOG_BASE_ADDR + 0x30,
186	.flags = IORESOURCE_MEM,
187	},
188	};
189
190	struct platform_device mxc_wdt = {
191	.name = "mxc_wdt",
192	.id = 0,
193	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
194	.resource = mxc_wdt_resources,
195	};
196
3d89baa7 SH	197	static struct resource mxc_w1_master_resources[] = {
	198	{
	199	.start = OWIRE_BASE_ADDR,
	200	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	201	.flags = IORESOURCE_MEM,
	202	},
	203	};
	204
	205	struct platform_device mxc_w1_master_device = {
	206	.name = "mxc_w1",
	207	.id = 0,
	208	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	209	.resource = mxc_w1_master_resources,
	210	};
	211
02870978 SH	212	static struct resource mxc_nand_resources[] = {
	213	{
	214	.start = NFC_BASE_ADDR,
	215	.end = NFC_BASE_ADDR + 0xfff,
	216	.flags = IORESOURCE_MEM
	217	}, {
	218	.start = MXC_INT_NANDFC,
	219	.end = MXC_INT_NANDFC,
	220	.flags = IORESOURCE_IRQ
	221	},
	222	};
	223
	224	struct platform_device mxc_nand_device = {
	225	.name = "mxc_nand",
	226	.id = 0,
	227	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	228	.resource = mxc_nand_resources,
	229	};
	230
e4813551 HS	231	#ifdef CONFIG_FB_IMX
	232	/*
	233	* lcdc:
	234	* - i.MX1: the basic controller
	235	* - i.MX21: to be checked
	236	* - i.MX27: like i.MX1, with slightly variations
	237	*/
	238	static struct resource mxc_fb[] = {
	239	{
	240	.start = LCDC_BASE_ADDR,
	241	.end = LCDC_BASE_ADDR + 0xFFF,
	242	.flags = IORESOURCE_MEM,
	243	},
	244	{
	245	.start = MXC_INT_LCDC,
	246	.end = MXC_INT_LCDC,
	247	.flags = IORESOURCE_IRQ,
	248	}
	249	};
	250
	251	/* mxc lcd driver */
	252	struct platform_device mxc_fb_device = {
	253	.name = "imx-fb",
	254	.id = 0,
	255	.num_resources = ARRAY_SIZE(mxc_fb),
	256	.resource = mxc_fb,
	257	.dev = {
	258	.coherent_dma_mask = 0xFFFFFFFF,
	259	},
	260	};
879fea1b	261	#endif
e4813551	262
879fea1b SH	263	#ifdef CONFIG_MACH_MX27
	264	static struct resource mxc_fec_resources[] = {
	265	{
	266	.start = FEC_BASE_ADDR,
	267	.end = FEC_BASE_ADDR + 0xfff,
	268	.flags = IORESOURCE_MEM
	269	}, {
	270	.start = MXC_INT_FEC,
	271	.end = MXC_INT_FEC,
	272	.flags = IORESOURCE_IRQ
	273	},
	274	};
	275
	276	struct platform_device mxc_fec_device = {
	277	.name = "fec",
	278	.id = 0,
	279	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	280	.resource = mxc_fec_resources,
	281	};
e4813551 HS	282	#endif
e4813551 HS	283
fc80a5e3 JB	284	/* GPIO port description */
	285	static struct mxc_gpio_port imx_gpio_ports[] = {
	286	[0] = {
	287	.chip.label = "gpio-0",
	288	.irq = MXC_INT_GPIO,
058b7a6f	289	.base = IO_ADDRESS(GPIO_BASE_ADDR),
9d631b83	290	.virtual_irq_start = MXC_GPIO_IRQ_START,
fc80a5e3 JB	291	},
	292	[1] = {
	293	.chip.label = "gpio-1",
058b7a6f	294	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
9d631b83	295	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
fc80a5e3 JB	296	},
	297	[2] = {
	298	.chip.label = "gpio-2",
058b7a6f	299	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
9d631b83	300	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
fc80a5e3 JB	301	},
	302	[3] = {
	303	.chip.label = "gpio-3",
058b7a6f	304	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
9d631b83	305	.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
fc80a5e3 JB	306	},
	307	[4] = {
	308	.chip.label = "gpio-4",
058b7a6f	309	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
9d631b83	310	.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
fc80a5e3 JB	311	},
	312	[5] = {
	313	.chip.label = "gpio-5",
058b7a6f	314	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
9d631b83	315	.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
fc80a5e3 JB	316	}
	317	};
	318
	319	int __init mxc_register_gpios(void)
	320	{
	321	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	322	}