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3e4ea372 AH |
1 | /* linux/arch/arm/mach-msm/timer.c |
2 | * | |
3 | * Copyright (C) 2007 Google, Inc. | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/time.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/clockchips.h> | |
22 | #include <linux/delay.h> | |
fced80c7 | 23 | #include <linux/io.h> |
3e4ea372 AH |
24 | |
25 | #include <asm/mach/time.h> | |
a09e64fb | 26 | #include <mach/msm_iomap.h> |
3e4ea372 | 27 | |
83a2c0e4 | 28 | #ifndef MSM_DGT_BASE |
3e4ea372 | 29 | #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10) |
83a2c0e4 | 30 | #endif |
3e4ea372 AH |
31 | |
32 | #define TIMER_MATCH_VAL 0x0000 | |
33 | #define TIMER_COUNT_VAL 0x0004 | |
34 | #define TIMER_ENABLE 0x0008 | |
35 | #define TIMER_ENABLE_CLR_ON_MATCH_EN 2 | |
36 | #define TIMER_ENABLE_EN 1 | |
37 | #define TIMER_CLEAR 0x000C | |
672039f0 JO |
38 | #define DGT_CLK_CTL 0x0034 |
39 | enum { | |
40 | DGT_CLK_CTL_DIV_1 = 0, | |
41 | DGT_CLK_CTL_DIV_2 = 1, | |
42 | DGT_CLK_CTL_DIV_3 = 2, | |
43 | DGT_CLK_CTL_DIV_4 = 3, | |
44 | }; | |
3e4ea372 AH |
45 | #define CSR_PROTECTION 0x0020 |
46 | #define CSR_PROTECTION_EN 1 | |
47 | ||
48 | #define GPT_HZ 32768 | |
672039f0 JO |
49 | |
50 | #if defined(CONFIG_ARCH_QSD8X50) | |
51 | #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ | |
52 | #define MSM_DGT_SHIFT (0) | |
53 | #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) | |
54 | #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ | |
55 | #define MSM_DGT_SHIFT (0) | |
56 | #else | |
3e4ea372 | 57 | #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */ |
672039f0 JO |
58 | #define MSM_DGT_SHIFT (5) |
59 | #endif | |
3e4ea372 AH |
60 | |
61 | struct msm_clock { | |
62 | struct clock_event_device clockevent; | |
63 | struct clocksource clocksource; | |
64 | struct irqaction irq; | |
bcc0f6af | 65 | void __iomem *regbase; |
3e4ea372 AH |
66 | uint32_t freq; |
67 | uint32_t shift; | |
68 | }; | |
69 | ||
70 | static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) | |
71 | { | |
72 | struct clock_event_device *evt = dev_id; | |
73 | evt->event_handler(evt); | |
74 | return IRQ_HANDLED; | |
75 | } | |
76 | ||
8e19608e | 77 | static cycle_t msm_gpt_read(struct clocksource *cs) |
3e4ea372 AH |
78 | { |
79 | return readl(MSM_GPT_BASE + TIMER_COUNT_VAL); | |
80 | } | |
81 | ||
8e19608e | 82 | static cycle_t msm_dgt_read(struct clocksource *cs) |
3e4ea372 AH |
83 | { |
84 | return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT; | |
85 | } | |
86 | ||
87 | static int msm_timer_set_next_event(unsigned long cycles, | |
88 | struct clock_event_device *evt) | |
89 | { | |
90 | struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); | |
91 | uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL); | |
92 | uint32_t alarm = now + (cycles << clock->shift); | |
93 | int late; | |
94 | ||
95 | writel(alarm, clock->regbase + TIMER_MATCH_VAL); | |
96 | now = readl(clock->regbase + TIMER_COUNT_VAL); | |
97 | late = now - alarm; | |
98 | if (late >= (-2 << clock->shift) && late < DGT_HZ*5) { | |
99 | printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, " | |
100 | "alarm already expired, now %x, alarm %x, late %d\n", | |
101 | cycles, clock->clockevent.name, now, alarm, late); | |
102 | return -ETIME; | |
103 | } | |
104 | return 0; | |
105 | } | |
106 | ||
107 | static void msm_timer_set_mode(enum clock_event_mode mode, | |
108 | struct clock_event_device *evt) | |
109 | { | |
110 | struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); | |
111 | switch (mode) { | |
112 | case CLOCK_EVT_MODE_RESUME: | |
113 | case CLOCK_EVT_MODE_PERIODIC: | |
114 | break; | |
115 | case CLOCK_EVT_MODE_ONESHOT: | |
116 | writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE); | |
117 | break; | |
118 | case CLOCK_EVT_MODE_UNUSED: | |
119 | case CLOCK_EVT_MODE_SHUTDOWN: | |
120 | writel(0, clock->regbase + TIMER_ENABLE); | |
121 | break; | |
122 | } | |
123 | } | |
124 | ||
125 | static struct msm_clock msm_clocks[] = { | |
126 | { | |
127 | .clockevent = { | |
128 | .name = "gp_timer", | |
129 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
130 | .shift = 32, | |
131 | .rating = 200, | |
132 | .set_next_event = msm_timer_set_next_event, | |
133 | .set_mode = msm_timer_set_mode, | |
134 | }, | |
135 | .clocksource = { | |
136 | .name = "gp_timer", | |
137 | .rating = 200, | |
138 | .read = msm_gpt_read, | |
139 | .mask = CLOCKSOURCE_MASK(32), | |
6f941961 | 140 | .shift = 17, |
3e4ea372 AH |
141 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
142 | }, | |
143 | .irq = { | |
144 | .name = "gp_timer", | |
145 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING, | |
146 | .handler = msm_timer_interrupt, | |
147 | .dev_id = &msm_clocks[0].clockevent, | |
148 | .irq = INT_GP_TIMER_EXP | |
149 | }, | |
150 | .regbase = MSM_GPT_BASE, | |
151 | .freq = GPT_HZ | |
152 | }, | |
153 | { | |
154 | .clockevent = { | |
155 | .name = "dg_timer", | |
156 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
157 | .shift = 32 + MSM_DGT_SHIFT, | |
158 | .rating = 300, | |
159 | .set_next_event = msm_timer_set_next_event, | |
160 | .set_mode = msm_timer_set_mode, | |
161 | }, | |
162 | .clocksource = { | |
163 | .name = "dg_timer", | |
164 | .rating = 300, | |
165 | .read = msm_dgt_read, | |
166 | .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), | |
167 | .shift = 24 - MSM_DGT_SHIFT, | |
168 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
169 | }, | |
170 | .irq = { | |
171 | .name = "dg_timer", | |
172 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING, | |
173 | .handler = msm_timer_interrupt, | |
174 | .dev_id = &msm_clocks[1].clockevent, | |
175 | .irq = INT_DEBUG_TIMER_EXP | |
176 | }, | |
177 | .regbase = MSM_DGT_BASE, | |
178 | .freq = DGT_HZ >> MSM_DGT_SHIFT, | |
179 | .shift = MSM_DGT_SHIFT | |
180 | } | |
181 | }; | |
182 | ||
183 | static void __init msm_timer_init(void) | |
184 | { | |
185 | int i; | |
186 | int res; | |
187 | ||
672039f0 JO |
188 | #ifdef CONFIG_ARCH_MSM8X60 |
189 | writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); | |
190 | #endif | |
191 | ||
3e4ea372 AH |
192 | for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) { |
193 | struct msm_clock *clock = &msm_clocks[i]; | |
194 | struct clock_event_device *ce = &clock->clockevent; | |
195 | struct clocksource *cs = &clock->clocksource; | |
196 | writel(0, clock->regbase + TIMER_ENABLE); | |
197 | writel(0, clock->regbase + TIMER_CLEAR); | |
198 | writel(~0, clock->regbase + TIMER_MATCH_VAL); | |
199 | ||
200 | ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift); | |
201 | /* allow at least 10 seconds to notice that the timer wrapped */ | |
202 | ce->max_delta_ns = | |
203 | clockevent_delta2ns(0xf0000000 >> clock->shift, ce); | |
204 | /* 4 gets rounded down to 3 */ | |
205 | ce->min_delta_ns = clockevent_delta2ns(4, ce); | |
320ab2b0 | 206 | ce->cpumask = cpumask_of(0); |
3e4ea372 AH |
207 | |
208 | cs->mult = clocksource_hz2mult(clock->freq, cs->shift); | |
209 | res = clocksource_register(cs); | |
210 | if (res) | |
211 | printk(KERN_ERR "msm_timer_init: clocksource_register " | |
212 | "failed for %s\n", cs->name); | |
213 | ||
214 | res = setup_irq(clock->irq.irq, &clock->irq); | |
215 | if (res) | |
216 | printk(KERN_ERR "msm_timer_init: setup_irq " | |
217 | "failed for %s\n", cs->name); | |
218 | ||
219 | clockevents_register_device(ce); | |
220 | } | |
221 | } | |
222 | ||
223 | struct sys_timer msm_timer = { | |
224 | .init = msm_timer_init | |
225 | }; |