[net-next-2.6.git] / arch / arm / mach-kirkwood / pcie.c

/*
 * arch/arm/mach-kirkwood/pcie.c
 *
 * PCIe functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <mach/bridge-regs.h>
#include "common.h"

void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
{
	*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
	*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
}

struct pcie_port {
	u8			root_bus_nr;
	void __iomem		*base;
	spinlock_t		conf_lock;
	int			irq;
	struct resource		res[2];
};

static int pcie_port_map[2];
static int num_pcie_ports;

static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
{
	struct pci_sys_data *sys = bus->sysdata;
	return sys->private_data;
}

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
	/*
	 * Don't go out when trying to access --
	 * 1. nonexisting device on local bus
	 * 2. where there's no device connected (no link)
	 */
	if (bus == pp->root_bus_nr && dev == 0)
		return 1;

	if (!orion_pcie_link_up(pp->base))
		return 0;

	if (bus == pp->root_bus_nr && dev != 1)
		return 0;

	return 1;
}


/*
 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	struct pcie_port *pp = bus_to_port(bus);
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	struct pcie_port *pp = bus_to_port(bus);
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};

static void __init pcie0_ioresources_init(struct pcie_port *pp)
{
	pp->base = (void __iomem *)PCIE_VIRT_BASE;
	pp->irq	= IRQ_KIRKWOOD_PCIE;

	/*
	 * IORESOURCE_IO
	 */
	pp->res[0].name = "PCIe 0 I/O Space";
	pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
	pp->res[0].flags = IORESOURCE_IO;

	/*
	 * IORESOURCE_MEM
	 */
	pp->res[1].name = "PCIe 0 MEM";
	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	pp->res[1].flags = IORESOURCE_MEM;
}

static void __init pcie1_ioresources_init(struct pcie_port *pp)
{
	pp->base = (void __iomem *)PCIE1_VIRT_BASE;
	pp->irq	= IRQ_KIRKWOOD_PCIE1;

	/*
	 * IORESOURCE_IO
	 */
	pp->res[0].name = "PCIe 1 I/O Space";
	pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
	pp->res[0].flags = IORESOURCE_IO;

	/*
	 * IORESOURCE_MEM
	 */
	pp->res[1].name = "PCIe 1 MEM";
	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	pp->res[1].flags = IORESOURCE_MEM;
}

static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
{
	extern unsigned int kirkwood_clk_ctrl;
	struct pcie_port *pp;
	int index;

	if (nr >= num_pcie_ports)
		return 0;

	index = pcie_port_map[nr];
	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);

	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	if (!pp)
		panic("PCIe: failed to allocate pcie_port data");
	sys->private_data = pp;
	pp->root_bus_nr = sys->busnr;
	spin_lock_init(&pp->conf_lock);

	switch (index) {
	case 0:
		kirkwood_clk_ctrl |= CGC_PEX0;
		pcie0_ioresources_init(pp);
		break;
	case 1:
		kirkwood_clk_ctrl |= CGC_PEX1;
		pcie1_ioresources_init(pp);
		break;
	default:
		panic("PCIe setup: invalid controller %d", index);
	}

	if (request_resource(&ioport_resource, &pp->res[0]))
		panic("Request PCIe%d IO resource failed\n", index);
	if (request_resource(&iomem_resource, &pp->res[1]))
		panic("Request PCIe%d Memory resource failed\n", index);

	sys->resource[0] = &pp->res[0];
	sys->resource[1] = &pp->res[1];
	sys->resource[2] = NULL;
	sys->io_offset = 0;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);

	return 1;
}

static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static struct pci_bus __init *
kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr < num_pcie_ports) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pcie_port *pp = bus_to_port(dev->bus);

	return pp->irq;
}

static struct hw_pci kirkwood_pci __initdata = {
	.swizzle	= pci_std_swizzle,
	.setup		= kirkwood_pcie_setup,
	.scan		= kirkwood_pcie_scan_bus,
	.map_irq	= kirkwood_pcie_map_irq,
};

static void __init add_pcie_port(int index, unsigned long base)
{
	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);

	if (orion_pcie_link_up((void __iomem *)base)) {
		printk(KERN_INFO "link up\n");
		pcie_port_map[num_pcie_ports++] = index;
	} else
		printk(KERN_INFO "link down, ignoring\n");
}

void __init kirkwood_pcie_init(unsigned int portmask)
{
	if (portmask & KW_PCIE0)
		add_pcie_port(0, PCIE_VIRT_BASE);

	if (portmask & KW_PCIE1)
		add_pcie_port(1, PCIE1_VIRT_BASE);

	kirkwood_pci.nr_controllers = num_pcie_ports;
	pci_common_init(&kirkwood_pci);
}
Commit	Line	Data
651c74c7 SB	1	/*
	2	* arch/arm/mach-kirkwood/pcie.c
	3	*
	4	* PCIe functions for Marvell Kirkwood SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/pci.h>
5a0e3ad6	13	#include <linux/slab.h>
651c74c7	14	#include <linux/mbus.h>
6e5c11a1	15	#include <asm/irq.h>
651c74c7	16	#include <asm/mach/pci.h>
6f088f1d	17	#include <plat/pcie.h>
e8b2b7ba	18	#include <mach/bridge-regs.h>
651c74c7 SB	19	#include "common.h"
651c74c7 SB	20
ffd58bd2 SB	21	void __init kirkwood_pcie_id(u32 dev, u32 rev)
	22	{
	23	dev = orion_pcie_dev_id((void __iomem )PCIE_VIRT_BASE);
	24	rev = orion_pcie_rev((void __iomem )PCIE_VIRT_BASE);
	25	}
651c74c7	26
ffd58bd2 SB	27	struct pcie_port {
	28	u8 root_bus_nr;
	29	void __iomem *base;
	30	spinlock_t conf_lock;
	31	int irq;
	32	struct resource res[2];
	33	};
651c74c7	34
ffd58bd2 SB	35	static int pcie_port_map[2];
	36	static int num_pcie_ports;
	37
	38	static inline struct pcie_port bus_to_port(struct pci_bus bus)
b2b3dc2f	39	{
ffd58bd2 SB	40	struct pci_sys_data *sys = bus->sysdata;
ffd58bd2 SB	41	return sys->private_data;
b2b3dc2f RS	42	}
b2b3dc2f RS	43
ffd58bd2	44	static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
651c74c7 SB	45	{
	46	/*
	47	* Don't go out when trying to access --
	48	* 1. nonexisting device on local bus
	49	* 2. where there's no device connected (no link)
	50	*/
ffd58bd2	51	if (bus == pp->root_bus_nr && dev == 0)
651c74c7 SB	52	return 1;
651c74c7 SB	53
ffd58bd2	54	if (!orion_pcie_link_up(pp->base))
651c74c7 SB	55	return 0;
651c74c7 SB	56
ffd58bd2	57	if (bus == pp->root_bus_nr && dev != 1)
651c74c7 SB	58	return 0;
	59
	60	return 1;
	61	}
	62
	63
	64	/*
	65	* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
	66	* and then reading the PCIE_CONF_DATA register. Need to make sure these
	67	* transactions are atomic.
	68	*/
651c74c7 SB	69
	70	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
	71	int size, u32 *val)
	72	{
ffd58bd2	73	struct pcie_port *pp = bus_to_port(bus);
651c74c7 SB	74	unsigned long flags;
	75	int ret;
	76
ffd58bd2	77	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
651c74c7 SB	78	*val = 0xffffffff;
	79	return PCIBIOS_DEVICE_NOT_FOUND;
	80	}
	81
ffd58bd2 SB	82	spin_lock_irqsave(&pp->conf_lock, flags);
	83	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	84	spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7 SB	85
	86	return ret;
	87	}
	88
	89	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
	90	int where, int size, u32 val)
	91	{
ffd58bd2	92	struct pcie_port *pp = bus_to_port(bus);
651c74c7 SB	93	unsigned long flags;
	94	int ret;
	95
ffd58bd2	96	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
651c74c7 SB	97	return PCIBIOS_DEVICE_NOT_FOUND;
651c74c7 SB	98
ffd58bd2 SB	99	spin_lock_irqsave(&pp->conf_lock, flags);
	100	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	101	spin_unlock_irqrestore(&pp->conf_lock, flags);
651c74c7 SB	102
	103	return ret;
	104	}
	105
	106	static struct pci_ops pcie_ops = {
	107	.read = pcie_rd_conf,
	108	.write = pcie_wr_conf,
	109	};
	110
a87182b3	111	static void __init pcie0_ioresources_init(struct pcie_port *pp)
651c74c7	112	{
a87182b3 NP	113	pp->base = (void __iomem *)PCIE_VIRT_BASE;
a87182b3 NP	114	pp->irq = IRQ_KIRKWOOD_PCIE;
651c74c7 SB	115
651c74c7 SB	116	/*
ffd58bd2	117	* IORESOURCE_IO
651c74c7	118	*/
ffd58bd2	119	pp->res[0].name = "PCIe 0 I/O Space";
e4ff1c39	120	pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
ffd58bd2 SB	121	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
ffd58bd2 SB	122	pp->res[0].flags = IORESOURCE_IO;
651c74c7 SB	123
651c74c7 SB	124	/*
ffd58bd2	125	* IORESOURCE_MEM
651c74c7	126	*/
ffd58bd2 SB	127	pp->res[1].name = "PCIe 0 MEM";
	128	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
	129	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
	130	pp->res[1].flags = IORESOURCE_MEM;
ffd58bd2 SB	131	}
ffd58bd2 SB	132
a87182b3	133	static void __init pcie1_ioresources_init(struct pcie_port *pp)
ffd58bd2	134	{
a87182b3 NP	135	pp->base = (void __iomem *)PCIE1_VIRT_BASE;
a87182b3 NP	136	pp->irq = IRQ_KIRKWOOD_PCIE1;
651c74c7 SB	137
	138	/*
	139	* IORESOURCE_IO
	140	*/
ffd58bd2	141	pp->res[0].name = "PCIe 1 I/O Space";
e4ff1c39	142	pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
ffd58bd2 SB	143	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
ffd58bd2 SB	144	pp->res[0].flags = IORESOURCE_IO;
651c74c7 SB	145
	146	/*
	147	* IORESOURCE_MEM
	148	*/
ffd58bd2 SB	149	pp->res[1].name = "PCIe 1 MEM";
	150	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
	151	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
	152	pp->res[1].flags = IORESOURCE_MEM;
ffd58bd2 SB	153	}
	154
	155	static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
	156	{
	157	extern unsigned int kirkwood_clk_ctrl;
	158	struct pcie_port *pp;
	159	int index;
	160
	161	if (nr >= num_pcie_ports)
	162	return 0;
	163
	164	index = pcie_port_map[nr];
	165	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
	166
	167	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
	168	if (!pp)
	169	panic("PCIe: failed to allocate pcie_port data");
	170	sys->private_data = pp;
	171	pp->root_bus_nr = sys->busnr;
	172	spin_lock_init(&pp->conf_lock);
	173
	174	switch (index) {
	175	case 0:
ffd58bd2	176	kirkwood_clk_ctrl \|= CGC_PEX0;
a87182b3	177	pcie0_ioresources_init(pp);
ffd58bd2 SB	178	break;
ffd58bd2 SB	179	case 1:
ffd58bd2	180	kirkwood_clk_ctrl \|= CGC_PEX1;
a87182b3	181	pcie1_ioresources_init(pp);
ffd58bd2 SB	182	break;
ffd58bd2 SB	183	default:
a87182b3	184	panic("PCIe setup: invalid controller %d", index);
ffd58bd2 SB	185	}
ffd58bd2 SB	186
a87182b3 NP	187	if (request_resource(&ioport_resource, &pp->res[0]))
	188	panic("Request PCIe%d IO resource failed\n", index);
	189	if (request_resource(&iomem_resource, &pp->res[1]))
	190	panic("Request PCIe%d Memory resource failed\n", index);
	191
	192	sys->resource[0] = &pp->res[0];
	193	sys->resource[1] = &pp->res[1];
	194	sys->resource[2] = NULL;
	195	sys->io_offset = 0;
	196
ffd58bd2 SB	197	/*
	198	* Generic PCIe unit setup.
	199	*/
	200	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
	201
	202	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
e8b2b7ba	203
651c74c7 SB	204	return 1;
	205	}
	206
	207	static void __devinit rc_pci_fixup(struct pci_dev *dev)
	208	{
	209	/*
	210	* Prevent enumeration of root complex.
	211	*/
	212	if (dev->bus->parent == NULL && dev->devfn == 0) {
	213	int i;
	214
	215	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
	216	dev->resource[i].start = 0;
	217	dev->resource[i].end = 0;
	218	dev->resource[i].flags = 0;
	219	}
	220	}
	221	}
	222	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
	223
	224	static struct pci_bus __init *
	225	kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
	226	{
	227	struct pci_bus *bus;
	228
ffd58bd2	229	if (nr < num_pcie_ports) {
651c74c7 SB	230	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	231	} else {
	232	bus = NULL;
	233	BUG();
	234	}
	235
	236	return bus;
	237	}
	238
	239	static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	240	{
ffd58bd2 SB	241	struct pcie_port *pp = bus_to_port(dev->bus);
	242
	243	return pp->irq;
651c74c7 SB	244	}
	245
	246	static struct hw_pci kirkwood_pci __initdata = {
651c74c7 SB	247	.swizzle = pci_std_swizzle,
	248	.setup = kirkwood_pcie_setup,
	249	.scan = kirkwood_pcie_scan_bus,
	250	.map_irq = kirkwood_pcie_map_irq,
	251	};
	252
ffd58bd2 SB	253	static void __init add_pcie_port(int index, unsigned long base)
	254	{
	255	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
	256
	257	if (orion_pcie_link_up((void __iomem *)base)) {
	258	printk(KERN_INFO "link up\n");
	259	pcie_port_map[num_pcie_ports++] = index;
	260	} else
	261	printk(KERN_INFO "link down, ignoring\n");
	262	}
	263
	264	void __init kirkwood_pcie_init(unsigned int portmask)
651c74c7	265	{
ffd58bd2 SB	266	if (portmask & KW_PCIE0)
	267	add_pcie_port(0, PCIE_VIRT_BASE);
	268
	269	if (portmask & KW_PCIE1)
	270	add_pcie_port(1, PCIE1_VIRT_BASE);
	271
	272	kirkwood_pci.nr_controllers = num_pcie_ports;
651c74c7 SB	273	pci_common_init(&kirkwood_pci);
651c74c7 SB	274	}