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Merge branch 'tty-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[net-next-2.6.git] / arch / arm / mach-kirkwood / common.c
CommitLineData
651c74c7
SB		 1/*
2 * arch/arm/mach-kirkwood/common.c
3 *
4 * Core functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
6574e001 17#include <linux/mv643xx_i2c.h>
651c74c7 18#include <linux/ata_platform.h>
fb7b2d3f 19#include <linux/mtd/nand.h>
18365d18 20#include <linux/spi/orion_spi.h>
dcf1cece 21#include <net/dsa.h>
651c74c7
SB		 22#include <asm/page.h>
23#include <asm/timex.h>
24#include <asm/mach/map.h>
25#include <asm/mach/time.h>
a09e64fb 26#include <mach/kirkwood.h>
fdd8b079 27#include <mach/bridge-regs.h>
49106c72 28#include <plat/audio.h>
6f088f1d
LB		 29#include <plat/cache-feroceon-l2.h>
30#include <plat/ehci-orion.h>
8235ee00 31#include <plat/mvsdio.h>
09c0ed2e 32#include <plat/mv_xor.h>
6f088f1d 33#include <plat/orion_nand.h>
3b937a7d 34#include <plat/orion_wdt.h>
6f088f1d 35#include <plat/time.h>
651c74c7
SB		 36#include "common.h"
37
38/*****************************************************************************
39 * I/O Address Mapping
40 ****************************************************************************/
41static struct map_desc kirkwood_io_desc[] __initdata = {
42 {
43 .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
44 .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
45 .length = KIRKWOOD_PCIE_IO_SIZE,
46 .type = MT_DEVICE,
ffd58bd2
SB		 47 }, {
48 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
49 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
50 .length = KIRKWOOD_PCIE1_IO_SIZE,
51 .type = MT_DEVICE,
651c74c7
SB		 52 }, {
53 .virtual = KIRKWOOD_REGS_VIRT_BASE,
54 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
55 .length = KIRKWOOD_REGS_SIZE,
56 .type = MT_DEVICE,
57 },
58};
59
60void __init kirkwood_map_io(void)
61{
62 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
63}
64
e8b2b7ba
RK		 65/*
66 * Default clock control bits. Any bit _not_ set in this variable
67 * will be cleared from the hardware after platform devices have been
68 * registered. Some reserved bits must be set to 1.
69 */
70unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
71
651c74c7
SB		 72
73/*****************************************************************************
74 * EHCI
75 ****************************************************************************/
76static struct orion_ehci_data kirkwood_ehci_data = {
77 .dram = &kirkwood_mbus_dram_info,
fb6f5529 78 .phy_version = EHCI_PHY_NA,
651c74c7
SB		 79};
80
81static u64 ehci_dmamask = 0xffffffffUL;
82
83
84/*****************************************************************************
85 * EHCI0
86 ****************************************************************************/
87static struct resource kirkwood_ehci_resources[] = {
88 {
89 .start = USB_PHYS_BASE,
90 .end = USB_PHYS_BASE + 0x0fff,
91 .flags = IORESOURCE_MEM,
92 }, {
93 .start = IRQ_KIRKWOOD_USB,
94 .end = IRQ_KIRKWOOD_USB,
95 .flags = IORESOURCE_IRQ,
96 },
97};
98
99static struct platform_device kirkwood_ehci = {
100 .name = "orion-ehci",
101 .id = 0,
102 .dev = {
103 .dma_mask = &ehci_dmamask,
104 .coherent_dma_mask = 0xffffffff,
105 .platform_data = &kirkwood_ehci_data,
106 },
107 .resource = kirkwood_ehci_resources,
108 .num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
109};
110
111void __init kirkwood_ehci_init(void)
112{
e8b2b7ba 113 kirkwood_clk_ctrl |= CGC_USB0;
651c74c7
SB		 114 platform_device_register(&kirkwood_ehci);
115}
116
117
118/*****************************************************************************
119 * GE00
120 ****************************************************************************/
121struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
651c74c7
SB		 122 .dram = &kirkwood_mbus_dram_info,
123};
124
125static struct resource kirkwood_ge00_shared_resources[] = {
126 {
127 .name = "ge00 base",
128 .start = GE00_PHYS_BASE + 0x2000,
129 .end = GE00_PHYS_BASE + 0x3fff,
130 .flags = IORESOURCE_MEM,
144f814a
LB		 131 }, {
132 .name = "ge00 err irq",
133 .start = IRQ_KIRKWOOD_GE00_ERR,
134 .end = IRQ_KIRKWOOD_GE00_ERR,
135 .flags = IORESOURCE_IRQ,
651c74c7
SB		 136 },
137};
138
139static struct platform_device kirkwood_ge00_shared = {
140 .name = MV643XX_ETH_SHARED_NAME,
141 .id = 0,
142 .dev = {
143 .platform_data = &kirkwood_ge00_shared_data,
144 },
144f814a 145 .num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
651c74c7
SB		 146 .resource = kirkwood_ge00_shared_resources,
147};
148
149static struct resource kirkwood_ge00_resources[] = {
150 {
151 .name = "ge00 irq",
152 .start = IRQ_KIRKWOOD_GE00_SUM,
153 .end = IRQ_KIRKWOOD_GE00_SUM,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device kirkwood_ge00 = {
159 .name = MV643XX_ETH_NAME,
160 .id = 0,
161 .num_resources = 1,
162 .resource = kirkwood_ge00_resources,
a49a018a
NP		 163 .dev = {
164 .coherent_dma_mask = 0xffffffff,
165 },
651c74c7
SB		 166};
167
168void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
169{
e8b2b7ba 170 kirkwood_clk_ctrl |= CGC_GE0;
651c74c7
SB		 171 eth_data->shared = &kirkwood_ge00_shared;
172 kirkwood_ge00.dev.platform_data = eth_data;
173
174 platform_device_register(&kirkwood_ge00_shared);
175 platform_device_register(&kirkwood_ge00);
176}
177
178
d15fb9ef
RS		 179/*****************************************************************************
180 * GE01
181 ****************************************************************************/
182struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
183 .dram = &kirkwood_mbus_dram_info,
184 .shared_smi = &kirkwood_ge00_shared,
185};
186
187static struct resource kirkwood_ge01_shared_resources[] = {
188 {
189 .name = "ge01 base",
190 .start = GE01_PHYS_BASE + 0x2000,
191 .end = GE01_PHYS_BASE + 0x3fff,
192 .flags = IORESOURCE_MEM,
193 }, {
194 .name = "ge01 err irq",
195 .start = IRQ_KIRKWOOD_GE01_ERR,
196 .end = IRQ_KIRKWOOD_GE01_ERR,
197 .flags = IORESOURCE_IRQ,
198 },
199};
200
201static struct platform_device kirkwood_ge01_shared = {
202 .name = MV643XX_ETH_SHARED_NAME,
203 .id = 1,
204 .dev = {
205 .platform_data = &kirkwood_ge01_shared_data,
206 },
207 .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
208 .resource = kirkwood_ge01_shared_resources,
209};
210
211static struct resource kirkwood_ge01_resources[] = {
212 {
213 .name = "ge01 irq",
214 .start = IRQ_KIRKWOOD_GE01_SUM,
215 .end = IRQ_KIRKWOOD_GE01_SUM,
216 .flags = IORESOURCE_IRQ,
217 },
218};
219
220static struct platform_device kirkwood_ge01 = {
221 .name = MV643XX_ETH_NAME,
222 .id = 1,
223 .num_resources = 1,
224 .resource = kirkwood_ge01_resources,
a49a018a
NP		 225 .dev = {
226 .coherent_dma_mask = 0xffffffff,
227 },
d15fb9ef
RS		 228};
229
230void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
231{
e8b2b7ba 232 kirkwood_clk_ctrl |= CGC_GE1;
d15fb9ef
RS		 233 eth_data->shared = &kirkwood_ge01_shared;
234 kirkwood_ge01.dev.platform_data = eth_data;
235
236 platform_device_register(&kirkwood_ge01_shared);
237 platform_device_register(&kirkwood_ge01);
238}
239
240
dcf1cece
LB		 241/*****************************************************************************
242 * Ethernet switch
243 ****************************************************************************/
244static struct resource kirkwood_switch_resources[] = {
245 {
246 .start = 0,
247 .end = 0,
248 .flags = IORESOURCE_IRQ,
249 },
250};
251
252static struct platform_device kirkwood_switch_device = {
253 .name = "dsa",
254 .id = 0,
255 .num_resources = 0,
256 .resource = kirkwood_switch_resources,
257};
258
259void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
260{
e84665c9
LB		 261 int i;
262
dcf1cece
LB		 263 if (irq != NO_IRQ) {
264 kirkwood_switch_resources[0].start = irq;
265 kirkwood_switch_resources[0].end = irq;
266 kirkwood_switch_device.num_resources = 1;
267 }
268
dcf1cece 269 d->netdev = &kirkwood_ge00.dev;
e84665c9
LB		 270 for (i = 0; i < d->nr_chips; i++)
271 d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
dcf1cece
LB		 272 kirkwood_switch_device.dev.platform_data = d;
273
274 platform_device_register(&kirkwood_switch_device);
275}
276
277
fb7b2d3f
NP		 278/*****************************************************************************
279 * NAND flash
280 ****************************************************************************/
281static struct resource kirkwood_nand_resource = {
282 .flags = IORESOURCE_MEM,
283 .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
284 .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
285 KIRKWOOD_NAND_MEM_SIZE - 1,
286};
287
288static struct orion_nand_data kirkwood_nand_data = {
289 .cle = 0,
290 .ale = 1,
291 .width = 8,
292};
293
294static struct platform_device kirkwood_nand_flash = {
295 .name = "orion_nand",
296 .id = -1,
297 .dev = {
298 .platform_data = &kirkwood_nand_data,
299 },
300 .resource = &kirkwood_nand_resource,
301 .num_resources = 1,
302};
303
304void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
305 int chip_delay)
306{
e8b2b7ba 307 kirkwood_clk_ctrl |= CGC_RUNIT;
fb7b2d3f
NP		 308 kirkwood_nand_data.parts = parts;
309 kirkwood_nand_data.nr_parts = nr_parts;
310 kirkwood_nand_data.chip_delay = chip_delay;
311 platform_device_register(&kirkwood_nand_flash);
312}
313
010937ec
BD		 314void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
315 int (*dev_ready)(struct mtd_info *))
316{
317 kirkwood_clk_ctrl |= CGC_RUNIT;
318 kirkwood_nand_data.parts = parts;
319 kirkwood_nand_data.nr_parts = nr_parts;
320 kirkwood_nand_data.dev_ready = dev_ready;
321 platform_device_register(&kirkwood_nand_flash);
322}
fb7b2d3f 323
651c74c7
SB		 324/*****************************************************************************
325 * SoC RTC
326 ****************************************************************************/
327static struct resource kirkwood_rtc_resource = {
328 .start = RTC_PHYS_BASE,
329 .end = RTC_PHYS_BASE + SZ_16 - 1,
330 .flags = IORESOURCE_MEM,
331};
332
5b99d534 333static void __init kirkwood_rtc_init(void)
651c74c7
SB		 334{
335 platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
336}
337
338
339/*****************************************************************************
340 * SATA
341 ****************************************************************************/
342static struct resource kirkwood_sata_resources[] = {
343 {
344 .name = "sata base",
345 .start = SATA_PHYS_BASE,
346 .end = SATA_PHYS_BASE + 0x5000 - 1,
347 .flags = IORESOURCE_MEM,
348 }, {
349 .name = "sata irq",
350 .start = IRQ_KIRKWOOD_SATA,
351 .end = IRQ_KIRKWOOD_SATA,
352 .flags = IORESOURCE_IRQ,
353 },
354};
355
356static struct platform_device kirkwood_sata = {
357 .name = "sata_mv",
358 .id = 0,
359 .dev = {
360 .coherent_dma_mask = 0xffffffff,
361 },
362 .num_resources = ARRAY_SIZE(kirkwood_sata_resources),
363 .resource = kirkwood_sata_resources,
364};
365
366void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
367{
e8b2b7ba
RK		 368 kirkwood_clk_ctrl |= CGC_SATA0;
369 if (sata_data->n_ports > 1)
370 kirkwood_clk_ctrl |= CGC_SATA1;
651c74c7
SB		 371 sata_data->dram = &kirkwood_mbus_dram_info;
372 kirkwood_sata.dev.platform_data = sata_data;
373 platform_device_register(&kirkwood_sata);
374}
375
376
8235ee00
NP		 377/*****************************************************************************
378 * SD/SDIO/MMC
379 ****************************************************************************/
380static struct resource mvsdio_resources[] = {
381 [0] = {
382 .start = SDIO_PHYS_BASE,
383 .end = SDIO_PHYS_BASE + SZ_1K - 1,
384 .flags = IORESOURCE_MEM,
385 },
386 [1] = {
387 .start = IRQ_KIRKWOOD_SDIO,
388 .end = IRQ_KIRKWOOD_SDIO,
389 .flags = IORESOURCE_IRQ,
390 },
391};
392
393static u64 mvsdio_dmamask = 0xffffffffUL;
394
395static struct platform_device kirkwood_sdio = {
396 .name = "mvsdio",
397 .id = -1,
398 .dev = {
399 .dma_mask = &mvsdio_dmamask,
400 .coherent_dma_mask = 0xffffffff,
401 },
402 .num_resources = ARRAY_SIZE(mvsdio_resources),
403 .resource = mvsdio_resources,
404};
405
406void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
407{
408 u32 dev, rev;
409
410 kirkwood_pcie_id(&dev, &rev);
1e4d2d3d 411 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
8235ee00
NP		 412 mvsdio_data->clock = 100000000;
413 else
414 mvsdio_data->clock = 200000000;
415 mvsdio_data->dram = &kirkwood_mbus_dram_info;
e8b2b7ba 416 kirkwood_clk_ctrl |= CGC_SDIO;
8235ee00
NP		 417 kirkwood_sdio.dev.platform_data = mvsdio_data;
418 platform_device_register(&kirkwood_sdio);
419}
420
421
18365d18
LB		 422/*****************************************************************************
423 * SPI
424 ****************************************************************************/
425static struct orion_spi_info kirkwood_spi_plat_data = {
18365d18
LB		 426};
427
428static struct resource kirkwood_spi_resources[] = {
429 {
430 .start = SPI_PHYS_BASE,
431 .end = SPI_PHYS_BASE + SZ_512 - 1,
432 .flags = IORESOURCE_MEM,
433 },
434};
435
436static struct platform_device kirkwood_spi = {
437 .name = "orion_spi",
438 .id = 0,
439 .resource = kirkwood_spi_resources,
440 .dev = {
441 .platform_data = &kirkwood_spi_plat_data,
442 },
443 .num_resources = ARRAY_SIZE(kirkwood_spi_resources),
444};
445
446void __init kirkwood_spi_init()
447{
e8b2b7ba 448 kirkwood_clk_ctrl |= CGC_RUNIT;
18365d18
LB		 449 platform_device_register(&kirkwood_spi);
450}
451
452
6574e001
MM		 453/*****************************************************************************
454 * I2C
455 ****************************************************************************/
456static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
457 .freq_m = 8, /* assumes 166 MHz TCLK */
458 .freq_n = 3,
459 .timeout = 1000, /* Default timeout of 1 second */
460};
461
462static struct resource kirkwood_i2c_resources[] = {
463 {
6574e001
MM		 464 .start = I2C_PHYS_BASE,
465 .end = I2C_PHYS_BASE + 0x1f,
466 .flags = IORESOURCE_MEM,
467 }, {
6574e001
MM		 468 .start = IRQ_KIRKWOOD_TWSI,
469 .end = IRQ_KIRKWOOD_TWSI,
470 .flags = IORESOURCE_IRQ,
471 },
472};
473
474static struct platform_device kirkwood_i2c = {
475 .name = MV64XXX_I2C_CTLR_NAME,
476 .id = 0,
477 .num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
478 .resource = kirkwood_i2c_resources,
479 .dev = {
480 .platform_data = &kirkwood_i2c_pdata,
481 },
482};
483
484void __init kirkwood_i2c_init(void)
485{
486 platform_device_register(&kirkwood_i2c);
487}
488
489
651c74c7
SB		 490/*****************************************************************************
491 * UART0
492 ****************************************************************************/
493static struct plat_serial8250_port kirkwood_uart0_data[] = {
494 {
495 .mapbase = UART0_PHYS_BASE,
496 .membase = (char *)UART0_VIRT_BASE,
497 .irq = IRQ_KIRKWOOD_UART_0,
498 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
499 .iotype = UPIO_MEM,
500 .regshift = 2,
79d4dd77 501 .uartclk = 0,
651c74c7
SB		 502 }, {
503 },
504};
505
506static struct resource kirkwood_uart0_resources[] = {
507 {
508 .start = UART0_PHYS_BASE,
509 .end = UART0_PHYS_BASE + 0xff,
510 .flags = IORESOURCE_MEM,
511 }, {
512 .start = IRQ_KIRKWOOD_UART_0,
513 .end = IRQ_KIRKWOOD_UART_0,
514 .flags = IORESOURCE_IRQ,
515 },
516};
517
518static struct platform_device kirkwood_uart0 = {
519 .name = "serial8250",
520 .id = 0,
521 .dev = {
522 .platform_data = kirkwood_uart0_data,
523 },
524 .resource = kirkwood_uart0_resources,
525 .num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
526};
527
528void __init kirkwood_uart0_init(void)
529{
530 platform_device_register(&kirkwood_uart0);
531}
532
533
534/*****************************************************************************
535 * UART1
536 ****************************************************************************/
537static struct plat_serial8250_port kirkwood_uart1_data[] = {
538 {
539 .mapbase = UART1_PHYS_BASE,
540 .membase = (char *)UART1_VIRT_BASE,
541 .irq = IRQ_KIRKWOOD_UART_1,
542 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
543 .iotype = UPIO_MEM,
544 .regshift = 2,
79d4dd77 545 .uartclk = 0,
651c74c7
SB		 546 }, {
547 },
548};
549
550static struct resource kirkwood_uart1_resources[] = {
551 {
552 .start = UART1_PHYS_BASE,
553 .end = UART1_PHYS_BASE + 0xff,
554 .flags = IORESOURCE_MEM,
555 }, {
556 .start = IRQ_KIRKWOOD_UART_1,
557 .end = IRQ_KIRKWOOD_UART_1,
558 .flags = IORESOURCE_IRQ,
559 },
560};
561
562static struct platform_device kirkwood_uart1 = {
563 .name = "serial8250",
564 .id = 1,
565 .dev = {
566 .platform_data = kirkwood_uart1_data,
567 },
568 .resource = kirkwood_uart1_resources,
569 .num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
570};
571
572void __init kirkwood_uart1_init(void)
573{
574 platform_device_register(&kirkwood_uart1);
575}
576
577
ae5c8c83
NP		 578/*****************************************************************************
579 * Cryptographic Engines and Security Accelerator (CESA)
580 ****************************************************************************/
581
582static struct resource kirkwood_crypto_res[] = {
583 {
584 .name = "regs",
585 .start = CRYPTO_PHYS_BASE,
586 .end = CRYPTO_PHYS_BASE + 0xffff,
587 .flags = IORESOURCE_MEM,
588 }, {
589 .name = "sram",
590 .start = KIRKWOOD_SRAM_PHYS_BASE,
591 .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
592 .flags = IORESOURCE_MEM,
593 }, {
594 .name = "crypto interrupt",
595 .start = IRQ_KIRKWOOD_CRYPTO,
596 .end = IRQ_KIRKWOOD_CRYPTO,
597 .flags = IORESOURCE_IRQ,
598 },
599};
600
601static struct platform_device kirkwood_crypto_device = {
602 .name = "mv_crypto",
603 .id = -1,
604 .num_resources = ARRAY_SIZE(kirkwood_crypto_res),
605 .resource = kirkwood_crypto_res,
606};
607
608void __init kirkwood_crypto_init(void)
609{
610 kirkwood_clk_ctrl |= CGC_CRYPTO;
611 platform_device_register(&kirkwood_crypto_device);
612}
613
614
09c0ed2e
SB		 615/*****************************************************************************
616 * XOR
617 ****************************************************************************/
618static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
619 .dram = &kirkwood_mbus_dram_info,
620};
621
284901a9 622static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
09c0ed2e
SB		 623
624
625/*****************************************************************************
626 * XOR0
627 ****************************************************************************/
628static struct resource kirkwood_xor0_shared_resources[] = {
629 {
630 .name = "xor 0 low",
631 .start = XOR0_PHYS_BASE,
632 .end = XOR0_PHYS_BASE + 0xff,
633 .flags = IORESOURCE_MEM,
634 }, {
635 .name = "xor 0 high",
636 .start = XOR0_HIGH_PHYS_BASE,
637 .end = XOR0_HIGH_PHYS_BASE + 0xff,
638 .flags = IORESOURCE_MEM,
639 },
640};
641
642static struct platform_device kirkwood_xor0_shared = {
643 .name = MV_XOR_SHARED_NAME,
644 .id = 0,
645 .dev = {
646 .platform_data = &kirkwood_xor_shared_data,
647 },
648 .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
649 .resource = kirkwood_xor0_shared_resources,
650};
651
652static struct resource kirkwood_xor00_resources[] = {
653 [0] = {
654 .start = IRQ_KIRKWOOD_XOR_00,
655 .end = IRQ_KIRKWOOD_XOR_00,
656 .flags = IORESOURCE_IRQ,
657 },
658};
659
660static struct mv_xor_platform_data kirkwood_xor00_data = {
661 .shared = &kirkwood_xor0_shared,
662 .hw_id = 0,
663 .pool_size = PAGE_SIZE,
664};
665
666static struct platform_device kirkwood_xor00_channel = {
667 .name = MV_XOR_NAME,
668 .id = 0,
669 .num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
670 .resource = kirkwood_xor00_resources,
671 .dev = {
672 .dma_mask = &kirkwood_xor_dmamask,
6a35528a 673 .coherent_dma_mask = DMA_BIT_MASK(64),
3e3e65fc 674 .platform_data = &kirkwood_xor00_data,
09c0ed2e
SB		 675 },
676};
677
678static struct resource kirkwood_xor01_resources[] = {
679 [0] = {
680 .start = IRQ_KIRKWOOD_XOR_01,
681 .end = IRQ_KIRKWOOD_XOR_01,
682 .flags = IORESOURCE_IRQ,
683 },
684};
685
686static struct mv_xor_platform_data kirkwood_xor01_data = {
687 .shared = &kirkwood_xor0_shared,
688 .hw_id = 1,
689 .pool_size = PAGE_SIZE,
690};
691
692static struct platform_device kirkwood_xor01_channel = {
693 .name = MV_XOR_NAME,
694 .id = 1,
695 .num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
696 .resource = kirkwood_xor01_resources,
697 .dev = {
698 .dma_mask = &kirkwood_xor_dmamask,
6a35528a 699 .coherent_dma_mask = DMA_BIT_MASK(64),
3e3e65fc 700 .platform_data = &kirkwood_xor01_data,
09c0ed2e
SB		 701 },
702};
703
5b99d534 704static void __init kirkwood_xor0_init(void)
09c0ed2e 705{
e8b2b7ba 706 kirkwood_clk_ctrl |= CGC_XOR0;
09c0ed2e
SB		 707 platform_device_register(&kirkwood_xor0_shared);
708
709 /*
710 * two engines can't do memset simultaneously, this limitation
711 * satisfied by removing memset support from one of the engines.
712 */
713 dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
714 dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
715 platform_device_register(&kirkwood_xor00_channel);
716
717 dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
718 dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
719 dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
720 platform_device_register(&kirkwood_xor01_channel);
721}
722
723
724/*****************************************************************************
725 * XOR1
726 ****************************************************************************/
727static struct resource kirkwood_xor1_shared_resources[] = {
728 {
729 .name = "xor 1 low",
730 .start = XOR1_PHYS_BASE,
731 .end = XOR1_PHYS_BASE + 0xff,
732 .flags = IORESOURCE_MEM,
733 }, {
734 .name = "xor 1 high",
735 .start = XOR1_HIGH_PHYS_BASE,
736 .end = XOR1_HIGH_PHYS_BASE + 0xff,
737 .flags = IORESOURCE_MEM,
738 },
739};
740
741static struct platform_device kirkwood_xor1_shared = {
742 .name = MV_XOR_SHARED_NAME,
743 .id = 1,
744 .dev = {
745 .platform_data = &kirkwood_xor_shared_data,
746 },
747 .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
748 .resource = kirkwood_xor1_shared_resources,
749};
750
751static struct resource kirkwood_xor10_resources[] = {
752 [0] = {
753 .start = IRQ_KIRKWOOD_XOR_10,
754 .end = IRQ_KIRKWOOD_XOR_10,
755 .flags = IORESOURCE_IRQ,
756 },
757};
758
759static struct mv_xor_platform_data kirkwood_xor10_data = {
760 .shared = &kirkwood_xor1_shared,
761 .hw_id = 0,
762 .pool_size = PAGE_SIZE,
763};
764
765static struct platform_device kirkwood_xor10_channel = {
766 .name = MV_XOR_NAME,
767 .id = 2,
768 .num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
769 .resource = kirkwood_xor10_resources,
770 .dev = {
771 .dma_mask = &kirkwood_xor_dmamask,
6a35528a 772 .coherent_dma_mask = DMA_BIT_MASK(64),
3e3e65fc 773 .platform_data = &kirkwood_xor10_data,
09c0ed2e
SB		 774 },
775};
776
777static struct resource kirkwood_xor11_resources[] = {
778 [0] = {
779 .start = IRQ_KIRKWOOD_XOR_11,
780 .end = IRQ_KIRKWOOD_XOR_11,
781 .flags = IORESOURCE_IRQ,
782 },
783};
784
785static struct mv_xor_platform_data kirkwood_xor11_data = {
786 .shared = &kirkwood_xor1_shared,
787 .hw_id = 1,
788 .pool_size = PAGE_SIZE,
789};
790
791static struct platform_device kirkwood_xor11_channel = {
792 .name = MV_XOR_NAME,
793 .id = 3,
794 .num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
795 .resource = kirkwood_xor11_resources,
796 .dev = {
797 .dma_mask = &kirkwood_xor_dmamask,
6a35528a 798 .coherent_dma_mask = DMA_BIT_MASK(64),
3e3e65fc 799 .platform_data = &kirkwood_xor11_data,
09c0ed2e
SB		 800 },
801};
802
5b99d534 803static void __init kirkwood_xor1_init(void)
09c0ed2e 804{
e8b2b7ba 805 kirkwood_clk_ctrl |= CGC_XOR1;
09c0ed2e
SB		 806 platform_device_register(&kirkwood_xor1_shared);
807
808 /*
809 * two engines can't do memset simultaneously, this limitation
810 * satisfied by removing memset support from one of the engines.
811 */
812 dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
813 dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
814 platform_device_register(&kirkwood_xor10_channel);
815
816 dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
817 dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
818 dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
819 platform_device_register(&kirkwood_xor11_channel);
820}
821
822
054bd3f0
TR		 823/*****************************************************************************
824 * Watchdog
825 ****************************************************************************/
3b937a7d 826static struct orion_wdt_platform_data kirkwood_wdt_data = {
054bd3f0
TR		 827 .tclk = 0,
828};
829
830static struct platform_device kirkwood_wdt_device = {
3b937a7d 831 .name = "orion_wdt",
054bd3f0
TR		 832 .id = -1,
833 .dev = {
834 .platform_data = &kirkwood_wdt_data,
835 },
836 .num_resources = 0,
837};
838
839static void __init kirkwood_wdt_init(void)
840{
841 kirkwood_wdt_data.tclk = kirkwood_tclk;
842 platform_device_register(&kirkwood_wdt_device);
843}
844
845
651c74c7
SB		 846/*****************************************************************************
847 * Time handling
848 ****************************************************************************/
79d4dd77
RS		 849int kirkwood_tclk;
850
851int __init kirkwood_find_tclk(void)
852{
b2b3dc2f
RS		 853 u32 dev, rev;
854
855 kirkwood_pcie_id(&dev, &rev);
1e4d2d3d 856
2fa0f939
SG		 857 if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
858 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
859 return 200000000;
b2b3dc2f 860
79d4dd77
RS		 861 return 166666667;
862}
863
6de95c19 864static void __init kirkwood_timer_init(void)
651c74c7 865{
79d4dd77
RS		 866 kirkwood_tclk = kirkwood_find_tclk();
867 orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
651c74c7
SB		 868}
869
870struct sys_timer kirkwood_timer = {
871 .init = kirkwood_timer_init,
872};
873
49106c72 874/*****************************************************************************
875 * Audio
876 ****************************************************************************/
877static struct resource kirkwood_i2s_resources[] = {
878 [0] = {
879 .start = AUDIO_PHYS_BASE,
880 .end = AUDIO_PHYS_BASE + SZ_16K - 1,
881 .flags = IORESOURCE_MEM,
882 },
883 [1] = {
884 .start = IRQ_KIRKWOOD_I2S,
885 .end = IRQ_KIRKWOOD_I2S,
886 .flags = IORESOURCE_IRQ,
887 },
888};
889
890static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
891 .dram = &kirkwood_mbus_dram_info,
892 .burst = 128,
893};
894
895static struct platform_device kirkwood_i2s_device = {
896 .name = "kirkwood-i2s",
897 .id = -1,
898 .num_resources = ARRAY_SIZE(kirkwood_i2s_resources),
899 .resource = kirkwood_i2s_resources,
900 .dev = {
901 .platform_data = &kirkwood_i2s_data,
902 },
903};
904
f0fba2ad 905static struct platform_device kirkwood_pcm_device = {
c88e7b93 906 .name = "kirkwood-pcm-audio",
f0fba2ad
LG		 907 .id = -1,
908};
909
49106c72 910void __init kirkwood_audio_init(void)
911{
912 kirkwood_clk_ctrl |= CGC_AUDIO;
913 platform_device_register(&kirkwood_i2s_device);
f0fba2ad 914 platform_device_register(&kirkwood_pcm_device);
49106c72 915}
651c74c7
SB		 916
917/*****************************************************************************
918 * General
919 ****************************************************************************/
b2b3dc2f
RS		 920/*
921 * Identify device ID and revision.
922 */
651c74c7
SB		 923static char * __init kirkwood_id(void)
924{
b2b3dc2f
RS		 925 u32 dev, rev;
926
927 kirkwood_pcie_id(&dev, &rev);
928
929 if (dev == MV88F6281_DEV_ID) {
930 if (rev == MV88F6281_REV_Z0)
931 return "MV88F6281-Z0";
932 else if (rev == MV88F6281_REV_A0)
933 return "MV88F6281-A0";
aec1bad3
SG		 934 else if (rev == MV88F6281_REV_A1)
935 return "MV88F6281-A1";
b2b3dc2f
RS		 936 else
937 return "MV88F6281-Rev-Unsupported";
938 } else if (dev == MV88F6192_DEV_ID) {
939 if (rev == MV88F6192_REV_Z0)
940 return "MV88F6192-Z0";
941 else if (rev == MV88F6192_REV_A0)
942 return "MV88F6192-A0";
1c2003a1
SB		 943 else if (rev == MV88F6192_REV_A1)
944 return "MV88F6192-A1";
b2b3dc2f
RS		 945 else
946 return "MV88F6192-Rev-Unsupported";
947 } else if (dev == MV88F6180_DEV_ID) {
948 if (rev == MV88F6180_REV_A0)
949 return "MV88F6180-Rev-A0";
1c2003a1
SB		 950 else if (rev == MV88F6180_REV_A1)
951 return "MV88F6180-Rev-A1";
b2b3dc2f
RS		 952 else
953 return "MV88F6180-Rev-Unsupported";
1e4d2d3d
SB		 954 } else if (dev == MV88F6282_DEV_ID) {
955 if (rev == MV88F6282_REV_A0)
956 return "MV88F6282-Rev-A0";
957 else
958 return "MV88F6282-Rev-Unsupported";
b2b3dc2f
RS		 959 } else {
960 return "Device-Unknown";
651c74c7 961 }
651c74c7
SB		 962}
963
4360bb41 964static void __init kirkwood_l2_init(void)
13387603 965{
4360bb41
RS		 966#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
967 writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
968 feroceon_l2_init(1);
969#else
970 writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
971 feroceon_l2_init(0);
972#endif
13387603
SB		 973}
974
651c74c7
SB		 975void __init kirkwood_init(void)
976{
977 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
79d4dd77
RS		 978 kirkwood_id(), kirkwood_tclk);
979 kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
13731d1a 980 kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
79d4dd77
RS		 981 kirkwood_spi_plat_data.tclk = kirkwood_tclk;
982 kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
983 kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
49106c72 984 kirkwood_i2s_data.tclk = kirkwood_tclk;
651c74c7 985
2bf30108
LB		 986 /*
987 * Disable propagation of mbus errors to the CPU local bus,
988 * as this causes mbus errors (which can occur for example
989 * for PCI aborts) to throw CPU aborts, which we're not set
990 * up to deal with.
991 */
992 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
993
651c74c7
SB		 994 kirkwood_setup_cpu_mbus();
995
996#ifdef CONFIG_CACHE_FEROCEON_L2
4360bb41 997 kirkwood_l2_init();
651c74c7 998#endif
5b99d534
NP		 999
1000 /* internal devices that every board has */
1001 kirkwood_rtc_init();
054bd3f0 1002 kirkwood_wdt_init();
5b99d534
NP		 1003 kirkwood_xor0_init();
1004 kirkwood_xor1_init();
ae5c8c83 1005 kirkwood_crypto_init();
651c74c7 1006}
e8b2b7ba
RK		 1007
1008static int __init kirkwood_clock_gate(void)
1009{
1010 unsigned int curr = readl(CLOCK_GATING_CTRL);
ffd58bd2 1011 u32 dev, rev;
e8b2b7ba 1012
ffd58bd2 1013 kirkwood_pcie_id(&dev, &rev);
e8b2b7ba
RK		 1014 printk(KERN_DEBUG "Gating clock of unused units\n");
1015 printk(KERN_DEBUG "before: 0x%08x\n", curr);
1016
1017 /* Make sure those units are accessible */
ffd58bd2 1018 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
e8b2b7ba
RK		 1019
1020 /* For SATA: first shutdown the phy */
1021 if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
1022 /* Disable PLL and IVREF */
1023 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
1024 /* Disable PHY */
1025 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
1026 }
1027 if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
1028 /* Disable PLL and IVREF */
1029 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
1030 /* Disable PHY */
1031 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
1032 }
1033
1034 /* For PCIe: first shutdown the phy */
1035 if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
1036 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
1037 while (1)
1038 if (readl(PCIE_STATUS) & 0x1)
1039 break;
1040 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
1041 }
1042
ffd58bd2
SB		 1043 /* For PCIe 1: first shutdown the phy */
1044 if (dev == MV88F6282_DEV_ID) {
1045 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
1046 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
1047 while (1)
1048 if (readl(PCIE1_STATUS) & 0x1)
1049 break;
1050 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
1051 }
1052 } else /* keep this bit set for devices that don't have PCIe1 */
1053 kirkwood_clk_ctrl |= CGC_PEX1;
1054
e8b2b7ba
RK		 1055 /* Now gate clock the required units */
1056 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
1057 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
1058
1059 return 0;
1060}
1061late_initcall(kirkwood_clock_gate);
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