[net-next-2.6.git] / arch / arm / mach-kirkwood / addr-map.c

/*
 * arch/arm/mach-kirkwood/addr-map.c
 *
 * Address map functions for Marvell Kirkwood SoCs
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include "common.h"

/*
 * Generic Address Decode Windows bit settings
 */
#define TARGET_DDR		0
#define TARGET_DEV_BUS		1
#define TARGET_SRAM		3
#define TARGET_PCIE		4
#define ATTR_DEV_SPI_ROM	0x1e
#define ATTR_DEV_BOOT		0x1d
#define ATTR_DEV_NAND		0x2f
#define ATTR_DEV_CS3		0x37
#define ATTR_DEV_CS2		0x3b
#define ATTR_DEV_CS1		0x3d
#define ATTR_DEV_CS0		0x3e
#define ATTR_PCIE_IO		0xe0
#define ATTR_PCIE_MEM		0xe8
#define ATTR_SRAM		0x01

/*
 * Helpers to get DDR bank info
 */
#define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
#define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))

/*
 * CPU Address Decode Windows registers
 */
#define WIN_OFF(n)		(BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
#define WIN_CTRL_OFF		0x0000
#define WIN_BASE_OFF		0x0004
#define WIN_REMAP_LO_OFF	0x0008
#define WIN_REMAP_HI_OFF	0x000c


struct mbus_dram_target_info kirkwood_mbus_dram_info;

static int __init cpu_win_can_remap(int win)
{
	if (win < 4)
		return 1;

	return 0;
}

static void __init setup_cpu_win(int win, u32 base, u32 size,
				 u8 target, u8 attr, int remap)
{
	void __iomem *addr = (void __iomem *)WIN_OFF(win);
	u32 ctrl;

	base &= 0xffff0000;
	ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;

	writel(base, addr + WIN_BASE_OFF);
	writel(ctrl, addr + WIN_CTRL_OFF);
	if (cpu_win_can_remap(win)) {
		if (remap < 0)
			remap = base;

		writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
		writel(0, addr + WIN_REMAP_HI_OFF);
	}
}

void __init kirkwood_setup_cpu_mbus(void)
{
	void __iomem *addr;
	int i;
	int cs;

	/*
	 * First, disable and clear windows.
	 */
	for (i = 0; i < 8; i++) {
		addr = (void __iomem *)WIN_OFF(i);

		writel(0, addr + WIN_BASE_OFF);
		writel(0, addr + WIN_CTRL_OFF);
		if (cpu_win_can_remap(i)) {
			writel(0, addr + WIN_REMAP_LO_OFF);
			writel(0, addr + WIN_REMAP_HI_OFF);
		}
	}

	/*
	 * Setup windows for PCIe IO+MEM space.
	 */
	setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);

	/*
	 * Setup window for NAND controller.
	 */
	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);

	/*
	 * Setup window for SRAM.
	 */
	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
		      TARGET_SRAM, ATTR_SRAM, -1);

	/*
	 * Setup MBUS dram target info.
	 */
	kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;

	addr = (void __iomem *)DDR_WINDOW_CPU_BASE;

	for (i = 0, cs = 0; i < 4; i++) {
		u32 base = readl(addr + DDR_BASE_CS_OFF(i));
		u32 size = readl(addr + DDR_SIZE_CS_OFF(i));

		/*
		 * Chip select enabled?
		 */
		if (size & 1) {
			struct mbus_dram_window *w;

			w = &kirkwood_mbus_dram_info.cs[cs++];
			w->cs_index = i;
			w->mbus_attr = 0xf & ~(1 << i);
			w->base = base & 0xffff0000;
			w->size = (size | 0x0000ffff) + 1;
		}
	}
	kirkwood_mbus_dram_info.num_cs = cs;
}
Commit	Line	Data
651c74c7 SB	1	/*
	2	* arch/arm/mach-kirkwood/addr-map.c
	3	*
	4	* Address map functions for Marvell Kirkwood SoCs
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/mbus.h>
	14	#include <linux/io.h>
a09e64fb	15	#include <mach/hardware.h>
651c74c7 SB	16	#include "common.h"
	17
	18	/*
	19	* Generic Address Decode Windows bit settings
	20	*/
	21	#define TARGET_DDR 0
	22	#define TARGET_DEV_BUS 1
c1191b0e	23	#define TARGET_SRAM 3
651c74c7 SB	24	#define TARGET_PCIE 4
	25	#define ATTR_DEV_SPI_ROM 0x1e
	26	#define ATTR_DEV_BOOT 0x1d
	27	#define ATTR_DEV_NAND 0x2f
	28	#define ATTR_DEV_CS3 0x37
	29	#define ATTR_DEV_CS2 0x3b
	30	#define ATTR_DEV_CS1 0x3d
	31	#define ATTR_DEV_CS0 0x3e
	32	#define ATTR_PCIE_IO 0xe0
	33	#define ATTR_PCIE_MEM 0xe8
c1191b0e	34	#define ATTR_SRAM 0x01
651c74c7 SB	35
	36	/*
	37	* Helpers to get DDR bank info
	38	*/
	39	#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
	40	#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
	41
	42	/*
	43	* CPU Address Decode Windows registers
	44	*/
	45	#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
	46	#define WIN_CTRL_OFF 0x0000
	47	#define WIN_BASE_OFF 0x0004
	48	#define WIN_REMAP_LO_OFF 0x0008
	49	#define WIN_REMAP_HI_OFF 0x000c
	50
	51
	52	struct mbus_dram_target_info kirkwood_mbus_dram_info;
	53
	54	static int __init cpu_win_can_remap(int win)
	55	{
	56	if (win < 4)
	57	return 1;
	58
	59	return 0;
	60	}
	61
	62	static void __init setup_cpu_win(int win, u32 base, u32 size,
	63	u8 target, u8 attr, int remap)
	64	{
	65	void __iomem addr = (void __iomem )WIN_OFF(win);
	66	u32 ctrl;
	67
	68	base &= 0xffff0000;
	69	ctrl = ((size - 1) & 0xffff0000) \| (attr << 8) \| (target << 4) \| 1;
	70
	71	writel(base, addr + WIN_BASE_OFF);
	72	writel(ctrl, addr + WIN_CTRL_OFF);
	73	if (cpu_win_can_remap(win)) {
	74	if (remap < 0)
	75	remap = base;
	76
	77	writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
	78	writel(0, addr + WIN_REMAP_HI_OFF);
	79	}
	80	}
	81
	82	void __init kirkwood_setup_cpu_mbus(void)
	83	{
	84	void __iomem *addr;
	85	int i;
	86	int cs;
	87
	88	/*
	89	* First, disable and clear windows.
	90	*/
	91	for (i = 0; i < 8; i++) {
	92	addr = (void __iomem *)WIN_OFF(i);
	93
	94	writel(0, addr + WIN_BASE_OFF);
	95	writel(0, addr + WIN_CTRL_OFF);
	96	if (cpu_win_can_remap(i)) {
	97	writel(0, addr + WIN_REMAP_LO_OFF);
	98	writel(0, addr + WIN_REMAP_HI_OFF);
99	}
100	}
101
102	/*
103	* Setup windows for PCIe IO+MEM space.
104	*/
105	setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
106	TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
107	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
a1897fa6	108	TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
651c74c7 SB	109
	110	/*
	111	* Setup window for NAND controller.
	112	*/
	113	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
	114	TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
	115
c1191b0e NP	116	/*
	117	* Setup window for SRAM.
	118	*/
	119	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
	120	TARGET_SRAM, ATTR_SRAM, -1);
2d0c9e73	121
651c74c7 SB	122	/*
	123	* Setup MBUS dram target info.
	124	*/
	125	kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
	126
	127	addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
	128
	129	for (i = 0, cs = 0; i < 4; i++) {
	130	u32 base = readl(addr + DDR_BASE_CS_OFF(i));
	131	u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
	132
	133	/*
	134	* Chip select enabled?
	135	*/
	136	if (size & 1) {
	137	struct mbus_dram_window *w;
	138
	139	w = &kirkwood_mbus_dram_info.cs[cs++];
	140	w->cs_index = i;
	141	w->mbus_attr = 0xf & ~(1 << i);
	142	w->base = base & 0xffff0000;
	143	w->size = (size \| 0x0000ffff) + 1;
	144	}
	145	}
	146	kirkwood_mbus_dram_info.num_cs = cs;
	147	}