[net-next-2.6.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sysdev.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>

#include <asm/clkdev.h>
#include <mach/clkdev.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst.h>

#include <mach/cm.h>
#include <mach/lm.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include <plat/timer-sp.h>

#define INTCP_PA_FLASH_BASE		0x24000000
#define INTCP_FLASH_SIZE		SZ_32M

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_VA_CIC_BASE		IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
#define INTCP_VA_PIC_BASE		IO_ADDRESS(INTEGRATOR_IC_BASE)
#define INTCP_VA_SIC_BASE		IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)

#define INTCP_ETH_SIZE			0x10

#define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 * fcb00000	cb000000	CP system control
 */

static struct map_desc intcp_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

#define cic_writel	__raw_writel
#define cic_readl	__raw_readl
#define pic_writel	__raw_writel
#define pic_readl	__raw_readl
#define sic_writel	__raw_writel
#define sic_readl	__raw_readl

static void cic_mask_irq(unsigned int irq)
{
	irq -= IRQ_CIC_START;
	cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
}

static void cic_unmask_irq(unsigned int irq)
{
	irq -= IRQ_CIC_START;
	cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
}

static struct irq_chip cic_chip = {
	.name	= "CIC",
	.ack	= cic_mask_irq,
	.mask	= cic_mask_irq,
	.unmask	= cic_unmask_irq,
};

static void pic_mask_irq(unsigned int irq)
{
	irq -= IRQ_PIC_START;
	pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
}

static void pic_unmask_irq(unsigned int irq)
{
	irq -= IRQ_PIC_START;
	pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
}

static struct irq_chip pic_chip = {
	.name	= "PIC",
	.ack	= pic_mask_irq,
	.mask	= pic_mask_irq,
	.unmask = pic_unmask_irq,
};

static void sic_mask_irq(unsigned int irq)
{
	irq -= IRQ_SIC_START;
	sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
}

static void sic_unmask_irq(unsigned int irq)
{
	irq -= IRQ_SIC_START;
	sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
}

static struct irq_chip sic_chip = {
	.name	= "SIC",
	.ack	= sic_mask_irq,
	.mask	= sic_mask_irq,
	.unmask	= sic_unmask_irq,
};

static void
sic_handle_irq(unsigned int irq, struct irq_desc *desc)
{
	unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);

	if (status == 0) {
		do_bad_IRQ(irq, desc);
		return;
	}

	do {
		irq = ffs(status) - 1;
		status &= ~(1 << irq);

		irq += IRQ_SIC_START;

		generic_handle_irq(irq);
	} while (status);
}

static void __init intcp_init_irq(void)
{
	unsigned int i;

	/*
	 * Disable all interrupt sources
	 */
	pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);

	for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
		if (i == 11)
			i = 22;
		if (i == 29)
			break;
		set_irq_chip(i, &pic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);

	for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
		set_irq_chip(i, &cic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);

	for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
		set_irq_chip(i, &sic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
}

/*
 * Clock handling
 */
#define CM_LOCK		(__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
#define CM_AUXOSC	(__io_address(INTEGRATOR_HDR_BASE)+0x1c)

static const struct icst_params cp_auxvco_params = {
	.ref		= 24000000,
	.vco_max	= ICST525_VCO_MAX_5V,
	.vco_min	= ICST525_VCO_MIN,
	.vd_min 	= 8,
	.vd_max 	= 263,
	.rd_min 	= 3,
	.rd_max 	= 65,
	.s2div		= icst525_s2div,
	.idx2s		= icst525_idx2s,
};

static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
{
	u32 val;

	val = readl(clk->vcoreg) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, CM_LOCK);
	writel(val, clk->vcoreg);
	writel(0, CM_LOCK);
}

static struct clk cp_auxclk = {
	.params	= &cp_auxvco_params,
	.vcoreg	= CM_AUXOSC,
	.setvco = cp_auxvco_set,
};

static struct clk_lookup cp_lookups[] = {
	{	/* CLCD */
		.dev_id		= "mb:c0",
		.clk		= &cp_auxclk,
	},
};

/*
 * Flash handling.
 */
static int intcp_flash_init(void)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(void)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(int on)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static struct flash_platform_data intcp_flash_data = {
	.map_name	= "cfi_probe",
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

static struct resource intcp_flash_resource = {
	.start		= INTCP_PA_FLASH_BASE,
	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device intcp_flash_device = {
	.name		= "armflash",
	.id		= 0,
	.dev		= {
		.platform_data	= &intcp_flash_data,
	},
	.num_resources	= 1,
	.resource	= &intcp_flash_resource,
};

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= INTEGRATOR_CP_ETH_BASE,
		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_CP_ETHINT,
		.end	= IRQ_CP_ETHINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static struct platform_device *intcp_devs[] __initdata = {
	&intcp_flash_device,
	&smc91x_device,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

static struct amba_device mmc_device = {
	.dev		= {
		.init_name = "mb:1c",
		.platform_data = &mmc_data,
	},
	.res		= {
		.start	= INTEGRATOR_CP_MMC_BASE,
		.end	= INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
	.periphid	= 0,
};

static struct amba_device aaci_device = {
	.dev		= {
		.init_name = "mb:1d",
	},
	.res		= {
		.start	= INTEGRATOR_CP_AACI_BASE,
		.end	= INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_CP_AACIINT, NO_IRQ },
	.periphid	= 0,
};


/*
 * CLCD support
 */
static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
	.bpp		= 16,
	.grayscale	= 0,
};

/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	u32 val;

	if (fb->fb.var.bits_per_pixel <= 8)
		val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
	else if (fb->fb.var.bits_per_pixel <= 16)
		val = CM_CTRL_LCDMUXSEL_VGA_16BPP
			| CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
			| CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static unsigned long framesize = SZ_1M;

static int cp_clcd_setup(struct clcd_fb *fb)
{
	dma_addr_t dma;

	fb->panel = &vga;

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void cp_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= cp_clcd_mmap,
	.remove		= cp_clcd_remove,
};

static struct amba_device clcd_device = {
	.dev		= {
		.init_name = "mb:c0",
		.coherent_dma_mask = ~0,
		.platform_data = &clcd_data,
	},
	.res		= {
		.start	= INTCP_PA_CLCD_BASE,
		.end	= INTCP_PA_CLCD_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.dma_mask	= ~0,
	.irq		= { IRQ_CP_CLCDCINT, NO_IRQ },
	.periphid	= 0,
};

static struct amba_device *amba_devs[] __initdata = {
	&mmc_device,
	&aaci_device,
	&clcd_device,
};

static void __init intcp_init(void)
{
	int i;

	clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
}

#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)

static void __init intcp_timer_init(void)
{
	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	writel(0, TIMER2_VA_BASE + TIMER_CTRL);

	sp804_clocksource_init(TIMER2_VA_BASE);
	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
}

static struct sys_timer cp_timer = {
	.init		= intcp_timer_init,
};

MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.phys_io	= 0x16000000,
	.io_pg_offst	= ((0xf1600000) >> 18) & 0xfffc,
	.boot_params	= 0x00000100,
	.map_io		= intcp_map_io,
	.init_irq	= intcp_init_irq,
	.timer		= &cp_timer,
	.init_machine	= intcp_init,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4 LT	15	#include <linux/dma-mapping.h>
	16	#include <linux/slab.h>
	17	#include <linux/string.h>
	18	#include <linux/sysdev.h>
a62c80e5 RK	19	#include <linux/amba/bus.h>
	20	#include <linux/amba/kmi.h>
	21	#include <linux/amba/clcd.h>
6ef297f8	22	#include <linux/amba/mmci.h>
fced80c7	23	#include <linux/io.h>
1da177e4	24
d72fbdf0 RK	25	#include <asm/clkdev.h>
d72fbdf0 RK	26	#include <mach/clkdev.h>
a09e64fb	27	#include <mach/hardware.h>
a285edcf	28	#include <mach/platform.h>
1da177e4 LT	29	#include <asm/irq.h>
	30	#include <asm/setup.h>
	31	#include <asm/mach-types.h>
5a46334a	32	#include <asm/hardware/arm_timer.h>
c5a0adb5	33	#include <asm/hardware/icst.h>
1da177e4	34
a09e64fb RK	35	#include <mach/cm.h>
a09e64fb RK	36	#include <mach/lm.h>
1da177e4 LT	37
	38	#include <asm/mach/arch.h>
	39	#include <asm/mach/flash.h>
	40	#include <asm/mach/irq.h>
1da177e4 LT	41	#include <asm/mach/map.h>
	42	#include <asm/mach/time.h>
	43
5a46334a RK	44	#include <plat/timer-sp.h>
5a46334a RK	45
1da177e4 LT	46	#define INTCP_PA_FLASH_BASE 0x24000000
	47	#define INTCP_FLASH_SIZE SZ_32M
	48
	49	#define INTCP_PA_CLCD_BASE 0xc0000000
	50
b830b9b5	51	#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
365f7a43	52	#define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
da7ba956	53	#define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
1da177e4	54
1da177e4 LT	55	#define INTCP_ETH_SIZE 0x10
1da177e4 LT	56
da7ba956	57	#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
1da177e4 LT	58	#define INTCP_FLASHPROG 0x04
	59	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	60	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	61
	62	/*
	63	* Logical Physical
	64	* f1000000 10000000 Core module registers
	65	* f1100000 11000000 System controller registers
	66	* f1200000 12000000 EBI registers
	67	* f1300000 13000000 Counter/Timer
	68	* f1400000 14000000 Interrupt controller
	69	* f1600000 16000000 UART 0
	70	* f1700000 17000000 UART 1
	71	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	72	* fc900000 c9000000 GPIO
	73	* fca00000 ca000000 SIC
	74	* fcb00000 cb000000 CP system control
1da177e4 LT	75	*/
	76
	77	static struct map_desc intcp_io_desc[] __initdata = {
c8d27298 DS	78	{
	79	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	80	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	81	.length = SZ_4K,
	82	.type = MT_DEVICE
	83	}, {
	84	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	85	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	86	.length = SZ_4K,
	87	.type = MT_DEVICE
	88	}, {
	89	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	90	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	91	.length = SZ_4K,
	92	.type = MT_DEVICE
	93	}, {
	94	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	95	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	96	.length = SZ_4K,
	97	.type = MT_DEVICE
	98	}, {
	99	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	100	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	101	.length = SZ_4K,
	102	.type = MT_DEVICE
	103	}, {
	104	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	105	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	106	.length = SZ_4K,
	107	.type = MT_DEVICE
	108	}, {
	109	.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
	110	.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
	111	.length = SZ_4K,
	112	.type = MT_DEVICE
	113	}, {
	114	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	115	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	116	.length = SZ_4K,
	117	.type = MT_DEVICE
	118	}, {
da7ba956 RK	119	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	120	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	121	.length = SZ_4K,
	122	.type = MT_DEVICE
	123	}, {
da7ba956 RK	124	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	125	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	126	.length = SZ_4K,
	127	.type = MT_DEVICE
	128	}, {
da7ba956 RK	129	.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
da7ba956 RK	130	.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
c8d27298 DS	131	.length = SZ_4K,
	132	.type = MT_DEVICE
	133	}
1da177e4 LT	134	};
	135
	136	static void __init intcp_map_io(void)
	137	{
	138	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	139	}
	140
	141	#define cic_writel __raw_writel
	142	#define cic_readl __raw_readl
	143	#define pic_writel __raw_writel
	144	#define pic_readl __raw_readl
	145	#define sic_writel __raw_writel
	146	#define sic_readl __raw_readl
	147
	148	static void cic_mask_irq(unsigned int irq)
	149	{
	150	irq -= IRQ_CIC_START;
	151	cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	152	}
	153
	154	static void cic_unmask_irq(unsigned int irq)
	155	{
	156	irq -= IRQ_CIC_START;
	157	cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
	158	}
	159
38c677cb DB	160	static struct irq_chip cic_chip = {
38c677cb DB	161	.name = "CIC",
1da177e4 LT	162	.ack = cic_mask_irq,
	163	.mask = cic_mask_irq,
	164	.unmask = cic_unmask_irq,
	165	};
	166
	167	static void pic_mask_irq(unsigned int irq)
	168	{
	169	irq -= IRQ_PIC_START;
	170	pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	171	}
	172
	173	static void pic_unmask_irq(unsigned int irq)
	174	{
	175	irq -= IRQ_PIC_START;
	176	pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
	177	}
	178
38c677cb DB	179	static struct irq_chip pic_chip = {
38c677cb DB	180	.name = "PIC",
1da177e4 LT	181	.ack = pic_mask_irq,
	182	.mask = pic_mask_irq,
	183	.unmask = pic_unmask_irq,
	184	};
	185
	186	static void sic_mask_irq(unsigned int irq)
	187	{
	188	irq -= IRQ_SIC_START;
	189	sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	190	}
	191
	192	static void sic_unmask_irq(unsigned int irq)
	193	{
	194	irq -= IRQ_SIC_START;
	195	sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
	196	}
	197
38c677cb DB	198	static struct irq_chip sic_chip = {
38c677cb DB	199	.name = "SIC",
1da177e4 LT	200	.ack = sic_mask_irq,
	201	.mask = sic_mask_irq,
	202	.unmask = sic_unmask_irq,
	203	};
	204
	205	static void
10dd5ce2	206	sic_handle_irq(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	207	{
	208	unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
	209
	210	if (status == 0) {
0cd61b68	211	do_bad_IRQ(irq, desc);
1da177e4 LT	212	return;
	213	}
	214
	215	do {
	216	irq = ffs(status) - 1;
	217	status &= ~(1 << irq);
	218
	219	irq += IRQ_SIC_START;
	220
d8aa0251	221	generic_handle_irq(irq);
1da177e4 LT	222	} while (status);
	223	}
	224
	225	static void __init intcp_init_irq(void)
	226	{
	227	unsigned int i;
	228
	229	/*
	230	* Disable all interrupt sources
	231	*/
	232	pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	233	pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	234
	235	for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
	236	if (i == 11)
	237	i = 22;
1da177e4 LT	238	if (i == 29)
	239	break;
	240	set_irq_chip(i, &pic_chip);
10dd5ce2	241	set_irq_handler(i, handle_level_irq);
1da177e4 LT	242	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
	243	}
	244
	245	cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	246	cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	247
	248	for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
	249	set_irq_chip(i, &cic_chip);
10dd5ce2	250	set_irq_handler(i, handle_level_irq);
1da177e4 LT	251	set_irq_flags(i, IRQF_VALID);
	252	}
	253
	254	sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	255	sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
	256
	257	for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
	258	set_irq_chip(i, &sic_chip);
10dd5ce2	259	set_irq_handler(i, handle_level_irq);
1da177e4 LT	260	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
	261	}
	262
56f1319e	263	set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
1da177e4 LT	264	}
	265
	266	/*
	267	* Clock handling
	268	*/
d1914c7e RK	269	#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
d1914c7e RK	270	#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
1da177e4	271
39c0cb02	272	static const struct icst_params cp_auxvco_params = {
64fceb1d	273	.ref = 24000000,
4de2edbd	274	.vco_max = ICST525_VCO_MAX_5V,
e73a46a3	275	.vco_min = ICST525_VCO_MIN,
1da177e4 LT	276	.vd_min = 8,
	277	.vd_max = 263,
	278	.rd_min = 3,
	279	.rd_max = 65,
232eaf7f RK	280	.s2div = icst525_s2div,
232eaf7f RK	281	.idx2s = icst525_idx2s,
1da177e4 LT	282	};
1da177e4 LT	283
39c0cb02	284	static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
1da177e4 LT	285	{
	286	u32 val;
	287
d1914c7e	288	val = readl(clk->vcoreg) & ~0x7ffff;
1da177e4 LT	289	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	290
	291	writel(0xa05f, CM_LOCK);
d1914c7e	292	writel(val, clk->vcoreg);
1da177e4 LT	293	writel(0, CM_LOCK);
	294	}
	295
d72fbdf0	296	static struct clk cp_auxclk = {
1da177e4	297	.params = &cp_auxvco_params,
d1914c7e	298	.vcoreg = CM_AUXOSC,
1da177e4 LT	299	.setvco = cp_auxvco_set,
	300	};
	301
d72fbdf0 RK	302	static struct clk_lookup cp_lookups[] = {
	303	{ /* CLCD */
	304	.dev_id = "mb:c0",
	305	.clk = &cp_auxclk,
	306	},
1da177e4 LT	307	};
	308
	309	/*
	310	* Flash handling.
	311	*/
	312	static int intcp_flash_init(void)
	313	{
	314	u32 val;
	315
	316	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	317	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
	318	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	319
	320	return 0;
	321	}
	322
	323	static void intcp_flash_exit(void)
	324	{
	325	u32 val;
	326
	327	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	328	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
	329	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	330	}
	331
	332	static void intcp_flash_set_vpp(int on)
	333	{
	334	u32 val;
	335
	336	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	337	if (on)
	338	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	339	else
	340	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	341	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	342	}
	343
	344	static struct flash_platform_data intcp_flash_data = {
	345	.map_name = "cfi_probe",
	346	.width = 4,
	347	.init = intcp_flash_init,
	348	.exit = intcp_flash_exit,
	349	.set_vpp = intcp_flash_set_vpp,
	350	};
	351
	352	static struct resource intcp_flash_resource = {
	353	.start = INTCP_PA_FLASH_BASE,
	354	.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	355	.flags = IORESOURCE_MEM,
	356	};
	357
	358	static struct platform_device intcp_flash_device = {
	359	.name = "armflash",
	360	.id = 0,
	361	.dev = {
	362	.platform_data = &intcp_flash_data,
	363	},
	364	.num_resources = 1,
	365	.resource = &intcp_flash_resource,
	366	};
	367
	368	static struct resource smc91x_resources[] = {
	369	[0] = {
da7ba956 RK	370	.start = INTEGRATOR_CP_ETH_BASE,
da7ba956 RK	371	.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
1da177e4 LT	372	.flags = IORESOURCE_MEM,
	373	},
	374	[1] = {
	375	.start = IRQ_CP_ETHINT,
	376	.end = IRQ_CP_ETHINT,
	377	.flags = IORESOURCE_IRQ,
	378	},
	379	};
	380
	381	static struct platform_device smc91x_device = {
	382	.name = "smc91x",
	383	.id = 0,
	384	.num_resources = ARRAY_SIZE(smc91x_resources),
	385	.resource = smc91x_resources,
	386	};
	387
	388	static struct platform_device *intcp_devs[] __initdata = {
	389	&intcp_flash_device,
	390	&smc91x_device,
	391	};
	392
	393	/*
	394	* It seems that the card insertion interrupt remains active after
	395	* we've acknowledged it. We therefore ignore the interrupt, and
	396	* rely on reading it from the SIC. This also means that we must
	397	* clear the latched interrupt.
	398	*/
	399	static unsigned int mmc_status(struct device *dev)
	400	{
b830b9b5 RK	401	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
b830b9b5 RK	402	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
1da177e4 LT	403
	404	return status & 8;
	405	}
	406
6ef297f8	407	static struct mmci_platform_data mmc_data = {
1da177e4 LT	408	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	409	.status = mmc_status,
7fb2bbf4 RK	410	.gpio_wp = -1,
7fb2bbf4 RK	411	.gpio_cd = -1,
1da177e4 LT	412	};
	413
	414	static struct amba_device mmc_device = {
	415	.dev = {
1d559e29	416	.init_name = "mb:1c",
1da177e4 LT	417	.platform_data = &mmc_data,
	418	},
	419	.res = {
da7ba956 RK	420	.start = INTEGRATOR_CP_MMC_BASE,
da7ba956 RK	421	.end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
1da177e4 LT	422	.flags = IORESOURCE_MEM,
	423	},
	424	.irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
	425	.periphid = 0,
	426	};
	427
	428	static struct amba_device aaci_device = {
	429	.dev = {
1d559e29	430	.init_name = "mb:1d",
1da177e4 LT	431	},
1da177e4 LT	432	.res = {
da7ba956 RK	433	.start = INTEGRATOR_CP_AACI_BASE,
da7ba956 RK	434	.end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
1da177e4 LT	435	.flags = IORESOURCE_MEM,
	436	},
	437	.irq = { IRQ_CP_AACIINT, NO_IRQ },
	438	.periphid = 0,
	439	};
	440
	441
	442	/*
	443	* CLCD support
	444	*/
	445	static struct clcd_panel vga = {
	446	.mode = {
	447	.name = "VGA",
	448	.refresh = 60,
	449	.xres = 640,
	450	.yres = 480,
	451	.pixclock = 39721,
	452	.left_margin = 40,
	453	.right_margin = 24,
	454	.upper_margin = 32,
	455	.lower_margin = 11,
	456	.hsync_len = 96,
	457	.vsync_len = 2,
	458	.sync = 0,
	459	.vmode = FB_VMODE_NONINTERLACED,
	460	},
	461	.width = -1,
	462	.height = -1,
	463	.tim2 = TIM2_BCD \| TIM2_IPC,
	464	.cntl = CNTL_LCDTFT \| CNTL_LCDVCOMP(1),
	465	.bpp = 16,
	466	.grayscale = 0,
	467	};
	468
	469	/*
	470	* Ensure VGA is selected.
	471	*/
	472	static void cp_clcd_enable(struct clcd_fb *fb)
	473	{
4774e226 RK	474	u32 val;
	475
	476	if (fb->fb.var.bits_per_pixel <= 8)
	477	val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
	478	else if (fb->fb.var.bits_per_pixel <= 16)
14e54cc3 CM	479	val = CM_CTRL_LCDMUXSEL_VGA_16BPP
	480	\| CM_CTRL_LCDEN0 \| CM_CTRL_LCDEN1
	481	\| CM_CTRL_STATIC1 \| CM_CTRL_STATIC2;
4774e226 RK	482	else
	483	val = 0; /* no idea for this, don't trust the docs */
	484
	485	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	486	CM_CTRL_LCDEN0\|
	487	CM_CTRL_LCDEN1\|
	488	CM_CTRL_STATIC1\|
	489	CM_CTRL_STATIC2\|
	490	CM_CTRL_STATIC\|
	491	CM_CTRL_n24BITEN, val);
1da177e4 LT	492	}
	493
	494	static unsigned long framesize = SZ_1M;
	495
	496	static int cp_clcd_setup(struct clcd_fb *fb)
	497	{
	498	dma_addr_t dma;
	499
	500	fb->panel = &vga;
	501
	502	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	503	&dma, GFP_KERNEL);
	504	if (!fb->fb.screen_base) {
	505	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	506	return -ENOMEM;
	507	}
	508
	509	fb->fb.fix.smem_start = dma;
	510	fb->fb.fix.smem_len = framesize;
	511
	512	return 0;
	513	}
	514
	515	static int cp_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	516	{
	517	return dma_mmap_writecombine(&fb->dev->dev, vma,
	518	fb->fb.screen_base,
	519	fb->fb.fix.smem_start,
	520	fb->fb.fix.smem_len);
	521	}
	522
	523	static void cp_clcd_remove(struct clcd_fb *fb)
	524	{
	525	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	526	fb->fb.screen_base, fb->fb.fix.smem_start);
	527	}
	528
	529	static struct clcd_board clcd_data = {
	530	.name = "Integrator/CP",
	531	.check = clcdfb_check,
	532	.decode = clcdfb_decode,
	533	.enable = cp_clcd_enable,
	534	.setup = cp_clcd_setup,
	535	.mmap = cp_clcd_mmap,
	536	.remove = cp_clcd_remove,
	537	};
	538
	539	static struct amba_device clcd_device = {
	540	.dev = {
1d559e29	541	.init_name = "mb:c0",
1da177e4 LT	542	.coherent_dma_mask = ~0,
	543	.platform_data = &clcd_data,
	544	},
	545	.res = {
	546	.start = INTCP_PA_CLCD_BASE,
	547	.end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
	548	.flags = IORESOURCE_MEM,
	549	},
	550	.dma_mask = ~0,
	551	.irq = { IRQ_CP_CLCDCINT, NO_IRQ },
	552	.periphid = 0,
	553	};
	554
	555	static struct amba_device *amba_devs[] __initdata = {
	556	&mmc_device,
	557	&aaci_device,
	558	&clcd_device,
	559	};
	560
	561	static void __init intcp_init(void)
	562	{
	563	int i;
	564
0a0300dc	565	clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
1da177e4 LT	566	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
	567
	568	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
	569	struct amba_device *d = amba_devs[i];
	570	amba_device_register(d, &iomem_resource);
	571	}
	572	}
	573
5a46334a RK	574	#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
	575	#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
	576	#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
1da177e4 LT	577
	578	static void __init intcp_timer_init(void)
	579	{
5a46334a RK	580	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
	581	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
	582	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
	583
	584	sp804_clocksource_init(TIMER2_VA_BASE);
	585	sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
1da177e4 LT	586	}
	587
	588	static struct sys_timer cp_timer = {
	589	.init = intcp_timer_init,
1da177e4 LT	590	};
	591
	592	MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
e9dea0c6	593	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
e9dea0c6 RK	594	.phys_io = 0x16000000,
	595	.io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
	596	.boot_params = 0x00000100,
	597	.map_io = intcp_map_io,
	598	.init_irq = intcp_init_irq,
1da177e4	599	.timer = &cp_timer,
e9dea0c6	600	.init_machine = intcp_init,
1da177e4	601	MACHINE_END