[net-next-2.6.git] / arch / arm / mach-integrator / integrator_cp.c

/*
 *  linux/arch/arm/mach-integrator/integrator_cp.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sysdev.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
#include <linux/amba/mmci.h>
#include <linux/io.h>

#include <asm/clkdev.h>
#include <mach/clkdev.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/hardware/icst525.h>

#include <mach/cm.h>
#include <mach/lm.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>

#include "common.h"

#define INTCP_PA_FLASH_BASE		0x24000000
#define INTCP_FLASH_SIZE		SZ_32M

#define INTCP_PA_CLCD_BASE		0xc0000000

#define INTCP_VA_CIC_BASE		IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
#define INTCP_VA_PIC_BASE		IO_ADDRESS(INTEGRATOR_IC_BASE)
#define INTCP_VA_SIC_BASE		IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)

#define INTCP_ETH_SIZE			0x10

#define INTCP_VA_CTRL_BASE		IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
#define INTCP_FLASHPROG			0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN	(1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN	(1 << 1)

/*
 * Logical      Physical
 * f1000000	10000000	Core module registers
 * f1100000	11000000	System controller registers
 * f1200000	12000000	EBI registers
 * f1300000	13000000	Counter/Timer
 * f1400000	14000000	Interrupt controller
 * f1600000	16000000	UART 0
 * f1700000	17000000	UART 1
 * f1a00000	1a000000	Debug LEDs
 * fc900000	c9000000	GPIO
 * fca00000	ca000000	SIC
 * fcb00000	cb000000	CP system control
 */

static struct map_desc intcp_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(INTEGRATOR_HDR_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_HDR_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_SC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_SC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_EBI_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_EBI_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CT_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CT_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_IC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_IC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART0_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART0_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_UART1_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_UART1_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_DBG_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_DBG_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}, {
		.virtual	= IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
		.pfn		= __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE
	}
};

static void __init intcp_map_io(void)
{
	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}

#define cic_writel	__raw_writel
#define cic_readl	__raw_readl
#define pic_writel	__raw_writel
#define pic_readl	__raw_readl
#define sic_writel	__raw_writel
#define sic_readl	__raw_readl

static void cic_mask_irq(unsigned int irq)
{
	irq -= IRQ_CIC_START;
	cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
}

static void cic_unmask_irq(unsigned int irq)
{
	irq -= IRQ_CIC_START;
	cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
}

static struct irq_chip cic_chip = {
	.name	= "CIC",
	.ack	= cic_mask_irq,
	.mask	= cic_mask_irq,
	.unmask	= cic_unmask_irq,
};

static void pic_mask_irq(unsigned int irq)
{
	irq -= IRQ_PIC_START;
	pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
}

static void pic_unmask_irq(unsigned int irq)
{
	irq -= IRQ_PIC_START;
	pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
}

static struct irq_chip pic_chip = {
	.name	= "PIC",
	.ack	= pic_mask_irq,
	.mask	= pic_mask_irq,
	.unmask = pic_unmask_irq,
};

static void sic_mask_irq(unsigned int irq)
{
	irq -= IRQ_SIC_START;
	sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
}

static void sic_unmask_irq(unsigned int irq)
{
	irq -= IRQ_SIC_START;
	sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
}

static struct irq_chip sic_chip = {
	.name	= "SIC",
	.ack	= sic_mask_irq,
	.mask	= sic_mask_irq,
	.unmask	= sic_unmask_irq,
};

static void
sic_handle_irq(unsigned int irq, struct irq_desc *desc)
{
	unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);

	if (status == 0) {
		do_bad_IRQ(irq, desc);
		return;
	}

	do {
		irq = ffs(status) - 1;
		status &= ~(1 << irq);

		irq += IRQ_SIC_START;

		generic_handle_irq(irq);
	} while (status);
}

static void __init intcp_init_irq(void)
{
	unsigned int i;

	/*
	 * Disable all interrupt sources
	 */
	pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);

	for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
		if (i == 11)
			i = 22;
		if (i == 29)
			break;
		set_irq_chip(i, &pic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);

	for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
		set_irq_chip(i, &cic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);

	for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
		set_irq_chip(i, &sic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
}

/*
 * Clock handling
 */
#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
#define CM_AUXOSC IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x1c)

static const struct icst_params cp_auxvco_params = {
	.ref		= 24000000,
	.vco_max	= ICST525_VCO_MAX_5V,
	.vco_min	= ICST525_VCO_MIN,
	.vd_min 	= 8,
	.vd_max 	= 263,
	.rd_min 	= 3,
	.rd_max 	= 65,
	.s2div		= icst525_s2div,
	.idx2s		= icst525_idx2s,
};

static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
{
	u32 val;

	val = readl(CM_AUXOSC) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, CM_LOCK);
	writel(val, CM_AUXOSC);
	writel(0, CM_LOCK);
}

static struct clk cp_auxclk = {
	.params	= &cp_auxvco_params,
	.setvco = cp_auxvco_set,
};

static struct clk_lookup cp_lookups[] = {
	{	/* CLCD */
		.dev_id		= "mb:c0",
		.clk		= &cp_auxclk,
	},
};

/*
 * Flash handling.
 */
static int intcp_flash_init(void)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val |= CINTEGRATOR_FLASHPROG_FLWREN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);

	return 0;
}

static void intcp_flash_exit(void)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static void intcp_flash_set_vpp(int on)
{
	u32 val;

	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	if (on)
		val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
	else
		val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}

static struct flash_platform_data intcp_flash_data = {
	.map_name	= "cfi_probe",
	.width		= 4,
	.init		= intcp_flash_init,
	.exit		= intcp_flash_exit,
	.set_vpp	= intcp_flash_set_vpp,
};

static struct resource intcp_flash_resource = {
	.start		= INTCP_PA_FLASH_BASE,
	.end		= INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device intcp_flash_device = {
	.name		= "armflash",
	.id		= 0,
	.dev		= {
		.platform_data	= &intcp_flash_data,
	},
	.num_resources	= 1,
	.resource	= &intcp_flash_resource,
};

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= INTEGRATOR_CP_ETH_BASE,
		.end	= INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_CP_ETHINT,
		.end	= IRQ_CP_ETHINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
};

static struct platform_device *intcp_devs[] __initdata = {
	&intcp_flash_device,
	&smc91x_device,
};

/*
 * It seems that the card insertion interrupt remains active after
 * we've acknowledged it.  We therefore ignore the interrupt, and
 * rely on reading it from the SIC.  This also means that we must
 * clear the latched interrupt.
 */
static unsigned int mmc_status(struct device *dev)
{
	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));

	return status & 8;
}

static struct mmci_platform_data mmc_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= mmc_status,
	.gpio_wp	= -1,
	.gpio_cd	= -1,
};

static struct amba_device mmc_device = {
	.dev		= {
		.init_name = "mb:1c",
		.platform_data = &mmc_data,
	},
	.res		= {
		.start	= INTEGRATOR_CP_MMC_BASE,
		.end	= INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
	.periphid	= 0,
};

static struct amba_device aaci_device = {
	.dev		= {
		.init_name = "mb:1d",
	},
	.res		= {
		.start	= INTEGRATOR_CP_AACI_BASE,
		.end	= INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_CP_AACIINT, NO_IRQ },
	.periphid	= 0,
};


/*
 * CLCD support
 */
static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_LCDVCOMP(1),
	.bpp		= 16,
	.grayscale	= 0,
};

/*
 * Ensure VGA is selected.
 */
static void cp_clcd_enable(struct clcd_fb *fb)
{
	u32 val;

	if (fb->fb.var.bits_per_pixel <= 8)
		val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
	else if (fb->fb.var.bits_per_pixel <= 16)
		val = CM_CTRL_LCDMUXSEL_VGA_16BPP
			| CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
			| CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
	else
		val = 0; /* no idea for this, don't trust the docs */

	cm_control(CM_CTRL_LCDMUXSEL_MASK|
		   CM_CTRL_LCDEN0|
		   CM_CTRL_LCDEN1|
		   CM_CTRL_STATIC1|
		   CM_CTRL_STATIC2|
		   CM_CTRL_STATIC|
		   CM_CTRL_n24BITEN, val);
}

static unsigned long framesize = SZ_1M;

static int cp_clcd_setup(struct clcd_fb *fb)
{
	dma_addr_t dma;

	fb->panel = &vga;

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void cp_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

static struct clcd_board clcd_data = {
	.name		= "Integrator/CP",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.enable		= cp_clcd_enable,
	.setup		= cp_clcd_setup,
	.mmap		= cp_clcd_mmap,
	.remove		= cp_clcd_remove,
};

static struct amba_device clcd_device = {
	.dev		= {
		.init_name = "mb:c0",
		.coherent_dma_mask = ~0,
		.platform_data = &clcd_data,
	},
	.res		= {
		.start	= INTCP_PA_CLCD_BASE,
		.end	= INTCP_PA_CLCD_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	},
	.dma_mask	= ~0,
	.irq		= { IRQ_CP_CLCDCINT, NO_IRQ },
	.periphid	= 0,
};

static struct amba_device *amba_devs[] __initdata = {
	&mmc_device,
	&aaci_device,
	&clcd_device,
};

static void __init intcp_init(void)
{
	int i;

	clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
}

#define TIMER_CTRL_IE	(1 << 5)			/* Interrupt Enable */

static void __init intcp_timer_init(void)
{
	integrator_time_init(1000, TIMER_CTRL_IE);
}

static struct sys_timer cp_timer = {
	.init		= intcp_timer_init,
};

MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
	.phys_io	= 0x16000000,
	.io_pg_offst	= ((0xf1600000) >> 18) & 0xfffc,
	.boot_params	= 0x00000100,
	.map_io		= intcp_map_io,
	.init_irq	= intcp_init_irq,
	.timer		= &cp_timer,
	.init_machine	= intcp_init,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-integrator/integrator_cp.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*/
	10	#include <linux/types.h>
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/list.h>
d052d1be	14	#include <linux/platform_device.h>
1da177e4 LT	15	#include <linux/dma-mapping.h>
	16	#include <linux/slab.h>
	17	#include <linux/string.h>
	18	#include <linux/sysdev.h>
a62c80e5 RK	19	#include <linux/amba/bus.h>
	20	#include <linux/amba/kmi.h>
	21	#include <linux/amba/clcd.h>
6ef297f8	22	#include <linux/amba/mmci.h>
fced80c7	23	#include <linux/io.h>
1da177e4	24
d72fbdf0 RK	25	#include <asm/clkdev.h>
d72fbdf0 RK	26	#include <mach/clkdev.h>
a09e64fb	27	#include <mach/hardware.h>
a285edcf	28	#include <mach/platform.h>
1da177e4 LT	29	#include <asm/irq.h>
	30	#include <asm/setup.h>
	31	#include <asm/mach-types.h>
1da177e4 LT	32	#include <asm/hardware/icst525.h>
1da177e4 LT	33
a09e64fb RK	34	#include <mach/cm.h>
a09e64fb RK	35	#include <mach/lm.h>
1da177e4 LT	36
	37	#include <asm/mach/arch.h>
	38	#include <asm/mach/flash.h>
	39	#include <asm/mach/irq.h>
1da177e4 LT	40	#include <asm/mach/map.h>
	41	#include <asm/mach/time.h>
	42
	43	#include "common.h"
1da177e4	44
1da177e4 LT	45	#define INTCP_PA_FLASH_BASE 0x24000000
	46	#define INTCP_FLASH_SIZE SZ_32M
	47
	48	#define INTCP_PA_CLCD_BASE 0xc0000000
	49
b830b9b5	50	#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
365f7a43	51	#define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
da7ba956	52	#define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
1da177e4	53
1da177e4 LT	54	#define INTCP_ETH_SIZE 0x10
1da177e4 LT	55
da7ba956	56	#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
1da177e4 LT	57	#define INTCP_FLASHPROG 0x04
	58	#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
	59	#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
	60
	61	/*
	62	* Logical Physical
	63	* f1000000 10000000 Core module registers
	64	* f1100000 11000000 System controller registers
	65	* f1200000 12000000 EBI registers
	66	* f1300000 13000000 Counter/Timer
	67	* f1400000 14000000 Interrupt controller
	68	* f1600000 16000000 UART 0
	69	* f1700000 17000000 UART 1
	70	* f1a00000 1a000000 Debug LEDs
da7ba956 RK	71	* fc900000 c9000000 GPIO
	72	* fca00000 ca000000 SIC
	73	* fcb00000 cb000000 CP system control
1da177e4 LT	74	*/
	75
	76	static struct map_desc intcp_io_desc[] __initdata = {
c8d27298 DS	77	{
	78	.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
	79	.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
	80	.length = SZ_4K,
	81	.type = MT_DEVICE
	82	}, {
	83	.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
	84	.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
	85	.length = SZ_4K,
	86	.type = MT_DEVICE
	87	}, {
	88	.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
	89	.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
	90	.length = SZ_4K,
	91	.type = MT_DEVICE
	92	}, {
	93	.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
	94	.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
	95	.length = SZ_4K,
	96	.type = MT_DEVICE
	97	}, {
	98	.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
	99	.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
	100	.length = SZ_4K,
	101	.type = MT_DEVICE
	102	}, {
	103	.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
	104	.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
	105	.length = SZ_4K,
	106	.type = MT_DEVICE
	107	}, {
	108	.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
	109	.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
	110	.length = SZ_4K,
	111	.type = MT_DEVICE
	112	}, {
	113	.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
	114	.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
	115	.length = SZ_4K,
	116	.type = MT_DEVICE
	117	}, {
da7ba956 RK	118	.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
da7ba956 RK	119	.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
c8d27298 DS	120	.length = SZ_4K,
	121	.type = MT_DEVICE
	122	}, {
da7ba956 RK	123	.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
da7ba956 RK	124	.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
c8d27298 DS	125	.length = SZ_4K,
	126	.type = MT_DEVICE
	127	}, {
da7ba956 RK	128	.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
da7ba956 RK	129	.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
c8d27298 DS	130	.length = SZ_4K,
	131	.type = MT_DEVICE
	132	}
1da177e4 LT	133	};
	134
	135	static void __init intcp_map_io(void)
	136	{
	137	iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
	138	}
	139
	140	#define cic_writel __raw_writel
	141	#define cic_readl __raw_readl
	142	#define pic_writel __raw_writel
	143	#define pic_readl __raw_readl
	144	#define sic_writel __raw_writel
	145	#define sic_readl __raw_readl
	146
	147	static void cic_mask_irq(unsigned int irq)
	148	{
	149	irq -= IRQ_CIC_START;
	150	cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	151	}
	152
	153	static void cic_unmask_irq(unsigned int irq)
	154	{
	155	irq -= IRQ_CIC_START;
	156	cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
	157	}
	158
38c677cb DB	159	static struct irq_chip cic_chip = {
38c677cb DB	160	.name = "CIC",
1da177e4 LT	161	.ack = cic_mask_irq,
	162	.mask = cic_mask_irq,
	163	.unmask = cic_unmask_irq,
	164	};
	165
	166	static void pic_mask_irq(unsigned int irq)
	167	{
	168	irq -= IRQ_PIC_START;
	169	pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	170	}
	171
	172	static void pic_unmask_irq(unsigned int irq)
	173	{
	174	irq -= IRQ_PIC_START;
	175	pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
	176	}
	177
38c677cb DB	178	static struct irq_chip pic_chip = {
38c677cb DB	179	.name = "PIC",
1da177e4 LT	180	.ack = pic_mask_irq,
	181	.mask = pic_mask_irq,
	182	.unmask = pic_unmask_irq,
	183	};
	184
	185	static void sic_mask_irq(unsigned int irq)
	186	{
	187	irq -= IRQ_SIC_START;
	188	sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	189	}
	190
	191	static void sic_unmask_irq(unsigned int irq)
	192	{
	193	irq -= IRQ_SIC_START;
	194	sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
	195	}
	196
38c677cb DB	197	static struct irq_chip sic_chip = {
38c677cb DB	198	.name = "SIC",
1da177e4 LT	199	.ack = sic_mask_irq,
	200	.mask = sic_mask_irq,
	201	.unmask = sic_unmask_irq,
	202	};
	203
	204	static void
10dd5ce2	205	sic_handle_irq(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	206	{
	207	unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
	208
	209	if (status == 0) {
0cd61b68	210	do_bad_IRQ(irq, desc);
1da177e4 LT	211	return;
	212	}
	213
	214	do {
	215	irq = ffs(status) - 1;
	216	status &= ~(1 << irq);
	217
	218	irq += IRQ_SIC_START;
	219
d8aa0251	220	generic_handle_irq(irq);
1da177e4 LT	221	} while (status);
	222	}
	223
	224	static void __init intcp_init_irq(void)
	225	{
	226	unsigned int i;
	227
	228	/*
	229	* Disable all interrupt sources
	230	*/
	231	pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
	232	pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
	233
	234	for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
	235	if (i == 11)
	236	i = 22;
1da177e4 LT	237	if (i == 29)
	238	break;
	239	set_irq_chip(i, &pic_chip);
10dd5ce2	240	set_irq_handler(i, handle_level_irq);
1da177e4 LT	241	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
	242	}
	243
	244	cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
	245	cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
	246
	247	for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
	248	set_irq_chip(i, &cic_chip);
10dd5ce2	249	set_irq_handler(i, handle_level_irq);
1da177e4 LT	250	set_irq_flags(i, IRQF_VALID);
	251	}
	252
	253	sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
	254	sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
	255
	256	for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
	257	set_irq_chip(i, &sic_chip);
10dd5ce2	258	set_irq_handler(i, handle_level_irq);
1da177e4 LT	259	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
	260	}
	261
56f1319e	262	set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
1da177e4 LT	263	}
	264
	265	/*
	266	* Clock handling
	267	*/
b830b9b5 RK	268	#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
b830b9b5 RK	269	#define CM_AUXOSC IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x1c)
1da177e4	270
39c0cb02	271	static const struct icst_params cp_auxvco_params = {
64fceb1d	272	.ref = 24000000,
4de2edbd	273	.vco_max = ICST525_VCO_MAX_5V,
e73a46a3	274	.vco_min = ICST525_VCO_MIN,
1da177e4 LT	275	.vd_min = 8,
	276	.vd_max = 263,
	277	.rd_min = 3,
	278	.rd_max = 65,
232eaf7f RK	279	.s2div = icst525_s2div,
232eaf7f RK	280	.idx2s = icst525_idx2s,
1da177e4 LT	281	};
1da177e4 LT	282
39c0cb02	283	static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
1da177e4 LT	284	{
	285	u32 val;
	286
	287	val = readl(CM_AUXOSC) & ~0x7ffff;
	288	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	289
	290	writel(0xa05f, CM_LOCK);
	291	writel(val, CM_AUXOSC);
	292	writel(0, CM_LOCK);
	293	}
	294
d72fbdf0	295	static struct clk cp_auxclk = {
1da177e4 LT	296	.params = &cp_auxvco_params,
	297	.setvco = cp_auxvco_set,
	298	};
	299
d72fbdf0 RK	300	static struct clk_lookup cp_lookups[] = {
	301	{ /* CLCD */
	302	.dev_id = "mb:c0",
	303	.clk = &cp_auxclk,
	304	},
1da177e4 LT	305	};
	306
	307	/*
	308	* Flash handling.
	309	*/
	310	static int intcp_flash_init(void)
	311	{
	312	u32 val;
	313
	314	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	315	val \|= CINTEGRATOR_FLASHPROG_FLWREN;
	316	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	317
	318	return 0;
	319	}
	320
	321	static void intcp_flash_exit(void)
	322	{
	323	u32 val;
	324
	325	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	326	val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN\|CINTEGRATOR_FLASHPROG_FLWREN);
	327	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	328	}
	329
	330	static void intcp_flash_set_vpp(int on)
	331	{
	332	u32 val;
	333
	334	val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	335	if (on)
	336	val \|= CINTEGRATOR_FLASHPROG_FLVPPEN;
	337	else
	338	val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
	339	writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
	340	}
	341
	342	static struct flash_platform_data intcp_flash_data = {
	343	.map_name = "cfi_probe",
	344	.width = 4,
	345	.init = intcp_flash_init,
	346	.exit = intcp_flash_exit,
	347	.set_vpp = intcp_flash_set_vpp,
	348	};
	349
	350	static struct resource intcp_flash_resource = {
	351	.start = INTCP_PA_FLASH_BASE,
	352	.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
	353	.flags = IORESOURCE_MEM,
	354	};
	355
	356	static struct platform_device intcp_flash_device = {
	357	.name = "armflash",
	358	.id = 0,
	359	.dev = {
	360	.platform_data = &intcp_flash_data,
	361	},
	362	.num_resources = 1,
	363	.resource = &intcp_flash_resource,
	364	};
	365
	366	static struct resource smc91x_resources[] = {
	367	[0] = {
da7ba956 RK	368	.start = INTEGRATOR_CP_ETH_BASE,
da7ba956 RK	369	.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
1da177e4 LT	370	.flags = IORESOURCE_MEM,
	371	},
	372	[1] = {
	373	.start = IRQ_CP_ETHINT,
	374	.end = IRQ_CP_ETHINT,
	375	.flags = IORESOURCE_IRQ,
	376	},
	377	};
	378
	379	static struct platform_device smc91x_device = {
	380	.name = "smc91x",
	381	.id = 0,
	382	.num_resources = ARRAY_SIZE(smc91x_resources),
	383	.resource = smc91x_resources,
	384	};
	385
	386	static struct platform_device *intcp_devs[] __initdata = {
	387	&intcp_flash_device,
	388	&smc91x_device,
	389	};
	390
	391	/*
	392	* It seems that the card insertion interrupt remains active after
	393	* we've acknowledged it. We therefore ignore the interrupt, and
	394	* rely on reading it from the SIC. This also means that we must
	395	* clear the latched interrupt.
	396	*/
	397	static unsigned int mmc_status(struct device *dev)
	398	{
b830b9b5 RK	399	unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
b830b9b5 RK	400	writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
1da177e4 LT	401
	402	return status & 8;
	403	}
	404
6ef297f8	405	static struct mmci_platform_data mmc_data = {
1da177e4 LT	406	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
1da177e4 LT	407	.status = mmc_status,
7fb2bbf4 RK	408	.gpio_wp = -1,
7fb2bbf4 RK	409	.gpio_cd = -1,
1da177e4 LT	410	};
	411
	412	static struct amba_device mmc_device = {
	413	.dev = {
1d559e29	414	.init_name = "mb:1c",
1da177e4 LT	415	.platform_data = &mmc_data,
	416	},
	417	.res = {
da7ba956 RK	418	.start = INTEGRATOR_CP_MMC_BASE,
da7ba956 RK	419	.end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
1da177e4 LT	420	.flags = IORESOURCE_MEM,
	421	},
	422	.irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
	423	.periphid = 0,
	424	};
	425
	426	static struct amba_device aaci_device = {
	427	.dev = {
1d559e29	428	.init_name = "mb:1d",
1da177e4 LT	429	},
1da177e4 LT	430	.res = {
da7ba956 RK	431	.start = INTEGRATOR_CP_AACI_BASE,
da7ba956 RK	432	.end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
1da177e4 LT	433	.flags = IORESOURCE_MEM,
	434	},
	435	.irq = { IRQ_CP_AACIINT, NO_IRQ },
	436	.periphid = 0,
	437	};
	438
	439
	440	/*
	441	* CLCD support
	442	*/
	443	static struct clcd_panel vga = {
	444	.mode = {
	445	.name = "VGA",
	446	.refresh = 60,
	447	.xres = 640,
	448	.yres = 480,
	449	.pixclock = 39721,
	450	.left_margin = 40,
	451	.right_margin = 24,
	452	.upper_margin = 32,
	453	.lower_margin = 11,
	454	.hsync_len = 96,
	455	.vsync_len = 2,
	456	.sync = 0,
	457	.vmode = FB_VMODE_NONINTERLACED,
	458	},
	459	.width = -1,
	460	.height = -1,
	461	.tim2 = TIM2_BCD \| TIM2_IPC,
	462	.cntl = CNTL_LCDTFT \| CNTL_LCDVCOMP(1),
	463	.bpp = 16,
	464	.grayscale = 0,
	465	};
	466
	467	/*
	468	* Ensure VGA is selected.
	469	*/
	470	static void cp_clcd_enable(struct clcd_fb *fb)
	471	{
4774e226 RK	472	u32 val;
	473
	474	if (fb->fb.var.bits_per_pixel <= 8)
	475	val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
	476	else if (fb->fb.var.bits_per_pixel <= 16)
14e54cc3 CM	477	val = CM_CTRL_LCDMUXSEL_VGA_16BPP
	478	\| CM_CTRL_LCDEN0 \| CM_CTRL_LCDEN1
	479	\| CM_CTRL_STATIC1 \| CM_CTRL_STATIC2;
4774e226 RK	480	else
	481	val = 0; /* no idea for this, don't trust the docs */
	482
	483	cm_control(CM_CTRL_LCDMUXSEL_MASK\|
	484	CM_CTRL_LCDEN0\|
	485	CM_CTRL_LCDEN1\|
	486	CM_CTRL_STATIC1\|
	487	CM_CTRL_STATIC2\|
	488	CM_CTRL_STATIC\|
	489	CM_CTRL_n24BITEN, val);
1da177e4 LT	490	}
	491
	492	static unsigned long framesize = SZ_1M;
	493
	494	static int cp_clcd_setup(struct clcd_fb *fb)
	495	{
	496	dma_addr_t dma;
	497
	498	fb->panel = &vga;
	499
	500	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	501	&dma, GFP_KERNEL);
	502	if (!fb->fb.screen_base) {
	503	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	504	return -ENOMEM;
	505	}
	506
	507	fb->fb.fix.smem_start = dma;
	508	fb->fb.fix.smem_len = framesize;
	509
	510	return 0;
	511	}
	512
	513	static int cp_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	514	{
	515	return dma_mmap_writecombine(&fb->dev->dev, vma,
	516	fb->fb.screen_base,
	517	fb->fb.fix.smem_start,
	518	fb->fb.fix.smem_len);
	519	}
	520
	521	static void cp_clcd_remove(struct clcd_fb *fb)
	522	{
	523	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	524	fb->fb.screen_base, fb->fb.fix.smem_start);
	525	}
	526
	527	static struct clcd_board clcd_data = {
	528	.name = "Integrator/CP",
	529	.check = clcdfb_check,
	530	.decode = clcdfb_decode,
	531	.enable = cp_clcd_enable,
	532	.setup = cp_clcd_setup,
	533	.mmap = cp_clcd_mmap,
	534	.remove = cp_clcd_remove,
	535	};
	536
	537	static struct amba_device clcd_device = {
	538	.dev = {
1d559e29	539	.init_name = "mb:c0",
1da177e4 LT	540	.coherent_dma_mask = ~0,
	541	.platform_data = &clcd_data,
	542	},
	543	.res = {
	544	.start = INTCP_PA_CLCD_BASE,
	545	.end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
	546	.flags = IORESOURCE_MEM,
	547	},
	548	.dma_mask = ~0,
	549	.irq = { IRQ_CP_CLCDCINT, NO_IRQ },
	550	.periphid = 0,
	551	};
	552
	553	static struct amba_device *amba_devs[] __initdata = {
	554	&mmc_device,
	555	&aaci_device,
	556	&clcd_device,
	557	};
	558
	559	static void __init intcp_init(void)
	560	{
	561	int i;
	562
0a0300dc	563	clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
1da177e4 LT	564	platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
	565
	566	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
	567	struct amba_device *d = amba_devs[i];
	568	amba_device_register(d, &iomem_resource);
	569	}
	570	}
	571
	572	#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
	573
	574	static void __init intcp_timer_init(void)
	575	{
861248d1	576	integrator_time_init(1000, TIMER_CTRL_IE);
1da177e4 LT	577	}
	578
	579	static struct sys_timer cp_timer = {
	580	.init = intcp_timer_init,
1da177e4 LT	581	};
	582
	583	MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
e9dea0c6	584	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
e9dea0c6 RK	585	.phys_io = 0x16000000,
	586	.io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
	587	.boot_params = 0x00000100,
	588	.map_io = intcp_map_io,
	589	.init_irq = intcp_init_irq,
1da177e4	590	.timer = &cp_timer,
e9dea0c6	591	.init_machine = intcp_init,
1da177e4	592	MACHINE_END