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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mach-integrator/integrator_cp.c | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | */ | |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/list.h> | |
d052d1be | 14 | #include <linux/platform_device.h> |
1da177e4 LT |
15 | #include <linux/dma-mapping.h> |
16 | #include <linux/slab.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/sysdev.h> | |
a62c80e5 RK |
19 | #include <linux/amba/bus.h> |
20 | #include <linux/amba/kmi.h> | |
21 | #include <linux/amba/clcd.h> | |
6ef297f8 | 22 | #include <linux/amba/mmci.h> |
fced80c7 | 23 | #include <linux/io.h> |
1da177e4 | 24 | |
d72fbdf0 RK |
25 | #include <asm/clkdev.h> |
26 | #include <mach/clkdev.h> | |
a09e64fb | 27 | #include <mach/hardware.h> |
a285edcf | 28 | #include <mach/platform.h> |
1da177e4 LT |
29 | #include <asm/irq.h> |
30 | #include <asm/setup.h> | |
31 | #include <asm/mach-types.h> | |
1da177e4 LT |
32 | #include <asm/hardware/icst525.h> |
33 | ||
a09e64fb RK |
34 | #include <mach/cm.h> |
35 | #include <mach/lm.h> | |
1da177e4 LT |
36 | |
37 | #include <asm/mach/arch.h> | |
38 | #include <asm/mach/flash.h> | |
39 | #include <asm/mach/irq.h> | |
1da177e4 LT |
40 | #include <asm/mach/map.h> |
41 | #include <asm/mach/time.h> | |
42 | ||
43 | #include "common.h" | |
1da177e4 LT |
44 | |
45 | #define INTCP_PA_MMC_BASE 0x1c000000 | |
46 | #define INTCP_PA_AACI_BASE 0x1d000000 | |
47 | ||
48 | #define INTCP_PA_FLASH_BASE 0x24000000 | |
49 | #define INTCP_FLASH_SIZE SZ_32M | |
50 | ||
51 | #define INTCP_PA_CLCD_BASE 0xc0000000 | |
52 | ||
365f7a43 CM |
53 | #define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40 |
54 | #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE) | |
55 | #define INTCP_VA_SIC_BASE IO_ADDRESS(0xca000000) | |
1da177e4 LT |
56 | |
57 | #define INTCP_PA_ETH_BASE 0xc8000000 | |
58 | #define INTCP_ETH_SIZE 0x10 | |
59 | ||
365f7a43 | 60 | #define INTCP_VA_CTRL_BASE IO_ADDRESS(0xcb000000) |
1da177e4 LT |
61 | #define INTCP_FLASHPROG 0x04 |
62 | #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) | |
63 | #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) | |
64 | ||
65 | /* | |
66 | * Logical Physical | |
67 | * f1000000 10000000 Core module registers | |
68 | * f1100000 11000000 System controller registers | |
69 | * f1200000 12000000 EBI registers | |
70 | * f1300000 13000000 Counter/Timer | |
71 | * f1400000 14000000 Interrupt controller | |
72 | * f1600000 16000000 UART 0 | |
73 | * f1700000 17000000 UART 1 | |
74 | * f1a00000 1a000000 Debug LEDs | |
75 | * f1b00000 1b000000 GPIO | |
76 | */ | |
77 | ||
78 | static struct map_desc intcp_io_desc[] __initdata = { | |
c8d27298 DS |
79 | { |
80 | .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), | |
81 | .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), | |
82 | .length = SZ_4K, | |
83 | .type = MT_DEVICE | |
84 | }, { | |
85 | .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), | |
86 | .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), | |
87 | .length = SZ_4K, | |
88 | .type = MT_DEVICE | |
89 | }, { | |
90 | .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), | |
91 | .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), | |
92 | .length = SZ_4K, | |
93 | .type = MT_DEVICE | |
94 | }, { | |
95 | .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), | |
96 | .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), | |
97 | .length = SZ_4K, | |
98 | .type = MT_DEVICE | |
99 | }, { | |
100 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), | |
101 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), | |
102 | .length = SZ_4K, | |
103 | .type = MT_DEVICE | |
104 | }, { | |
105 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), | |
106 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), | |
107 | .length = SZ_4K, | |
108 | .type = MT_DEVICE | |
109 | }, { | |
110 | .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE), | |
111 | .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE), | |
112 | .length = SZ_4K, | |
113 | .type = MT_DEVICE | |
114 | }, { | |
115 | .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE), | |
116 | .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE), | |
117 | .length = SZ_4K, | |
118 | .type = MT_DEVICE | |
119 | }, { | |
120 | .virtual = IO_ADDRESS(INTEGRATOR_GPIO_BASE), | |
121 | .pfn = __phys_to_pfn(INTEGRATOR_GPIO_BASE), | |
122 | .length = SZ_4K, | |
123 | .type = MT_DEVICE | |
124 | }, { | |
365f7a43 | 125 | .virtual = IO_ADDRESS(0xca000000), |
c8d27298 DS |
126 | .pfn = __phys_to_pfn(0xca000000), |
127 | .length = SZ_4K, | |
128 | .type = MT_DEVICE | |
129 | }, { | |
365f7a43 | 130 | .virtual = IO_ADDRESS(0xcb000000), |
c8d27298 DS |
131 | .pfn = __phys_to_pfn(0xcb000000), |
132 | .length = SZ_4K, | |
133 | .type = MT_DEVICE | |
134 | } | |
1da177e4 LT |
135 | }; |
136 | ||
137 | static void __init intcp_map_io(void) | |
138 | { | |
139 | iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc)); | |
140 | } | |
141 | ||
142 | #define cic_writel __raw_writel | |
143 | #define cic_readl __raw_readl | |
144 | #define pic_writel __raw_writel | |
145 | #define pic_readl __raw_readl | |
146 | #define sic_writel __raw_writel | |
147 | #define sic_readl __raw_readl | |
148 | ||
149 | static void cic_mask_irq(unsigned int irq) | |
150 | { | |
151 | irq -= IRQ_CIC_START; | |
152 | cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | |
153 | } | |
154 | ||
155 | static void cic_unmask_irq(unsigned int irq) | |
156 | { | |
157 | irq -= IRQ_CIC_START; | |
158 | cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET); | |
159 | } | |
160 | ||
38c677cb DB |
161 | static struct irq_chip cic_chip = { |
162 | .name = "CIC", | |
1da177e4 LT |
163 | .ack = cic_mask_irq, |
164 | .mask = cic_mask_irq, | |
165 | .unmask = cic_unmask_irq, | |
166 | }; | |
167 | ||
168 | static void pic_mask_irq(unsigned int irq) | |
169 | { | |
170 | irq -= IRQ_PIC_START; | |
171 | pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | |
172 | } | |
173 | ||
174 | static void pic_unmask_irq(unsigned int irq) | |
175 | { | |
176 | irq -= IRQ_PIC_START; | |
177 | pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET); | |
178 | } | |
179 | ||
38c677cb DB |
180 | static struct irq_chip pic_chip = { |
181 | .name = "PIC", | |
1da177e4 LT |
182 | .ack = pic_mask_irq, |
183 | .mask = pic_mask_irq, | |
184 | .unmask = pic_unmask_irq, | |
185 | }; | |
186 | ||
187 | static void sic_mask_irq(unsigned int irq) | |
188 | { | |
189 | irq -= IRQ_SIC_START; | |
190 | sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | |
191 | } | |
192 | ||
193 | static void sic_unmask_irq(unsigned int irq) | |
194 | { | |
195 | irq -= IRQ_SIC_START; | |
196 | sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET); | |
197 | } | |
198 | ||
38c677cb DB |
199 | static struct irq_chip sic_chip = { |
200 | .name = "SIC", | |
1da177e4 LT |
201 | .ack = sic_mask_irq, |
202 | .mask = sic_mask_irq, | |
203 | .unmask = sic_unmask_irq, | |
204 | }; | |
205 | ||
206 | static void | |
10dd5ce2 | 207 | sic_handle_irq(unsigned int irq, struct irq_desc *desc) |
1da177e4 LT |
208 | { |
209 | unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS); | |
210 | ||
211 | if (status == 0) { | |
0cd61b68 | 212 | do_bad_IRQ(irq, desc); |
1da177e4 LT |
213 | return; |
214 | } | |
215 | ||
216 | do { | |
217 | irq = ffs(status) - 1; | |
218 | status &= ~(1 << irq); | |
219 | ||
220 | irq += IRQ_SIC_START; | |
221 | ||
d8aa0251 | 222 | generic_handle_irq(irq); |
1da177e4 LT |
223 | } while (status); |
224 | } | |
225 | ||
226 | static void __init intcp_init_irq(void) | |
227 | { | |
228 | unsigned int i; | |
229 | ||
230 | /* | |
231 | * Disable all interrupt sources | |
232 | */ | |
233 | pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | |
234 | pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); | |
235 | ||
236 | for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) { | |
237 | if (i == 11) | |
238 | i = 22; | |
1da177e4 LT |
239 | if (i == 29) |
240 | break; | |
241 | set_irq_chip(i, &pic_chip); | |
10dd5ce2 | 242 | set_irq_handler(i, handle_level_irq); |
1da177e4 LT |
243 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
244 | } | |
245 | ||
246 | cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | |
247 | cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); | |
248 | ||
249 | for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) { | |
250 | set_irq_chip(i, &cic_chip); | |
10dd5ce2 | 251 | set_irq_handler(i, handle_level_irq); |
1da177e4 LT |
252 | set_irq_flags(i, IRQF_VALID); |
253 | } | |
254 | ||
255 | sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | |
256 | sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); | |
257 | ||
258 | for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { | |
259 | set_irq_chip(i, &sic_chip); | |
10dd5ce2 | 260 | set_irq_handler(i, handle_level_irq); |
1da177e4 LT |
261 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
262 | } | |
263 | ||
56f1319e | 264 | set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq); |
1da177e4 LT |
265 | } |
266 | ||
267 | /* | |
268 | * Clock handling | |
269 | */ | |
270 | #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET) | |
271 | #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c) | |
272 | ||
273 | static const struct icst525_params cp_auxvco_params = { | |
274 | .ref = 24000, | |
275 | .vco_max = 320000, | |
276 | .vd_min = 8, | |
277 | .vd_max = 263, | |
278 | .rd_min = 3, | |
279 | .rd_max = 65, | |
280 | }; | |
281 | ||
282 | static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco) | |
283 | { | |
284 | u32 val; | |
285 | ||
286 | val = readl(CM_AUXOSC) & ~0x7ffff; | |
287 | val |= vco.v | (vco.r << 9) | (vco.s << 16); | |
288 | ||
289 | writel(0xa05f, CM_LOCK); | |
290 | writel(val, CM_AUXOSC); | |
291 | writel(0, CM_LOCK); | |
292 | } | |
293 | ||
d72fbdf0 | 294 | static struct clk cp_auxclk = { |
1da177e4 LT |
295 | .params = &cp_auxvco_params, |
296 | .setvco = cp_auxvco_set, | |
297 | }; | |
298 | ||
d72fbdf0 RK |
299 | static struct clk_lookup cp_lookups[] = { |
300 | { /* CLCD */ | |
301 | .dev_id = "mb:c0", | |
302 | .clk = &cp_auxclk, | |
303 | }, | |
1da177e4 LT |
304 | }; |
305 | ||
306 | /* | |
307 | * Flash handling. | |
308 | */ | |
309 | static int intcp_flash_init(void) | |
310 | { | |
311 | u32 val; | |
312 | ||
313 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
314 | val |= CINTEGRATOR_FLASHPROG_FLWREN; | |
315 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static void intcp_flash_exit(void) | |
321 | { | |
322 | u32 val; | |
323 | ||
324 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
325 | val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN); | |
326 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
327 | } | |
328 | ||
329 | static void intcp_flash_set_vpp(int on) | |
330 | { | |
331 | u32 val; | |
332 | ||
333 | val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
334 | if (on) | |
335 | val |= CINTEGRATOR_FLASHPROG_FLVPPEN; | |
336 | else | |
337 | val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN; | |
338 | writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); | |
339 | } | |
340 | ||
341 | static struct flash_platform_data intcp_flash_data = { | |
342 | .map_name = "cfi_probe", | |
343 | .width = 4, | |
344 | .init = intcp_flash_init, | |
345 | .exit = intcp_flash_exit, | |
346 | .set_vpp = intcp_flash_set_vpp, | |
347 | }; | |
348 | ||
349 | static struct resource intcp_flash_resource = { | |
350 | .start = INTCP_PA_FLASH_BASE, | |
351 | .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, | |
352 | .flags = IORESOURCE_MEM, | |
353 | }; | |
354 | ||
355 | static struct platform_device intcp_flash_device = { | |
356 | .name = "armflash", | |
357 | .id = 0, | |
358 | .dev = { | |
359 | .platform_data = &intcp_flash_data, | |
360 | }, | |
361 | .num_resources = 1, | |
362 | .resource = &intcp_flash_resource, | |
363 | }; | |
364 | ||
365 | static struct resource smc91x_resources[] = { | |
366 | [0] = { | |
367 | .start = INTCP_PA_ETH_BASE, | |
368 | .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1, | |
369 | .flags = IORESOURCE_MEM, | |
370 | }, | |
371 | [1] = { | |
372 | .start = IRQ_CP_ETHINT, | |
373 | .end = IRQ_CP_ETHINT, | |
374 | .flags = IORESOURCE_IRQ, | |
375 | }, | |
376 | }; | |
377 | ||
378 | static struct platform_device smc91x_device = { | |
379 | .name = "smc91x", | |
380 | .id = 0, | |
381 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
382 | .resource = smc91x_resources, | |
383 | }; | |
384 | ||
385 | static struct platform_device *intcp_devs[] __initdata = { | |
386 | &intcp_flash_device, | |
387 | &smc91x_device, | |
388 | }; | |
389 | ||
390 | /* | |
391 | * It seems that the card insertion interrupt remains active after | |
392 | * we've acknowledged it. We therefore ignore the interrupt, and | |
393 | * rely on reading it from the SIC. This also means that we must | |
394 | * clear the latched interrupt. | |
395 | */ | |
396 | static unsigned int mmc_status(struct device *dev) | |
397 | { | |
365f7a43 CM |
398 | unsigned int status = readl(IO_ADDRESS(0xca000000) + 4); |
399 | writel(8, IO_ADDRESS(0xcb000000) + 8); | |
1da177e4 LT |
400 | |
401 | return status & 8; | |
402 | } | |
403 | ||
6ef297f8 | 404 | static struct mmci_platform_data mmc_data = { |
1da177e4 LT |
405 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
406 | .status = mmc_status, | |
7fb2bbf4 RK |
407 | .gpio_wp = -1, |
408 | .gpio_cd = -1, | |
1da177e4 LT |
409 | }; |
410 | ||
411 | static struct amba_device mmc_device = { | |
412 | .dev = { | |
1d559e29 | 413 | .init_name = "mb:1c", |
1da177e4 LT |
414 | .platform_data = &mmc_data, |
415 | }, | |
416 | .res = { | |
417 | .start = INTCP_PA_MMC_BASE, | |
418 | .end = INTCP_PA_MMC_BASE + SZ_4K - 1, | |
419 | .flags = IORESOURCE_MEM, | |
420 | }, | |
421 | .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }, | |
422 | .periphid = 0, | |
423 | }; | |
424 | ||
425 | static struct amba_device aaci_device = { | |
426 | .dev = { | |
1d559e29 | 427 | .init_name = "mb:1d", |
1da177e4 LT |
428 | }, |
429 | .res = { | |
430 | .start = INTCP_PA_AACI_BASE, | |
431 | .end = INTCP_PA_AACI_BASE + SZ_4K - 1, | |
432 | .flags = IORESOURCE_MEM, | |
433 | }, | |
434 | .irq = { IRQ_CP_AACIINT, NO_IRQ }, | |
435 | .periphid = 0, | |
436 | }; | |
437 | ||
438 | ||
439 | /* | |
440 | * CLCD support | |
441 | */ | |
442 | static struct clcd_panel vga = { | |
443 | .mode = { | |
444 | .name = "VGA", | |
445 | .refresh = 60, | |
446 | .xres = 640, | |
447 | .yres = 480, | |
448 | .pixclock = 39721, | |
449 | .left_margin = 40, | |
450 | .right_margin = 24, | |
451 | .upper_margin = 32, | |
452 | .lower_margin = 11, | |
453 | .hsync_len = 96, | |
454 | .vsync_len = 2, | |
455 | .sync = 0, | |
456 | .vmode = FB_VMODE_NONINTERLACED, | |
457 | }, | |
458 | .width = -1, | |
459 | .height = -1, | |
460 | .tim2 = TIM2_BCD | TIM2_IPC, | |
461 | .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1), | |
462 | .bpp = 16, | |
463 | .grayscale = 0, | |
464 | }; | |
465 | ||
466 | /* | |
467 | * Ensure VGA is selected. | |
468 | */ | |
469 | static void cp_clcd_enable(struct clcd_fb *fb) | |
470 | { | |
4774e226 RK |
471 | u32 val; |
472 | ||
473 | if (fb->fb.var.bits_per_pixel <= 8) | |
474 | val = CM_CTRL_LCDMUXSEL_VGA_8421BPP; | |
475 | else if (fb->fb.var.bits_per_pixel <= 16) | |
14e54cc3 CM |
476 | val = CM_CTRL_LCDMUXSEL_VGA_16BPP |
477 | | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1 | |
478 | | CM_CTRL_STATIC1 | CM_CTRL_STATIC2; | |
4774e226 RK |
479 | else |
480 | val = 0; /* no idea for this, don't trust the docs */ | |
481 | ||
482 | cm_control(CM_CTRL_LCDMUXSEL_MASK| | |
483 | CM_CTRL_LCDEN0| | |
484 | CM_CTRL_LCDEN1| | |
485 | CM_CTRL_STATIC1| | |
486 | CM_CTRL_STATIC2| | |
487 | CM_CTRL_STATIC| | |
488 | CM_CTRL_n24BITEN, val); | |
1da177e4 LT |
489 | } |
490 | ||
491 | static unsigned long framesize = SZ_1M; | |
492 | ||
493 | static int cp_clcd_setup(struct clcd_fb *fb) | |
494 | { | |
495 | dma_addr_t dma; | |
496 | ||
497 | fb->panel = &vga; | |
498 | ||
499 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, | |
500 | &dma, GFP_KERNEL); | |
501 | if (!fb->fb.screen_base) { | |
502 | printk(KERN_ERR "CLCD: unable to map framebuffer\n"); | |
503 | return -ENOMEM; | |
504 | } | |
505 | ||
506 | fb->fb.fix.smem_start = dma; | |
507 | fb->fb.fix.smem_len = framesize; | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | |
513 | { | |
514 | return dma_mmap_writecombine(&fb->dev->dev, vma, | |
515 | fb->fb.screen_base, | |
516 | fb->fb.fix.smem_start, | |
517 | fb->fb.fix.smem_len); | |
518 | } | |
519 | ||
520 | static void cp_clcd_remove(struct clcd_fb *fb) | |
521 | { | |
522 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, | |
523 | fb->fb.screen_base, fb->fb.fix.smem_start); | |
524 | } | |
525 | ||
526 | static struct clcd_board clcd_data = { | |
527 | .name = "Integrator/CP", | |
528 | .check = clcdfb_check, | |
529 | .decode = clcdfb_decode, | |
530 | .enable = cp_clcd_enable, | |
531 | .setup = cp_clcd_setup, | |
532 | .mmap = cp_clcd_mmap, | |
533 | .remove = cp_clcd_remove, | |
534 | }; | |
535 | ||
536 | static struct amba_device clcd_device = { | |
537 | .dev = { | |
1d559e29 | 538 | .init_name = "mb:c0", |
1da177e4 LT |
539 | .coherent_dma_mask = ~0, |
540 | .platform_data = &clcd_data, | |
541 | }, | |
542 | .res = { | |
543 | .start = INTCP_PA_CLCD_BASE, | |
544 | .end = INTCP_PA_CLCD_BASE + SZ_4K - 1, | |
545 | .flags = IORESOURCE_MEM, | |
546 | }, | |
547 | .dma_mask = ~0, | |
548 | .irq = { IRQ_CP_CLCDCINT, NO_IRQ }, | |
549 | .periphid = 0, | |
550 | }; | |
551 | ||
552 | static struct amba_device *amba_devs[] __initdata = { | |
553 | &mmc_device, | |
554 | &aaci_device, | |
555 | &clcd_device, | |
556 | }; | |
557 | ||
558 | static void __init intcp_init(void) | |
559 | { | |
560 | int i; | |
561 | ||
0a0300dc | 562 | clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups)); |
1da177e4 LT |
563 | platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); |
564 | ||
565 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | |
566 | struct amba_device *d = amba_devs[i]; | |
567 | amba_device_register(d, &iomem_resource); | |
568 | } | |
569 | } | |
570 | ||
571 | #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */ | |
572 | ||
573 | static void __init intcp_timer_init(void) | |
574 | { | |
575 | integrator_time_init(1000000 / HZ, TIMER_CTRL_IE); | |
576 | } | |
577 | ||
578 | static struct sys_timer cp_timer = { | |
579 | .init = intcp_timer_init, | |
580 | .offset = integrator_gettimeoffset, | |
581 | }; | |
582 | ||
583 | MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") | |
e9dea0c6 | 584 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ |
e9dea0c6 RK |
585 | .phys_io = 0x16000000, |
586 | .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc, | |
587 | .boot_params = 0x00000100, | |
588 | .map_io = intcp_map_io, | |
589 | .init_irq = intcp_init_irq, | |
1da177e4 | 590 | .timer = &cp_timer, |
e9dea0c6 | 591 | .init_machine = intcp_init, |
1da177e4 | 592 | MACHINE_END |