[net-next-2.6.git] / arch / arm / mach-integrator / include / mach / platform.h

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
/* DO NOT EDIT!! - this file automatically generated
 *                 from .s file by awk -f s2h.awk
 */
/**************************************************************************
 * * Copyright © ARM Limited 1998.  All rights reserved.
 * ***********************************************************************/
/* ************************************************************************
 *
 *   Integrator address map
 *
 * 	NOTE: This is a multi-hosted header file for use with uHAL and
 * 	      supported debuggers.
 *
 * ***********************************************************************/

#ifndef __address_h
#define __address_h                     1

/* ========================================================================
 *  Integrator definitions
 * ========================================================================
 * ------------------------------------------------------------------------
 *  Memory definitions
 * ------------------------------------------------------------------------
 *  Integrator memory map
 *
 */
#define INTEGRATOR_BOOT_ROM_LO          0x00000000
#define INTEGRATOR_BOOT_ROM_HI          0x20000000
#define INTEGRATOR_BOOT_ROM_BASE        INTEGRATOR_BOOT_ROM_HI	 /*  Normal position */
#define INTEGRATOR_BOOT_ROM_SIZE        SZ_512K

/*
 *  New Core Modules have different amounts of SSRAM, the amount of SSRAM
 *  fitted can be found in HDR_STAT.
 *
 *  The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
 *  the minimum amount of SSRAM fitted on any core module.
 *
 *  New Core Modules also alias the SSRAM.
 *
 */
#define INTEGRATOR_SSRAM_BASE           0x00000000
#define INTEGRATOR_SSRAM_ALIAS_BASE     0x10800000
#define INTEGRATOR_SSRAM_SIZE           SZ_256K

#define INTEGRATOR_FLASH_BASE           0x24000000
#define INTEGRATOR_FLASH_SIZE           SZ_32M

#define INTEGRATOR_MBRD_SSRAM_BASE      0x28000000
#define INTEGRATOR_MBRD_SSRAM_SIZE      SZ_512K

/*
 *  SDRAM is a SIMM therefore the size is not known.
 *
 */
#define INTEGRATOR_SDRAM_BASE           0x00040000

#define INTEGRATOR_SDRAM_ALIAS_BASE     0x80000000
#define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
#define INTEGRATOR_HDR1_SDRAM_BASE      0x90000000
#define INTEGRATOR_HDR2_SDRAM_BASE      0xA0000000
#define INTEGRATOR_HDR3_SDRAM_BASE      0xB0000000

/*
 *  Logic expansion modules
 *
 */
#define INTEGRATOR_LOGIC_MODULES_BASE   0xC0000000
#define INTEGRATOR_LOGIC_MODULE0_BASE   0xC0000000
#define INTEGRATOR_LOGIC_MODULE1_BASE   0xD0000000
#define INTEGRATOR_LOGIC_MODULE2_BASE   0xE0000000
#define INTEGRATOR_LOGIC_MODULE3_BASE   0xF0000000

/* ------------------------------------------------------------------------
 *  Integrator header card registers
 * ------------------------------------------------------------------------
 *
 */
#define INTEGRATOR_HDR_ID_OFFSET        0x00
#define INTEGRATOR_HDR_PROC_OFFSET      0x04
#define INTEGRATOR_HDR_OSC_OFFSET       0x08
#define INTEGRATOR_HDR_CTRL_OFFSET      0x0C
#define INTEGRATOR_HDR_STAT_OFFSET      0x10
#define INTEGRATOR_HDR_LOCK_OFFSET      0x14
#define INTEGRATOR_HDR_SDRAM_OFFSET     0x20
#define INTEGRATOR_HDR_INIT_OFFSET      0x24	 /*  CM9x6 */
#define INTEGRATOR_HDR_IC_OFFSET        0x40
#define INTEGRATOR_HDR_SPDBASE_OFFSET   0x100
#define INTEGRATOR_HDR_SPDTOP_OFFSET    0x200

#define INTEGRATOR_HDR_BASE             0x10000000
#define INTEGRATOR_HDR_ID               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
#define INTEGRATOR_HDR_PROC             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
#define INTEGRATOR_HDR_OSC              (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
#define INTEGRATOR_HDR_CTRL             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
#define INTEGRATOR_HDR_STAT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
#define INTEGRATOR_HDR_LOCK             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
#define INTEGRATOR_HDR_SDRAM            (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
#define INTEGRATOR_HDR_INIT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
#define INTEGRATOR_HDR_IC               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
#define INTEGRATOR_HDR_SPDBASE          (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
#define INTEGRATOR_HDR_SPDTOP           (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)

#define INTEGRATOR_HDR_CTRL_LED         0x01
#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
#define INTEGRATOR_HDR_CTRL_REMAP       0x04
#define INTEGRATOR_HDR_CTRL_RESET       0x08
#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN  0x20
#define INTEGRATOR_HDR_CTRL_FASTBUS     0x40
#define INTEGRATOR_HDR_CTRL_SYNC        0x80

#define INTEGRATOR_HDR_OSC_CORE_10MHz   0x102
#define INTEGRATOR_HDR_OSC_CORE_15MHz   0x107
#define INTEGRATOR_HDR_OSC_CORE_20MHz   0x10C
#define INTEGRATOR_HDR_OSC_CORE_25MHz   0x111
#define INTEGRATOR_HDR_OSC_CORE_30MHz   0x116
#define INTEGRATOR_HDR_OSC_CORE_35MHz   0x11B
#define INTEGRATOR_HDR_OSC_CORE_40MHz   0x120
#define INTEGRATOR_HDR_OSC_CORE_45MHz   0x125
#define INTEGRATOR_HDR_OSC_CORE_50MHz   0x12A
#define INTEGRATOR_HDR_OSC_CORE_55MHz   0x12F
#define INTEGRATOR_HDR_OSC_CORE_60MHz   0x134
#define INTEGRATOR_HDR_OSC_CORE_65MHz   0x139
#define INTEGRATOR_HDR_OSC_CORE_70MHz   0x13E
#define INTEGRATOR_HDR_OSC_CORE_75MHz   0x143
#define INTEGRATOR_HDR_OSC_CORE_80MHz   0x148
#define INTEGRATOR_HDR_OSC_CORE_85MHz   0x14D
#define INTEGRATOR_HDR_OSC_CORE_90MHz   0x152
#define INTEGRATOR_HDR_OSC_CORE_95MHz   0x157
#define INTEGRATOR_HDR_OSC_CORE_100MHz  0x15C
#define INTEGRATOR_HDR_OSC_CORE_105MHz  0x161
#define INTEGRATOR_HDR_OSC_CORE_110MHz  0x166
#define INTEGRATOR_HDR_OSC_CORE_115MHz  0x16B
#define INTEGRATOR_HDR_OSC_CORE_120MHz  0x170
#define INTEGRATOR_HDR_OSC_CORE_125MHz  0x175
#define INTEGRATOR_HDR_OSC_CORE_130MHz  0x17A
#define INTEGRATOR_HDR_OSC_CORE_135MHz  0x17F
#define INTEGRATOR_HDR_OSC_CORE_140MHz  0x184
#define INTEGRATOR_HDR_OSC_CORE_145MHz  0x189
#define INTEGRATOR_HDR_OSC_CORE_150MHz  0x18E
#define INTEGRATOR_HDR_OSC_CORE_155MHz  0x193
#define INTEGRATOR_HDR_OSC_CORE_160MHz  0x198
#define INTEGRATOR_HDR_OSC_CORE_MASK    0x7FF

#define INTEGRATOR_HDR_OSC_MEM_10MHz    0x10C000
#define INTEGRATOR_HDR_OSC_MEM_15MHz    0x116000
#define INTEGRATOR_HDR_OSC_MEM_20MHz    0x120000
#define INTEGRATOR_HDR_OSC_MEM_25MHz    0x12A000
#define INTEGRATOR_HDR_OSC_MEM_30MHz    0x134000
#define INTEGRATOR_HDR_OSC_MEM_33MHz    0x13A000
#define INTEGRATOR_HDR_OSC_MEM_40MHz    0x148000
#define INTEGRATOR_HDR_OSC_MEM_50MHz    0x15C000
#define INTEGRATOR_HDR_OSC_MEM_60MHz    0x170000
#define INTEGRATOR_HDR_OSC_MEM_66MHz    0x17C000
#define INTEGRATOR_HDR_OSC_MEM_MASK     0x7FF000

#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0  0x0
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0  0x0800000
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6  0x1000000
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00  0x1800000
#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK  0x1800000

#define INTEGRATOR_HDR_SDRAM_SPD_OK     (1 << 5)


/* ------------------------------------------------------------------------
 *  Integrator system registers
 * ------------------------------------------------------------------------
 *
 */

/*
 *  System Controller
 *
 */
#define INTEGRATOR_SC_ID_OFFSET         0x00
#define INTEGRATOR_SC_OSC_OFFSET        0x04
#define INTEGRATOR_SC_CTRLS_OFFSET      0x08
#define INTEGRATOR_SC_CTRLC_OFFSET      0x0C
#define INTEGRATOR_SC_DEC_OFFSET        0x10
#define INTEGRATOR_SC_ARB_OFFSET        0x14
#define INTEGRATOR_SC_PCIENABLE_OFFSET  0x18
#define INTEGRATOR_SC_LOCK_OFFSET       0x1C

#define INTEGRATOR_SC_BASE              0x11000000
#define INTEGRATOR_SC_ID                (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
#define INTEGRATOR_SC_OSC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
#define INTEGRATOR_SC_CTRLS             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
#define INTEGRATOR_SC_CTRLC             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
#define INTEGRATOR_SC_DEC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
#define INTEGRATOR_SC_ARB               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
#define INTEGRATOR_SC_PCIENABLE         (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
#define INTEGRATOR_SC_LOCK              (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)

#define INTEGRATOR_SC_OSC_SYS_10MHz     0x20
#define INTEGRATOR_SC_OSC_SYS_15MHz     0x34
#define INTEGRATOR_SC_OSC_SYS_20MHz     0x48
#define INTEGRATOR_SC_OSC_SYS_25MHz     0x5C
#define INTEGRATOR_SC_OSC_SYS_33MHz     0x7C
#define INTEGRATOR_SC_OSC_SYS_MASK      0xFF

#define INTEGRATOR_SC_OSC_PCI_25MHz     0x100
#define INTEGRATOR_SC_OSC_PCI_33MHz     0x0
#define INTEGRATOR_SC_OSC_PCI_MASK      0x100

#define INTEGRATOR_SC_CTRL_SOFTRST      (1 << 0)
#define INTEGRATOR_SC_CTRL_nFLVPPEN     (1 << 1)
#define INTEGRATOR_SC_CTRL_nFLWP        (1 << 2)
#define INTEGRATOR_SC_CTRL_URTS0        (1 << 4)
#define INTEGRATOR_SC_CTRL_UDTR0        (1 << 5)
#define INTEGRATOR_SC_CTRL_URTS1        (1 << 6)
#define INTEGRATOR_SC_CTRL_UDTR1        (1 << 7)

/*
 *  External Bus Interface
 *
 */
#define INTEGRATOR_EBI_BASE             0x12000000

#define INTEGRATOR_EBI_CSR0_OFFSET      0x00
#define INTEGRATOR_EBI_CSR1_OFFSET      0x04
#define INTEGRATOR_EBI_CSR2_OFFSET      0x08
#define INTEGRATOR_EBI_CSR3_OFFSET      0x0C
#define INTEGRATOR_EBI_LOCK_OFFSET      0x20

#define INTEGRATOR_EBI_CSR0             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
#define INTEGRATOR_EBI_CSR1             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define INTEGRATOR_EBI_CSR2             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
#define INTEGRATOR_EBI_CSR3             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
#define INTEGRATOR_EBI_LOCK             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)

#define INTEGRATOR_EBI_8_BIT            0x00
#define INTEGRATOR_EBI_16_BIT           0x01
#define INTEGRATOR_EBI_32_BIT           0x02
#define INTEGRATOR_EBI_WRITE_ENABLE     0x04
#define INTEGRATOR_EBI_SYNC             0x08
#define INTEGRATOR_EBI_WS_2             0x00
#define INTEGRATOR_EBI_WS_3             0x10
#define INTEGRATOR_EBI_WS_4             0x20
#define INTEGRATOR_EBI_WS_5             0x30
#define INTEGRATOR_EBI_WS_6             0x40
#define INTEGRATOR_EBI_WS_7             0x50
#define INTEGRATOR_EBI_WS_8             0x60
#define INTEGRATOR_EBI_WS_9             0x70
#define INTEGRATOR_EBI_WS_10            0x80
#define INTEGRATOR_EBI_WS_11            0x90
#define INTEGRATOR_EBI_WS_12            0xA0
#define INTEGRATOR_EBI_WS_13            0xB0
#define INTEGRATOR_EBI_WS_14            0xC0
#define INTEGRATOR_EBI_WS_15            0xD0
#define INTEGRATOR_EBI_WS_16            0xE0
#define INTEGRATOR_EBI_WS_17            0xF0


#define INTEGRATOR_CT_BASE              0x13000000	 /*  Counter/Timers */
#define INTEGRATOR_IC_BASE              0x14000000	 /*  Interrupt Controller */
#define INTEGRATOR_RTC_BASE             0x15000000	 /*  Real Time Clock */
#define INTEGRATOR_UART0_BASE           0x16000000	 /*  UART 0 */
#define INTEGRATOR_UART1_BASE           0x17000000	 /*  UART 1 */
#define INTEGRATOR_KBD_BASE             0x18000000	 /*  Keyboard */
#define INTEGRATOR_MOUSE_BASE           0x19000000	 /*  Mouse */

/*
 *  LED's & Switches
 *
 */
#define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
#define INTEGRATOR_DBG_LEDS_OFFSET      0x04
#define INTEGRATOR_DBG_SWITCH_OFFSET    0x08

#define INTEGRATOR_DBG_BASE             0x1A000000
#define INTEGRATOR_DBG_ALPHA            (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
#define INTEGRATOR_DBG_LEDS             (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
#define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)

#define INTEGRATOR_AP_GPIO_BASE		0x1B000000	/* GPIO */

#define INTEGRATOR_CP_MMC_BASE		0x1C000000	/* MMC */
#define INTEGRATOR_CP_AACI_BASE		0x1D000000	/* AACI */
#define INTEGRATOR_CP_ETH_BASE		0xC8000000	/* Ethernet */
#define INTEGRATOR_CP_GPIO_BASE		0xC9000000	/* GPIO */
#define INTEGRATOR_CP_SIC_BASE		0xCA000000	/* SIC */
#define INTEGRATOR_CP_CTL_BASE		0xCB000000	/* CP system control */

/* ------------------------------------------------------------------------
 *  KMI keyboard/mouse definitions
 * ------------------------------------------------------------------------
 */
/* PS2 Keyboard interface */
#define KMI0_BASE                       INTEGRATOR_KBD_BASE

/* PS2 Mouse interface */
#define KMI1_BASE                       INTEGRATOR_MOUSE_BASE

/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */

/* ------------------------------------------------------------------------
 *  Where in the memory map does PCI live?
 * ------------------------------------------------------------------------
 *  This represents a fairly liberal usage of address space.  Even though
 *  the V3 only has two windows (therefore we need to map stuff on the fly),
 *  we maintain the same addresses, even if they're not mapped.
 *
 */
#define PHYS_PCI_MEM_BASE               0x40000000   /* 512M to xxx */
/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
 */
#define PHYS_PCI_IO_BASE                0x60000000   /* 16M to xxx */
/*  unused (128-16)M from B1000000-B7FFFFFF
 */
#define PHYS_PCI_CONFIG_BASE            0x61000000   /* 16M to xxx */
/*  unused ((128-16)M - 64K) from XXX
 */
#define PHYS_PCI_V3_BASE                0x62000000

#define PCI_DRAMSIZE                    INTEGRATOR_SSRAM_SIZE

/* 'export' these to UHAL */
#define UHAL_PCI_IO                     PCI_IO_BASE
#define UHAL_PCI_MEM                    PCI_MEM_BASE
#define UHAL_PCI_ALLOC_IO_BASE          0x00004000
#define UHAL_PCI_ALLOC_MEM_BASE         PCI_MEM_BASE
#define UHAL_PCI_MAX_SLOT               20

/* ========================================================================
 *  Start of uHAL definitions
 * ========================================================================
 */

/* ------------------------------------------------------------------------
 *  Integrator Interrupt Controllers
 * ------------------------------------------------------------------------
 *
 *  Offsets from interrupt controller base
 *
 *  System Controller interrupt controller base is
 *
 * 	INTEGRATOR_IC_BASE + (header_number << 6)
 *
 *  Core Module interrupt controller base is
 *
 * 	INTEGRATOR_HDR_IC
 *
 */
#define IRQ_STATUS                      0
#define IRQ_RAW_STATUS                  0x04
#define IRQ_ENABLE                      0x08
#define IRQ_ENABLE_SET                  0x08
#define IRQ_ENABLE_CLEAR                0x0C

#define INT_SOFT_SET                    0x10
#define INT_SOFT_CLEAR                  0x14

#define FIQ_STATUS                      0x20
#define FIQ_RAW_STATUS                  0x24
#define FIQ_ENABLE                      0x28
#define FIQ_ENABLE_SET                  0x28
#define FIQ_ENABLE_CLEAR                0x2C


/* ------------------------------------------------------------------------
 *  Interrupts
 * ------------------------------------------------------------------------
 *
 *
 *  Each Core Module has two interrupts controllers, one on the core module
 *  itself and one in the system controller on the motherboard.  The
 *  READ_INT macro in target.s reads both interrupt controllers and returns
 *  a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
 *  and bits 24 to 31 are from the core module.
 *
 *  The following definitions relate to the bitmask returned by READ_INT.
 *
 */

/* ------------------------------------------------------------------------
 *  LED's - The header LED is not accessible via the uHAL API
 * ------------------------------------------------------------------------
 *
 */
#define GREEN_LED                       0x01
#define YELLOW_LED                      0x02
#define RED_LED                         0x04
#define GREEN_LED_2                     0x08
#define ALL_LEDS                        0x0F

#define LED_BANK                        INTEGRATOR_DBG_LEDS

/*
 *  Memory definitions - run uHAL out of SSRAM.
 *
 */
#define uHAL_MEMORY_SIZE                INTEGRATOR_SSRAM_SIZE

/*
 *  Clean base - dummy
 *
 */
#define CLEAN_BASE                      INTEGRATOR_BOOT_ROM_HI

/*
 *  Timer definitions
 *
 *  Only use timer 1 & 2
 *  (both run at 24MHz and will need the clock divider set to 16).
 *
 *  Timer 0 runs at bus frequency and therefore could vary and currently
 *  uHAL can't handle that.
 *
 */

#define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
#define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
#define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)

#define MAX_TIMER                       2
#define MAX_PERIOD                      699050
#define TICKS_PER_uSEC                  24

/*
 *  These are useconds NOT ticks.
 *
 */
#define mSEC_1                          1000
#define mSEC_5                          (mSEC_1 * 5)
#define mSEC_10                         (mSEC_1 * 10)
#define mSEC_25                         (mSEC_1 * 25)
#define SEC_1                           (mSEC_1 * 1000)

#define INTEGRATOR_CSR_BASE             0x10000000
#define INTEGRATOR_CSR_SIZE             0x10000000

#endif

/* 	END */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License as published by
	4	* the Free Software Foundation; either version 2 of the License, or
	5	* (at your option) any later version.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	15	*/
	16	/* DO NOT EDIT!! - this file automatically generated
	17	* from .s file by awk -f s2h.awk
	18	*/
	19	/**************************************************************************
121e70b6	20	* * Copyright © ARM Limited 1998. All rights reserved.
1da177e4 LT	21	* ***********************************************************************/
1da177e4 LT	22	/* ************************************************************************
1f9c381f	23	*
1da177e4	24	* Integrator address map
1f9c381f	25	*
1da177e4 LT	26	* NOTE: This is a multi-hosted header file for use with uHAL and
1da177e4 LT	27	* supported debuggers.
1f9c381f	28	*
1da177e4 LT	29	* ***********************************************************************/
	30
	31	#ifndef __address_h
	32	#define __address_h 1
	33
	34	/* ========================================================================
	35	* Integrator definitions
	36	* ========================================================================
	37	* ------------------------------------------------------------------------
	38	* Memory definitions
	39	* ------------------------------------------------------------------------
	40	* Integrator memory map
1f9c381f	41	*
1da177e4 LT	42	*/
	43	#define INTEGRATOR_BOOT_ROM_LO 0x00000000
	44	#define INTEGRATOR_BOOT_ROM_HI 0x20000000
	45	#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
	46	#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
	47
1f9c381f	48	/*
1da177e4 LT	49	* New Core Modules have different amounts of SSRAM, the amount of SSRAM
1da177e4 LT	50	* fitted can be found in HDR_STAT.
1f9c381f	51	*
1da177e4 LT	52	* The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
1da177e4 LT	53	* the minimum amount of SSRAM fitted on any core module.
1f9c381f	54	*
1da177e4	55	* New Core Modules also alias the SSRAM.
1f9c381f	56	*
1da177e4 LT	57	*/
	58	#define INTEGRATOR_SSRAM_BASE 0x00000000
	59	#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
	60	#define INTEGRATOR_SSRAM_SIZE SZ_256K
	61
	62	#define INTEGRATOR_FLASH_BASE 0x24000000
	63	#define INTEGRATOR_FLASH_SIZE SZ_32M
	64
	65	#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
	66	#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
	67
1f9c381f	68	/*
1da177e4	69	* SDRAM is a SIMM therefore the size is not known.
1f9c381f	70	*
1da177e4 LT	71	*/
	72	#define INTEGRATOR_SDRAM_BASE 0x00040000
	73
	74	#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
	75	#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
	76	#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
	77	#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
	78	#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
	79
1f9c381f	80	/*
1da177e4	81	* Logic expansion modules
1f9c381f	82	*
1da177e4 LT	83	*/
	84	#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
	85	#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
	86	#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
	87	#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
	88	#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
	89
	90	/* ------------------------------------------------------------------------
	91	* Integrator header card registers
	92	* ------------------------------------------------------------------------
1f9c381f	93	*
1da177e4 LT	94	*/
	95	#define INTEGRATOR_HDR_ID_OFFSET 0x00
	96	#define INTEGRATOR_HDR_PROC_OFFSET 0x04
	97	#define INTEGRATOR_HDR_OSC_OFFSET 0x08
	98	#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
	99	#define INTEGRATOR_HDR_STAT_OFFSET 0x10
	100	#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
	101	#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
	102	#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
	103	#define INTEGRATOR_HDR_IC_OFFSET 0x40
	104	#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
	105	#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
	106
	107	#define INTEGRATOR_HDR_BASE 0x10000000
	108	#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
	109	#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
	110	#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
	111	#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
	112	#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
	113	#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
	114	#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
	115	#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
	116	#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
	117	#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
	118	#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
	119
	120	#define INTEGRATOR_HDR_CTRL_LED 0x01
	121	#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
	122	#define INTEGRATOR_HDR_CTRL_REMAP 0x04
	123	#define INTEGRATOR_HDR_CTRL_RESET 0x08
	124	#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
	125	#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
	126	#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
	127	#define INTEGRATOR_HDR_CTRL_SYNC 0x80
	128
	129	#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
	130	#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
	131	#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
	132	#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
	133	#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
	134	#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
	135	#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
	136	#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
	137	#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
	138	#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
	139	#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
	140	#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
	141	#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
	142	#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
	143	#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
	144	#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
	145	#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
	146	#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
	147	#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
	148	#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
	149	#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
	150	#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
	151	#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
	152	#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
	153	#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
	154	#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
	155	#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
	156	#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
	157	#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
158	#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
159	#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
160	#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
161
162	#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
163	#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
164	#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
165	#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
166	#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
167	#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
168	#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
169	#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
170	#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
171	#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
172	#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
173
174	#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
175	#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
176	#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
177	#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
178	#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
179
180	#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
181
182
183	/* ------------------------------------------------------------------------
184	* Integrator system registers
185	* ------------------------------------------------------------------------
1f9c381f	186	*
1da177e4 LT	187	*/
1da177e4 LT	188
1f9c381f	189	/*
1da177e4	190	* System Controller
1f9c381f	191	*
1da177e4 LT	192	*/
	193	#define INTEGRATOR_SC_ID_OFFSET 0x00
	194	#define INTEGRATOR_SC_OSC_OFFSET 0x04
	195	#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
	196	#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
	197	#define INTEGRATOR_SC_DEC_OFFSET 0x10
	198	#define INTEGRATOR_SC_ARB_OFFSET 0x14
	199	#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
	200	#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
	201
	202	#define INTEGRATOR_SC_BASE 0x11000000
	203	#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
	204	#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
	205	#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
	206	#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
	207	#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
	208	#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
	209	#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
	210	#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
	211
	212	#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
	213	#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
	214	#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
	215	#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
	216	#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
	217	#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
	218
	219	#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
	220	#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
	221	#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
	222
	223	#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
	224	#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
	225	#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
	226	#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
	227	#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
	228	#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
	229	#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
	230
1f9c381f	231	/*
1da177e4	232	* External Bus Interface
1f9c381f	233	*
1da177e4	234	*/
1f9c381f	235	#define INTEGRATOR_EBI_BASE 0x12000000
1da177e4 LT	236
	237	#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
	238	#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
	239	#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
	240	#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
	241	#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
	242
	243	#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
	244	#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
	245	#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
	246	#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
	247	#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
	248
	249	#define INTEGRATOR_EBI_8_BIT 0x00
	250	#define INTEGRATOR_EBI_16_BIT 0x01
	251	#define INTEGRATOR_EBI_32_BIT 0x02
	252	#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
	253	#define INTEGRATOR_EBI_SYNC 0x08
	254	#define INTEGRATOR_EBI_WS_2 0x00
	255	#define INTEGRATOR_EBI_WS_3 0x10
	256	#define INTEGRATOR_EBI_WS_4 0x20
	257	#define INTEGRATOR_EBI_WS_5 0x30
	258	#define INTEGRATOR_EBI_WS_6 0x40
	259	#define INTEGRATOR_EBI_WS_7 0x50
	260	#define INTEGRATOR_EBI_WS_8 0x60
	261	#define INTEGRATOR_EBI_WS_9 0x70
	262	#define INTEGRATOR_EBI_WS_10 0x80
	263	#define INTEGRATOR_EBI_WS_11 0x90
	264	#define INTEGRATOR_EBI_WS_12 0xA0
	265	#define INTEGRATOR_EBI_WS_13 0xB0
	266	#define INTEGRATOR_EBI_WS_14 0xC0
	267	#define INTEGRATOR_EBI_WS_15 0xD0
	268	#define INTEGRATOR_EBI_WS_16 0xE0
	269	#define INTEGRATOR_EBI_WS_17 0xF0
	270
	271
	272	#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
	273	#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
	274	#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
	275	#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
	276	#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
	277	#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
	278	#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
	279
1f9c381f	280	/*
1da177e4	281	* LED's & Switches
1f9c381f	282	*
1da177e4 LT	283	*/
	284	#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
	285	#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
	286	#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
	287
	288	#define INTEGRATOR_DBG_BASE 0x1A000000
	289	#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
	290	#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
	291	#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
	292
da7ba956 RK	293	#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
	294
	295	#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
	296	#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
	297	#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
	298	#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
	299	#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
	300	#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
1da177e4 LT	301
	302	/* ------------------------------------------------------------------------
	303	* KMI keyboard/mouse definitions
	304	* ------------------------------------------------------------------------
	305	*/
	306	/* PS2 Keyboard interface */
1f9c381f	307	#define KMI0_BASE INTEGRATOR_KBD_BASE
1da177e4 LT	308
	309	/* PS2 Mouse interface */
	310	#define KMI1_BASE INTEGRATOR_MOUSE_BASE
	311
	312	/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
	313
	314	/* ------------------------------------------------------------------------
	315	* Where in the memory map does PCI live?
	316	* ------------------------------------------------------------------------
	317	* This represents a fairly liberal usage of address space. Even though
	318	* the V3 only has two windows (therefore we need to map stuff on the fly),
	319	* we maintain the same addresses, even if they're not mapped.
1f9c381f	320	*
1da177e4 LT	321	*/
	322	#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */
	323	/* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
	324	*/
	325	#define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */
	326	/* unused (128-16)M from B1000000-B7FFFFFF
	327	*/
	328	#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
	329	/* unused ((128-16)M - 64K) from XXX
	330	*/
	331	#define PHYS_PCI_V3_BASE 0x62000000
	332
1f9c381f	333	#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
1da177e4 LT	334
	335	/* 'export' these to UHAL */
	336	#define UHAL_PCI_IO PCI_IO_BASE
	337	#define UHAL_PCI_MEM PCI_MEM_BASE
	338	#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
	339	#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
	340	#define UHAL_PCI_MAX_SLOT 20
1f9c381f	341
1da177e4 LT	342	/* ========================================================================
	343	* Start of uHAL definitions
	344	* ========================================================================
	345	*/
	346
	347	/* ------------------------------------------------------------------------
	348	* Integrator Interrupt Controllers
	349	* ------------------------------------------------------------------------
1f9c381f RK	350	*
	351	* Offsets from interrupt controller base
	352	*
1da177e4	353	* System Controller interrupt controller base is
1f9c381f	354	*
1da177e4	355	* INTEGRATOR_IC_BASE + (header_number << 6)
1f9c381f	356	*
1da177e4	357	* Core Module interrupt controller base is
1f9c381f RK	358	*
	359	* INTEGRATOR_HDR_IC
	360	*
1da177e4 LT	361	*/
	362	#define IRQ_STATUS 0
	363	#define IRQ_RAW_STATUS 0x04
	364	#define IRQ_ENABLE 0x08
	365	#define IRQ_ENABLE_SET 0x08
	366	#define IRQ_ENABLE_CLEAR 0x0C
	367
	368	#define INT_SOFT_SET 0x10
	369	#define INT_SOFT_CLEAR 0x14
	370
	371	#define FIQ_STATUS 0x20
	372	#define FIQ_RAW_STATUS 0x24
	373	#define FIQ_ENABLE 0x28
	374	#define FIQ_ENABLE_SET 0x28
	375	#define FIQ_ENABLE_CLEAR 0x2C
	376
	377
	378	/* ------------------------------------------------------------------------
	379	* Interrupts
	380	* ------------------------------------------------------------------------
1f9c381f RK	381	*
1f9c381f RK	382	*
1da177e4 LT	383	* Each Core Module has two interrupts controllers, one on the core module
	384	* itself and one in the system controller on the motherboard. The
	385	* READ_INT macro in target.s reads both interrupt controllers and returns
	386	* a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
	387	* and bits 24 to 31 are from the core module.
1f9c381f	388	*
1da177e4	389	* The following definitions relate to the bitmask returned by READ_INT.
1f9c381f	390	*
1da177e4 LT	391	*/
	392
	393	/* ------------------------------------------------------------------------
	394	* LED's - The header LED is not accessible via the uHAL API
	395	* ------------------------------------------------------------------------
1f9c381f	396	*
1da177e4 LT	397	*/
	398	#define GREEN_LED 0x01
	399	#define YELLOW_LED 0x02
	400	#define RED_LED 0x04
	401	#define GREEN_LED_2 0x08
	402	#define ALL_LEDS 0x0F
	403
	404	#define LED_BANK INTEGRATOR_DBG_LEDS
	405
1f9c381f	406	/*
1da177e4	407	* Memory definitions - run uHAL out of SSRAM.
1f9c381f	408	*
1da177e4 LT	409	*/
	410	#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
	411
1f9c381f	412	/*
1da177e4	413	* Clean base - dummy
1f9c381f	414	*
1da177e4	415	*/
1e8b0416	416	#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI
1da177e4	417
1f9c381f	418	/*
1da177e4	419	* Timer definitions
1f9c381f	420	*
1da177e4 LT	421	* Only use timer 1 & 2
1da177e4 LT	422	* (both run at 24MHz and will need the clock divider set to 16).
1f9c381f	423	*
1da177e4 LT	424	* Timer 0 runs at bus frequency and therefore could vary and currently
1da177e4 LT	425	* uHAL can't handle that.
1f9c381f	426	*
1da177e4 LT	427	*/
	428
	429	#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
	430	#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
	431	#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
	432
	433	#define MAX_TIMER 2
	434	#define MAX_PERIOD 699050
	435	#define TICKS_PER_uSEC 24
	436
1f9c381f RK	437	/*
	438	* These are useconds NOT ticks.
	439	*
1da177e4 LT	440	*/
	441	#define mSEC_1 1000
	442	#define mSEC_5 (mSEC_1 * 5)
	443	#define mSEC_10 (mSEC_1 * 10)
	444	#define mSEC_25 (mSEC_1 * 25)
	445	#define SEC_1 (mSEC_1 * 1000)
	446
	447	#define INTEGRATOR_CSR_BASE 0x10000000
	448	#define INTEGRATOR_CSR_SIZE 0x10000000
	449
	450	#endif
	451
	452	/* END */