git://bbs.cooldavid.org / net-next-2.6.git / blame
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| ff4569c7 DB |
1 | /* |
| 2 | * mach-davinci/nand.h | |
| 3 | * | |
| 4 | * Copyright © 2006 Texas Instruments. | |
| 5 | * | |
| 6 | * Ported to 2.6.23 Copyright © 2008 by | |
| 7 | * Sander Huijsen <Shuijsen@optelecom-nkf.com> | |
| 8 | * Troy Kisky <troy.kisky@boundarydevices.com> | |
| 9 | * Dirk Behme <Dirk.Behme@gmail.com> | |
| 10 | * | |
| 11 | * -------------------------------------------------------------------------- | |
| 12 | * | |
| 13 | * This program is free software; you can redistribute it and/or modify | |
| 14 | * it under the terms of the GNU General Public License as published by | |
| 15 | * the Free Software Foundation; either version 2 of the License, or | |
| 16 | * (at your option) any later version. | |
| 17 | * | |
| 18 | * This program is distributed in the hope that it will be useful, | |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 21 | * GNU General Public License for more details. | |
| 22 | * | |
| 23 | * You should have received a copy of the GNU General Public License | |
| 24 | * along with this program; if not, write to the Free Software | |
| 25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __ARCH_ARM_DAVINCI_NAND_H | |
| 29 | #define __ARCH_ARM_DAVINCI_NAND_H | |
| 30 | ||
| 31 | #include <linux/mtd/nand.h> | |
| 32 | ||
| 33 | #define NRCSR_OFFSET 0x00 | |
| 34 | #define AWCCR_OFFSET 0x04 | |
| 35 | #define A1CR_OFFSET 0x10 | |
| 36 | #define NANDFCR_OFFSET 0x60 | |
| 37 | #define NANDFSR_OFFSET 0x64 | |
| 38 | #define NANDF1ECC_OFFSET 0x70 | |
| 39 | ||
| 40 | /* 4-bit ECC syndrome registers */ | |
| 41 | #define NAND_4BIT_ECC_LOAD_OFFSET 0xbc | |
| 42 | #define NAND_4BIT_ECC1_OFFSET 0xc0 | |
| 43 | #define NAND_4BIT_ECC2_OFFSET 0xc4 | |
| 44 | #define NAND_4BIT_ECC3_OFFSET 0xc8 | |
| 45 | #define NAND_4BIT_ECC4_OFFSET 0xcc | |
| 46 | #define NAND_ERR_ADD1_OFFSET 0xd0 | |
| 47 | #define NAND_ERR_ADD2_OFFSET 0xd4 | |
| 48 | #define NAND_ERR_ERRVAL1_OFFSET 0xd8 | |
| 49 | #define NAND_ERR_ERRVAL2_OFFSET 0xdc | |
| 50 | ||
| 51 | /* NOTE: boards don't need to use these address bits | |
| 52 | * for ALE/CLE unless they support booting from NAND. | |
| 53 | * They're used unless platform data overrides them. | |
| 54 | */ | |
| 55 | #define MASK_ALE 0x08 | |
| 56 | #define MASK_CLE 0x10 | |
| 57 | ||
| 58 | struct davinci_nand_pdata { /* platform_data */ | |
| 59 | uint32_t mask_ale; | |
| 60 | uint32_t mask_cle; | |
| 61 | ||
| 62 | /* for packages using two chipselects */ | |
| 63 | uint32_t mask_chipsel; | |
| 64 | ||
| 65 | /* board's default static partition info */ | |
| 66 | struct mtd_partition *parts; | |
| 67 | unsigned nr_parts; | |
| 68 | ||
| 69 | /* none == NAND_ECC_NONE (strongly *not* advised!!) | |
| 70 | * soft == NAND_ECC_SOFT | |
| 6a4123e5 DB |
71 | * else == NAND_ECC_HW, according to ecc_bits |
| 72 | * | |
| 73 | * All DaVinci-family chips support 1-bit hardware ECC. | |
| 74 | * Newer ones also support 4-bit ECC, but are awkward | |
| 75 | * using it with large page chips. | |
| ff4569c7 DB |
76 | */ |
| 77 | nand_ecc_modes_t ecc_mode; | |
| 6a4123e5 | 78 | u8 ecc_bits; |
| ff4569c7 DB |
79 | |
| 80 | /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ | |
| 81 | unsigned options; | |
| 82 | }; | |
| 83 | ||
| 84 | #endif /* __ARCH_ARM_DAVINCI_NAND_H */ |