[net-next-2.6.git] / arch / arm / mach-davinci / include / mach / gpio.h

/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef	__DAVINCI_GPIO_H
#define	__DAVINCI_GPIO_H

#include <linux/io.h>
#include <asm-generic/gpio.h>

#include <mach/irqs.h>
#include <mach/common.h>

#define DAVINCI_GPIO_BASE 0x01C67000

/*
 * basic gpio routines
 *
 * board-specific init should be done by arch/.../.../board-XXX.c (maybe
 * initializing banks together) rather than boot loaders; kexec() won't
 * go through boot loaders.
 *
 * the gpio clock will be turned on when gpios are used, and you may also
 * need to pay attention to PINMUX registers to be sure those pins are
 * used as gpios, not with other peripherals.
 *
 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation,
 * and maybe for later updates, code may write GPIO(N).  These may be
 * all 1.8V signals, all 3.3V ones, or a mix of the two.  A given chip
 * may not support all the GPIOs in that range.
 *
 * GPIOs can also be on external chips, numbered after the ones built-in
 * to the DaVinci chip.  For now, they won't be usable as IRQ sources.
 */
#define	GPIO(X)		(X)		/* 0 <= X <= (DAVINCI_N_GPIO - 1) */

struct gpio_controller {
	u32	dir;
	u32	out_data;
	u32	set_data;
	u32	clr_data;
	u32	in_data;
	u32	set_rising;
	u32	clr_rising;
	u32	set_falling;
	u32	clr_falling;
	u32	intstat;
};

/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
 * with constant parameters; or in outlined code they execute at runtime.
 *
 * You'd access the controller directly when reading or writing more than
 * one gpio value at a time, and to support wired logic where the value
 * being driven by the cpu need not match the value read back.
 *
 * These are NOT part of the cross-platform GPIO interface
 */
static inline struct gpio_controller *__iomem
__gpio_to_controller(unsigned gpio)
{
	void *__iomem ptr;
	void __iomem *base = davinci_soc_info.gpio_base;

	if (gpio < 32 * 1)
		ptr = base + 0x10;
	else if (gpio < 32 * 2)
		ptr = base + 0x38;
	else if (gpio < 32 * 3)
		ptr = base + 0x60;
	else if (gpio < 32 * 4)
		ptr = base + 0x88;
	else
		ptr = NULL;
	return ptr;
}

static inline u32 __gpio_mask(unsigned gpio)
{
	return 1 << (gpio % 32);
}

/* The get/set/clear functions will inline when called with constant
 * parameters referencing built-in GPIOs, for low-overhead bitbanging.
 *
 * Otherwise, calls with variable parameters or referencing external
 * GPIOs (e.g. on GPIO expander chips) use outlined functions.
 */
static inline void gpio_set_value(unsigned gpio, int value)
{
	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
		struct gpio_controller	*__iomem g;
		u32			mask;

		g = __gpio_to_controller(gpio);
		mask = __gpio_mask(gpio);
		if (value)
			__raw_writel(mask, &g->set_data);
		else
			__raw_writel(mask, &g->clr_data);
		return;
	}

	__gpio_set_value(gpio, value);
}

/* Returns zero or nonzero; works for gpios configured as inputs OR
 * as outputs, at least for built-in GPIOs.
 *
 * NOTE: for built-in GPIOs, changes in reported values are synchronized
 * to the GPIO clock.  This is easily seen after calling gpio_set_value()
 * and then immediately gpio_get_value(), where the gpio_get_value() will
 * return the old value until the GPIO clock ticks and the new value gets
 * latched.
 */
static inline int gpio_get_value(unsigned gpio)
{
	struct gpio_controller	*__iomem g;

	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
		return __gpio_get_value(gpio);

	g = __gpio_to_controller(gpio);
	return __gpio_mask(gpio) & __raw_readl(&g->in_data);
}

static inline int gpio_cansleep(unsigned gpio)
{
	if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
		return 0;
	else
		return __gpio_cansleep(gpio);
}

static inline int gpio_to_irq(unsigned gpio)
{
	return __gpio_to_irq(gpio);
}

static inline int irq_to_gpio(unsigned irq)
{
	/* don't support the reverse mapping */
	return -ENOSYS;
}

#endif				/* __DAVINCI_GPIO_H */
Commit	Line	Data
3d9edf09 VB	1	/*
	2	* TI DaVinci GPIO Support
	3	*
	4	* Copyright (c) 2006 David Brownell
	5	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#ifndef __DAVINCI_GPIO_H
	14	#define __DAVINCI_GPIO_H
	15
558de8a7	16	#include <linux/io.h>
dce1115b	17	#include <asm-generic/gpio.h>
f5c122da	18
80b02c17	19	#include <mach/irqs.h>
a994955c	20	#include <mach/common.h>
558de8a7	21
f5c122da KH	22	#define DAVINCI_GPIO_BASE 0x01C67000
f5c122da KH	23
3d9edf09 VB	24	/*
	25	* basic gpio routines
	26	*
	27	* board-specific init should be done by arch/.../.../board-XXX.c (maybe
	28	* initializing banks together) rather than boot loaders; kexec() won't
	29	* go through boot loaders.
	30	*
	31	* the gpio clock will be turned on when gpios are used, and you may also
474dad54	32	* need to pay attention to PINMUX registers to be sure those pins are
3d9edf09 VB	33	* used as gpios, not with other peripherals.
3d9edf09 VB	34	*
dce1115b	35	* On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation,
474dad54 DB	36	* and maybe for later updates, code may write GPIO(N). These may be
	37	* all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip
	38	* may not support all the GPIOs in that range.
dce1115b DB	39	*
	40	* GPIOs can also be on external chips, numbered after the ones built-in
	41	* to the DaVinci chip. For now, they won't be usable as IRQ sources.
3d9edf09	42	*/
474dad54	43	#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
3d9edf09 VB	44
	45	struct gpio_controller {
	46	u32 dir;
	47	u32 out_data;
	48	u32 set_data;
	49	u32 clr_data;
	50	u32 in_data;
	51	u32 set_rising;
	52	u32 clr_rising;
	53	u32 set_falling;
	54	u32 clr_falling;
	55	u32 intstat;
	56	};
	57
	58	/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
	59	* with constant parameters; or in outlined code they execute at runtime.
	60	*
	61	* You'd access the controller directly when reading or writing more than
	62	* one gpio value at a time, and to support wired logic where the value
	63	* being driven by the cpu need not match the value read back.
	64	*
	65	* These are NOT part of the cross-platform GPIO interface
	66	*/
	67	static inline struct gpio_controller *__iomem
	68	__gpio_to_controller(unsigned gpio)
	69	{
	70	void *__iomem ptr;
a994955c	71	void __iomem *base = davinci_soc_info.gpio_base;
3d9edf09	72
474dad54	73	if (gpio < 32 * 1)
a994955c	74	ptr = base + 0x10;
474dad54	75	else if (gpio < 32 * 2)
a994955c	76	ptr = base + 0x38;
474dad54	77	else if (gpio < 32 * 3)
a994955c	78	ptr = base + 0x60;
474dad54	79	else if (gpio < 32 * 4)
a994955c	80	ptr = base + 0x88;
3d9edf09 VB	81	else
	82	ptr = NULL;
	83	return ptr;
	84	}
	85
	86	static inline u32 __gpio_mask(unsigned gpio)
	87	{
	88	return 1 << (gpio % 32);
	89	}
	90
	91	/* The get/set/clear functions will inline when called with constant
dce1115b	92	* parameters referencing built-in GPIOs, for low-overhead bitbanging.
3d9edf09	93	*
dce1115b DB	94	* Otherwise, calls with variable parameters or referencing external
dce1115b DB	95	* GPIOs (e.g. on GPIO expander chips) use outlined functions.
3d9edf09	96	*/
3d9edf09 VB	97	static inline void gpio_set_value(unsigned gpio, int value)
3d9edf09 VB	98	{
dce1115b	99	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
3d9edf09 VB	100	struct gpio_controller *__iomem g;
	101	u32 mask;
	102
3d9edf09 VB	103	g = __gpio_to_controller(gpio);
	104	mask = __gpio_mask(gpio);
	105	if (value)
	106	__raw_writel(mask, &g->set_data);
	107	else
	108	__raw_writel(mask, &g->clr_data);
	109	return;
	110	}
	111
dce1115b	112	__gpio_set_value(gpio, value);
3d9edf09 VB	113	}
	114
	115	/* Returns zero or nonzero; works for gpios configured as inputs OR
dce1115b	116	* as outputs, at least for built-in GPIOs.
3d9edf09	117	*
dce1115b DB	118	* NOTE: for built-in GPIOs, changes in reported values are synchronized
	119	* to the GPIO clock. This is easily seen after calling gpio_set_value()
	120	* and then immediately gpio_get_value(), where the gpio_get_value() will
	121	* return the old value until the GPIO clock ticks and the new value gets
	122	* latched.
3d9edf09	123	*/
3d9edf09 VB	124	static inline int gpio_get_value(unsigned gpio)
3d9edf09 VB	125	{
dce1115b	126	struct gpio_controller *__iomem g;
3d9edf09	127
dce1115b DB	128	if (!__builtin_constant_p(gpio) \|\| gpio >= DAVINCI_N_GPIO)
dce1115b DB	129	return __gpio_get_value(gpio);
3d9edf09 VB	130
3d9edf09 VB	131	g = __gpio_to_controller(gpio);
dce1115b	132	return __gpio_mask(gpio) & __raw_readl(&g->in_data);
3d9edf09 VB	133	}
3d9edf09 VB	134
dce1115b DB	135	static inline int gpio_cansleep(unsigned gpio)
	136	{
	137	if (__builtin_constant_p(gpio) && gpio < DAVINCI_N_GPIO)
	138	return 0;
	139	else
	140	return __gpio_cansleep(gpio);
	141	}
3d9edf09 VB	142
	143	static inline int gpio_to_irq(unsigned gpio)
	144	{
7a36071e	145	return __gpio_to_irq(gpio);
3d9edf09 VB	146	}
	147
	148	static inline int irq_to_gpio(unsigned irq)
	149	{
7a36071e DB	150	/* don't support the reverse mapping */
7a36071e DB	151	return -ENOSYS;
3d9edf09 VB	152	}
	153
	154	#endif /* __DAVINCI_GPIO_H */