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1da177e4 | 1 | /* |
4baa9922 | 2 | * arch/arm/include/asm/ptrace.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996-2003 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #ifndef __ASM_ARM_PTRACE_H | |
11 | #define __ASM_ARM_PTRACE_H | |
12 | ||
d1cbbd6b CM |
13 | #include <asm/hwcap.h> |
14 | ||
1da177e4 LT |
15 | #define PTRACE_GETREGS 12 |
16 | #define PTRACE_SETREGS 13 | |
17 | #define PTRACE_GETFPREGS 14 | |
18 | #define PTRACE_SETFPREGS 15 | |
1b116522 RK |
19 | /* PTRACE_ATTACH is 16 */ |
20 | /* PTRACE_DETACH is 17 */ | |
1da177e4 LT |
21 | #define PTRACE_GETWMMXREGS 18 |
22 | #define PTRACE_SETWMMXREGS 19 | |
1b116522 | 23 | /* 20 is unused */ |
1da177e4 | 24 | #define PTRACE_OLDSETOPTIONS 21 |
1da177e4 | 25 | #define PTRACE_GET_THREAD_AREA 22 |
3f471126 | 26 | #define PTRACE_SET_SYSCALL 23 |
5429b060 | 27 | /* PTRACE_SYSCALL is 24 */ |
5429b060 LB |
28 | #define PTRACE_GETCRUNCHREGS 25 |
29 | #define PTRACE_SETCRUNCHREGS 26 | |
3d1228ea CM |
30 | #define PTRACE_GETVFPREGS 27 |
31 | #define PTRACE_SETVFPREGS 28 | |
5429b060 | 32 | |
1da177e4 LT |
33 | /* |
34 | * PSR bits | |
35 | */ | |
36 | #define USR26_MODE 0x00000000 | |
37 | #define FIQ26_MODE 0x00000001 | |
38 | #define IRQ26_MODE 0x00000002 | |
39 | #define SVC26_MODE 0x00000003 | |
40 | #define USR_MODE 0x00000010 | |
41 | #define FIQ_MODE 0x00000011 | |
42 | #define IRQ_MODE 0x00000012 | |
43 | #define SVC_MODE 0x00000013 | |
44 | #define ABT_MODE 0x00000017 | |
45 | #define UND_MODE 0x0000001b | |
46 | #define SYSTEM_MODE 0x0000001f | |
47 | #define MODE32_BIT 0x00000010 | |
48 | #define MODE_MASK 0x0000001f | |
49 | #define PSR_T_BIT 0x00000020 | |
50 | #define PSR_F_BIT 0x00000040 | |
51 | #define PSR_I_BIT 0x00000080 | |
d1cbbd6b | 52 | #define PSR_A_BIT 0x00000100 |
26584853 | 53 | #define PSR_E_BIT 0x00000200 |
1da177e4 LT |
54 | #define PSR_J_BIT 0x01000000 |
55 | #define PSR_Q_BIT 0x08000000 | |
56 | #define PSR_V_BIT 0x10000000 | |
57 | #define PSR_C_BIT 0x20000000 | |
58 | #define PSR_Z_BIT 0x40000000 | |
59 | #define PSR_N_BIT 0x80000000 | |
1da177e4 LT |
60 | |
61 | /* | |
62 | * Groups of PSR bits | |
63 | */ | |
64 | #define PSR_f 0xff000000 /* Flags */ | |
65 | #define PSR_s 0x00ff0000 /* Status */ | |
66 | #define PSR_x 0x0000ff00 /* Extension */ | |
67 | #define PSR_c 0x000000ff /* Control */ | |
68 | ||
d71e1352 CM |
69 | /* |
70 | * ARMv7 groups of APSR bits | |
71 | */ | |
72 | #define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */ | |
73 | #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ | |
74 | #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */ | |
75 | ||
26584853 CM |
76 | /* |
77 | * Default endianness state | |
78 | */ | |
79 | #ifdef CONFIG_CPU_ENDIAN_BE8 | |
80 | #define PSR_ENDSTATE PSR_E_BIT | |
81 | #else | |
82 | #define PSR_ENDSTATE 0 | |
83 | #endif | |
84 | ||
68b7f715 PB |
85 | /* |
86 | * These are 'magic' values for PTRACE_PEEKUSR that return info about where a | |
87 | * process is located in memory. | |
88 | */ | |
89 | #define PT_TEXT_ADDR 0x10000 | |
90 | #define PT_DATA_ADDR 0x10004 | |
91 | #define PT_TEXT_END_ADDR 0x10008 | |
92 | ||
1da177e4 LT |
93 | #ifndef __ASSEMBLY__ |
94 | ||
2dede2d8 NP |
95 | /* |
96 | * This struct defines the way the registers are stored on the | |
97 | * stack during a system call. Note that sizeof(struct pt_regs) | |
98 | * has to be a multiple of 8. | |
99 | */ | |
092a4e95 | 100 | #ifndef __KERNEL__ |
1da177e4 LT |
101 | struct pt_regs { |
102 | long uregs[18]; | |
103 | }; | |
092a4e95 JI |
104 | #else /* __KERNEL__ */ |
105 | struct pt_regs { | |
106 | unsigned long uregs[18]; | |
107 | }; | |
108 | #endif /* __KERNEL__ */ | |
1da177e4 LT |
109 | |
110 | #define ARM_cpsr uregs[16] | |
111 | #define ARM_pc uregs[15] | |
112 | #define ARM_lr uregs[14] | |
113 | #define ARM_sp uregs[13] | |
114 | #define ARM_ip uregs[12] | |
115 | #define ARM_fp uregs[11] | |
116 | #define ARM_r10 uregs[10] | |
117 | #define ARM_r9 uregs[9] | |
118 | #define ARM_r8 uregs[8] | |
119 | #define ARM_r7 uregs[7] | |
120 | #define ARM_r6 uregs[6] | |
121 | #define ARM_r5 uregs[5] | |
122 | #define ARM_r4 uregs[4] | |
123 | #define ARM_r3 uregs[3] | |
124 | #define ARM_r2 uregs[2] | |
125 | #define ARM_r1 uregs[1] | |
126 | #define ARM_r0 uregs[0] | |
127 | #define ARM_ORIG_r0 uregs[17] | |
128 | ||
129 | #ifdef __KERNEL__ | |
130 | ||
440e6ca7 CH |
131 | #define arch_has_single_step() (1) |
132 | ||
1da177e4 LT |
133 | #define user_mode(regs) \ |
134 | (((regs)->ARM_cpsr & 0xf) == 0) | |
135 | ||
136 | #ifdef CONFIG_ARM_THUMB | |
137 | #define thumb_mode(regs) \ | |
138 | (((regs)->ARM_cpsr & PSR_T_BIT)) | |
139 | #else | |
140 | #define thumb_mode(regs) (0) | |
141 | #endif | |
142 | ||
909d6c6c GD |
143 | #define isa_mode(regs) \ |
144 | ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ | |
145 | (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) | |
146 | ||
1da177e4 LT |
147 | #define processor_mode(regs) \ |
148 | ((regs)->ARM_cpsr & MODE_MASK) | |
149 | ||
150 | #define interrupts_enabled(regs) \ | |
151 | (!((regs)->ARM_cpsr & PSR_I_BIT)) | |
152 | ||
153 | #define fast_interrupts_enabled(regs) \ | |
154 | (!((regs)->ARM_cpsr & PSR_F_BIT)) | |
155 | ||
1da177e4 LT |
156 | /* Are the current registers suitable for user mode? |
157 | * (used to maintain security in signal handlers) | |
158 | */ | |
159 | static inline int valid_user_regs(struct pt_regs *regs) | |
160 | { | |
41e2e8fd RK |
161 | unsigned long mode = regs->ARM_cpsr & MODE_MASK; |
162 | ||
163 | /* | |
164 | * Always clear the F (FIQ) and A (delayed abort) bits | |
165 | */ | |
166 | regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); | |
167 | ||
168 | if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { | |
169 | if (mode == USR_MODE) | |
170 | return 1; | |
171 | if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE) | |
172 | return 1; | |
d1cbbd6b | 173 | } |
1da177e4 LT |
174 | |
175 | /* | |
176 | * Force CPSR to something logical... | |
177 | */ | |
41e2e8fd | 178 | regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; |
d1cbbd6b CM |
179 | if (!(elf_hwcap & HWCAP_26BIT)) |
180 | regs->ARM_cpsr |= USR_MODE; | |
1da177e4 LT |
181 | |
182 | return 0; | |
183 | } | |
184 | ||
1de765c1 | 185 | #define instruction_pointer(regs) (regs)->ARM_pc |
1da177e4 LT |
186 | |
187 | #ifdef CONFIG_SMP | |
188 | extern unsigned long profile_pc(struct pt_regs *regs); | |
189 | #else | |
190 | #define profile_pc(regs) instruction_pointer(regs) | |
191 | #endif | |
192 | ||
652a12ef | 193 | #define predicate(x) ((x) & 0xf0000000) |
1da177e4 | 194 | #define PREDICATE_ALWAYS 0xe0000000 |
f22ab814 | 195 | |
e513f8bf WD |
196 | /* |
197 | * kprobe-based event tracer support | |
198 | */ | |
199 | #include <linux/stddef.h> | |
200 | #include <linux/types.h> | |
201 | #define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0)) | |
202 | ||
203 | extern int regs_query_register_offset(const char *name); | |
204 | extern const char *regs_query_register_name(unsigned int offset); | |
205 | extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr); | |
206 | extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, | |
207 | unsigned int n); | |
208 | ||
209 | /** | |
210 | * regs_get_register() - get register value from its offset | |
211 | * @regs: pt_regs from which register value is gotten | |
212 | * @offset: offset number of the register. | |
213 | * | |
214 | * regs_get_register returns the value of a register whose offset from @regs. | |
215 | * The @offset is the offset of the register in struct pt_regs. | |
216 | * If @offset is bigger than MAX_REG_OFFSET, this returns 0. | |
217 | */ | |
218 | static inline unsigned long regs_get_register(struct pt_regs *regs, | |
219 | unsigned int offset) | |
220 | { | |
221 | if (unlikely(offset > MAX_REG_OFFSET)) | |
222 | return 0; | |
223 | return *(unsigned long *)((unsigned long)regs + offset); | |
224 | } | |
225 | ||
226 | /* Valid only for Kernel mode traps. */ | |
227 | static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) | |
228 | { | |
229 | return regs->ARM_sp; | |
230 | } | |
231 | ||
f22ab814 | 232 | #endif /* __KERNEL__ */ |
1da177e4 LT |
233 | |
234 | #endif /* __ASSEMBLY__ */ | |
235 | ||
236 | #endif | |
237 |