[net-next-2.6.git] / arch / arm / common / it8152.c

/*
 * linux/arch/arm/common/it8152.c
 *
 * Copyright Compulab Ltd, 2002-2007
 * Mike Rapoport <mike@compulab.co.il>
 *
 * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
 * (see this file for respective copyrights)
 *
 * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
 * and demux code.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ptrace.h>
#include <linux/interrupt.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <asm/mach/pci.h>
#include <asm/hardware/it8152.h>

#define MAX_SLOTS		21

static void it8152_mask_irq(unsigned int irq)
{
       if (irq >= IT8152_LD_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
			    (1 << (irq - IT8152_LD_IRQ(0)))),
			    IT8152_INTC_LDCNIMR);
       } else if (irq >= IT8152_LP_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
			    (1 << (irq - IT8152_LP_IRQ(0)))),
			    IT8152_INTC_LPCNIMR);
       } else if (irq >= IT8152_PD_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
			    (1 << (irq - IT8152_PD_IRQ(0)))),
			    IT8152_INTC_PDCNIMR);
       }
}

static void it8152_unmask_irq(unsigned int irq)
{
       if (irq >= IT8152_LD_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
			     ~(1 << (irq - IT8152_LD_IRQ(0)))),
			    IT8152_INTC_LDCNIMR);
       } else if (irq >= IT8152_LP_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
			     ~(1 << (irq - IT8152_LP_IRQ(0)))),
			    IT8152_INTC_LPCNIMR);
       } else if (irq >= IT8152_PD_IRQ(0)) {
	       __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
			     ~(1 << (irq - IT8152_PD_IRQ(0)))),
			    IT8152_INTC_PDCNIMR);
       }
}

static struct irq_chip it8152_irq_chip = {
	.name		= "it8152",
	.ack		= it8152_mask_irq,
	.mask		= it8152_mask_irq,
	.unmask		= it8152_unmask_irq,
};

void it8152_init_irq(void)
{
	int irq;

	__raw_writel((0xffff), IT8152_INTC_PDCNIMR);
	__raw_writel((0), IT8152_INTC_PDCNIRR);
	__raw_writel((0xffff), IT8152_INTC_LPCNIMR);
	__raw_writel((0), IT8152_INTC_LPCNIRR);
	__raw_writel((0xffff), IT8152_INTC_LDCNIMR);
	__raw_writel((0), IT8152_INTC_LDCNIRR);

	for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
		set_irq_chip(irq, &it8152_irq_chip);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}
}

void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
{
       int bits_pd, bits_lp, bits_ld;
       int i;

       while (1) {
	       /* Read all */
	       bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
	       bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
	       bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);

	       /* Ack */
	       __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
	       __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
	       __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);

	       if (!(bits_ld | bits_lp | bits_pd)) {
		       /* Re-read to guarantee, that there was a moment of
			  time, when they all three were 0. */
		       bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
		       bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
		       bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
		       if (!(bits_ld | bits_lp | bits_pd))
			       return;
	       }

	       bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
	       while (bits_pd) {
		       i = __ffs(bits_pd);
		       generic_handle_irq(IT8152_PD_IRQ(i));
		       bits_pd &= ~(1 << i);
	       }

	       bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
	       while (bits_lp) {
		       i = __ffs(bits_lp);
		       generic_handle_irq(IT8152_LP_IRQ(i));
		       bits_lp &= ~(1 << i);
	       }

	       bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
	       while (bits_ld) {
		       i = __ffs(bits_ld);
		       generic_handle_irq(IT8152_LD_IRQ(i));
		       bits_ld &= ~(1 << i);
	       }
       }
}

/* mapping for on-chip devices */
int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
	    (dev->device == PCI_DEVICE_ID_ITE_8152)) {
		if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
			return IT8152_AUDIO_INT;
		if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
			return IT8152_USB_INT;
		if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
			return IT8152_CDMA_INT;
	}

	return 0;
}

static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
						 unsigned int devfn)
{
	unsigned long addr = 0;

	if (bus->number == 0) {
			if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
				addr = (devfn << 8);
	} else
		addr = (bus->number << 16) | (devfn << 8);

	return addr;
}

static int it8152_pci_read_config(struct pci_bus *bus,
				  unsigned int devfn, int where,
				  int size, u32 *value)
{
	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
	u32 v;
	int shift;

	shift = (where & 3);

	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
	v = (__raw_readl(IT8152_PCI_CFG_DATA)  >> (8 * (shift)));

	*value = v;

	return PCIBIOS_SUCCESSFUL;
}

static int it8152_pci_write_config(struct pci_bus *bus,
				   unsigned int devfn, int where,
				   int size, u32 value)
{
	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
	u32 v, vtemp, mask = 0;
	int shift;

	if (size == 1)
		mask = 0xff;
	if (size == 2)
		mask = 0xffff;

	shift = (where & 3);

	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
	vtemp = __raw_readl(IT8152_PCI_CFG_DATA);

	if (mask)
		vtemp &= ~(mask << (8 * shift));
	else
		vtemp = 0;

	v = (value << (8 * shift));
	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
	__raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops it8152_ops = {
	.read = it8152_pci_read_config,
	.write = it8152_pci_write_config,
};

static struct resource it8152_io = {
	.name	= "IT8152 PCI I/O region",
	.flags	= IORESOURCE_IO,
};

static struct resource it8152_mem = {
	.name	= "IT8152 PCI memory region",
	.start	= 0x10000000,
	.end	= 0x13e00000,
	.flags	= IORESOURCE_MEM,
};

/*
 * The following functions are needed for DMA bouncing.
 * ITE8152 chip can addrees up to 64MByte, so all the devices
 * connected to ITE8152 (PCI and USB) should have limited DMA window
 */

/*
 * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
 * other devices.
 */
static int it8152_pci_platform_notify(struct device *dev)
{
	if (dev->bus == &pci_bus_type) {
		if (dev->dma_mask)
			*dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
		dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
		dmabounce_register_dev(dev, 2048, 4096);
	}
	return 0;
}

static int it8152_pci_platform_notify_remove(struct device *dev)
{
	if (dev->bus == &pci_bus_type)
		dmabounce_unregister_dev(dev);

	return 0;
}

int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
{
	dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
		__func__, dma_addr, size);
	return (dev->bus == &pci_bus_type) &&
		((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
}

int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
{
	it8152_io.start = IT8152_IO_BASE + 0x12000;
	it8152_io.end	= IT8152_IO_BASE + 0x12000 + 0x100000;

	sys->mem_offset = 0x10000000;
	sys->io_offset  = IT8152_IO_BASE;

	if (request_resource(&ioport_resource, &it8152_io)) {
		printk(KERN_ERR "PCI: unable to allocate IO region\n");
		goto err0;
	}
	if (request_resource(&iomem_resource, &it8152_mem)) {
		printk(KERN_ERR "PCI: unable to allocate memory region\n");
		goto err1;
	}

	sys->resource[0] = &it8152_io;
	sys->resource[1] = &it8152_mem;

	if (platform_notify || platform_notify_remove) {
		printk(KERN_ERR "PCI: Can't use platform_notify\n");
		goto err2;
	}

	platform_notify = it8152_pci_platform_notify;
	platform_notify_remove = it8152_pci_platform_notify_remove;

	return 1;

err2:
	release_resource(&it8152_io);
err1:
	release_resource(&it8152_mem);
err0:
	return -EBUSY;
}

/*
 * If we set up a device for bus mastering, we need to check the latency
 * timer as we don't have even crappy BIOSes to set it properly.
 * The implementation is from arch/i386/pci/i386.c
 */
unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;

	/* no need to update on-chip OHCI controller */
	if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
	    (dev->device == PCI_DEVICE_ID_ITE_8152) &&
	    ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
		return;

	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	       pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}


struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
	return pci_scan_bus(nr, &it8152_ops, sys);
}
Commit	Line	Data
a8fc0789 MR	1	/*
	2	* linux/arch/arm/common/it8152.c
	3	*
	4	* Copyright Compulab Ltd, 2002-2007
	5	* Mike Rapoport <mike@compulab.co.il>
	6	*
	7	* The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
	8	* (see this file for respective copyrights)
	9	*
	10	* Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
	11	* and demux code.
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*/
	17
	18	#include <linux/sched.h>
	19	#include <linux/kernel.h>
	20	#include <linux/pci.h>
	21	#include <linux/ptrace.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/mm.h>
	24	#include <linux/slab.h>
	25	#include <linux/init.h>
	26	#include <linux/ioport.h>
	27	#include <linux/irq.h>
	28	#include <linux/io.h>
	29
	30	#include <asm/mach/pci.h>
	31	#include <asm/hardware/it8152.h>
	32
	33	#define MAX_SLOTS 21
	34
	35	static void it8152_mask_irq(unsigned int irq)
	36	{
	37	if (irq >= IT8152_LD_IRQ(0)) {
	38	__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) \|
	39	(1 << (irq - IT8152_LD_IRQ(0)))),
	40	IT8152_INTC_LDCNIMR);
	41	} else if (irq >= IT8152_LP_IRQ(0)) {
	42	__raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) \|
	43	(1 << (irq - IT8152_LP_IRQ(0)))),
	44	IT8152_INTC_LPCNIMR);
	45	} else if (irq >= IT8152_PD_IRQ(0)) {
	46	__raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) \|
	47	(1 << (irq - IT8152_PD_IRQ(0)))),
	48	IT8152_INTC_PDCNIMR);
	49	}
	50	}
	51
	52	static void it8152_unmask_irq(unsigned int irq)
	53	{
	54	if (irq >= IT8152_LD_IRQ(0)) {
	55	__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
	56	~(1 << (irq - IT8152_LD_IRQ(0)))),
	57	IT8152_INTC_LDCNIMR);
	58	} else if (irq >= IT8152_LP_IRQ(0)) {
	59	__raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
	60	~(1 << (irq - IT8152_LP_IRQ(0)))),
	61	IT8152_INTC_LPCNIMR);
	62	} else if (irq >= IT8152_PD_IRQ(0)) {
	63	__raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
	64	~(1 << (irq - IT8152_PD_IRQ(0)))),
65	IT8152_INTC_PDCNIMR);
66	}
67	}
68
a8fc0789 MR	69	static struct irq_chip it8152_irq_chip = {
	70	.name = "it8152",
	71	.ack = it8152_mask_irq,
	72	.mask = it8152_mask_irq,
	73	.unmask = it8152_unmask_irq,
	74	};
	75
	76	void it8152_init_irq(void)
	77	{
	78	int irq;
	79
	80	__raw_writel((0xffff), IT8152_INTC_PDCNIMR);
	81	__raw_writel((0), IT8152_INTC_PDCNIRR);
	82	__raw_writel((0xffff), IT8152_INTC_LPCNIMR);
	83	__raw_writel((0), IT8152_INTC_LPCNIRR);
	84	__raw_writel((0xffff), IT8152_INTC_LDCNIMR);
	85	__raw_writel((0), IT8152_INTC_LDCNIRR);
	86
	87	for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
	88	set_irq_chip(irq, &it8152_irq_chip);
	89	set_irq_handler(irq, handle_level_irq);
	90	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	91	}
	92	}
	93
	94	void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
	95	{
	96	int bits_pd, bits_lp, bits_ld;
	97	int i;
	98
a8fc0789 MR	99	while (1) {
	100	/* Read all */
	101	bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
	102	bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
	103	bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
	104
	105	/* Ack */
	106	__raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
	107	__raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
	108	__raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
	109
	110	if (!(bits_ld \| bits_lp \| bits_pd)) {
	111	/* Re-read to guarantee, that there was a moment of
	112	time, when they all three were 0. */
	113	bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
	114	bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
b6265177	115	bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
a8fc0789 MR	116	if (!(bits_ld \| bits_lp \| bits_pd))
	117	return;
	118	}
	119
	120	bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
	121	while (bits_pd) {
	122	i = __ffs(bits_pd);
d8aa0251	123	generic_handle_irq(IT8152_PD_IRQ(i));
a8fc0789 MR	124	bits_pd &= ~(1 << i);
	125	}
	126
	127	bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
	128	while (bits_lp) {
b6265177	129	i = __ffs(bits_lp);
d8aa0251	130	generic_handle_irq(IT8152_LP_IRQ(i));
a8fc0789 MR	131	bits_lp &= ~(1 << i);
	132	}
	133
	134	bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
	135	while (bits_ld) {
b6265177	136	i = __ffs(bits_ld);
d8aa0251	137	generic_handle_irq(IT8152_LD_IRQ(i));
a8fc0789 MR	138	bits_ld &= ~(1 << i);
	139	}
	140	}
	141	}
	142
	143	/* mapping for on-chip devices */
	144	int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
	145	{
	146	if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
	147	(dev->device == PCI_DEVICE_ID_ITE_8152)) {
	148	if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
	149	return IT8152_AUDIO_INT;
	150	if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
	151	return IT8152_USB_INT;
	152	if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
	153	return IT8152_CDMA_INT;
	154	}
	155
	156	return 0;
	157	}
	158
	159	static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
	160	unsigned int devfn)
	161	{
	162	unsigned long addr = 0;
	163
	164	if (bus->number == 0) {
	165	if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
	166	addr = (devfn << 8);
	167	} else
	168	addr = (bus->number << 16) \| (devfn << 8);
	169
	170	return addr;
	171	}
	172
	173	static int it8152_pci_read_config(struct pci_bus *bus,
	174	unsigned int devfn, int where,
	175	int size, u32 *value)
	176	{
	177	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
	178	u32 v;
	179	int shift;
	180
	181	shift = (where & 3);
	182
	183	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
	184	v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift)));
	185
	186	*value = v;
	187
	188	return PCIBIOS_SUCCESSFUL;
	189	}
	190
	191	static int it8152_pci_write_config(struct pci_bus *bus,
	192	unsigned int devfn, int where,
	193	int size, u32 value)
	194	{
	195	unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
	196	u32 v, vtemp, mask = 0;
	197	int shift;
	198
	199	if (size == 1)
	200	mask = 0xff;
	201	if (size == 2)
202	mask = 0xffff;
203
204	shift = (where & 3);
205
206	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
207	vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
208
209	if (mask)
210	vtemp &= ~(mask << (8 * shift));
211	else
212	vtemp = 0;
213
214	v = (value << (8 * shift));
215	__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
216	__raw_writel((v \| vtemp), IT8152_PCI_CFG_DATA);
217
218	return PCIBIOS_SUCCESSFUL;
219	}
220
221	static struct pci_ops it8152_ops = {
222	.read = it8152_pci_read_config,
223	.write = it8152_pci_write_config,
224	};
225
226	static struct resource it8152_io = {
227	.name = "IT8152 PCI I/O region",
228	.flags = IORESOURCE_IO,
229	};
230
231	static struct resource it8152_mem = {
232	.name = "IT8152 PCI memory region",
233	.start = 0x10000000,
234	.end = 0x13e00000,
235	.flags = IORESOURCE_MEM,
236	};
237
238	/*
239	* The following functions are needed for DMA bouncing.
240	* ITE8152 chip can addrees up to 64MByte, so all the devices
241	* connected to ITE8152 (PCI and USB) should have limited DMA window
242	*/
243
244	/*
245	* Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
246	* other devices.
247	*/
248	static int it8152_pci_platform_notify(struct device *dev)
249	{
250	if (dev->bus == &pci_bus_type) {
251	if (dev->dma_mask)
252	*dev->dma_mask = (SZ_64M - 1) \| PHYS_OFFSET;
253	dev->coherent_dma_mask = (SZ_64M - 1) \| PHYS_OFFSET;
254	dmabounce_register_dev(dev, 2048, 4096);
255	}
256	return 0;
257	}
258
259	static int it8152_pci_platform_notify_remove(struct device *dev)
260	{
261	if (dev->bus == &pci_bus_type)
262	dmabounce_unregister_dev(dev);
263
264	return 0;
265	}
266
267	int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
268	{
269	dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
8e86f427	270	__func__, dma_addr, size);
a8fc0789 MR	271	return (dev->bus == &pci_bus_type) &&
	272	((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
	273	}
	274
a8fc0789 MR	275	int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
	276	{
	277	it8152_io.start = IT8152_IO_BASE + 0x12000;
	278	it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000;
	279
	280	sys->mem_offset = 0x10000000;
	281	sys->io_offset = IT8152_IO_BASE;
	282
	283	if (request_resource(&ioport_resource, &it8152_io)) {
	284	printk(KERN_ERR "PCI: unable to allocate IO region\n");
	285	goto err0;
	286	}
	287	if (request_resource(&iomem_resource, &it8152_mem)) {
	288	printk(KERN_ERR "PCI: unable to allocate memory region\n");
	289	goto err1;
	290	}
	291
	292	sys->resource[0] = &it8152_io;
	293	sys->resource[1] = &it8152_mem;
	294
	295	if (platform_notify \|\| platform_notify_remove) {
	296	printk(KERN_ERR "PCI: Can't use platform_notify\n");
	297	goto err2;
	298	}
	299
	300	platform_notify = it8152_pci_platform_notify;
	301	platform_notify_remove = it8152_pci_platform_notify_remove;
	302
	303	return 1;
	304
	305	err2:
	306	release_resource(&it8152_io);
	307	err1:
	308	release_resource(&it8152_mem);
	309	err0:
	310	return -EBUSY;
	311	}
	312
	313	/*
	314	* If we set up a device for bus mastering, we need to check the latency
	315	* timer as we don't have even crappy BIOSes to set it properly.
	316	* The implementation is from arch/i386/pci/i386.c
	317	*/
	318	unsigned int pcibios_max_latency = 255;
	319
	320	void pcibios_set_master(struct pci_dev *dev)
	321	{
	322	u8 lat;
	323
	324	/* no need to update on-chip OHCI controller */
	325	if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
	326	(dev->device == PCI_DEVICE_ID_ITE_8152) &&
	327	((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
	328	return;
	329
	330	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	331	if (lat < 16)
	332	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	333	else if (lat > pcibios_max_latency)
	334	lat = pcibios_max_latency;
	335	else
	336	return;
	337	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	338	pci_name(dev), lat);
339	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
340	}
341
342
343	struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
344	{
345	return pci_scan_bus(nr, &it8152_ops, sys);
346	}
347