[net-next-2.6.git] / arch / arm / common / gic.c

/*
 *  linux/arch/arm/common/gic.c
 *
 *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Interrupt architecture for the GIC:
 *
 * o There is one Interrupt Distributor, which receives interrupts
 *   from system devices and sends them to the Interrupt Controllers.
 *
 * o There is one CPU Interface per CPU, which sends interrupts sent
 *   by the Distributor, and interrupts generated locally, to the
 *   associated CPU. The base address of the CPU interface is usually
 *   aliased so that the same address points to different chips depending
 *   on the CPU it is accessed from.
 *
 * Note that IRQs 0-31 are special - they are local to each CPU.
 * As such, the enable set/clear, pending set/clear and active bit
 * registers are banked per-cpu for these sources.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/io.h>

#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>

static DEFINE_SPINLOCK(irq_controller_lock);

struct gic_chip_data {
	unsigned int irq_offset;
	void __iomem *dist_base;
	void __iomem *cpu_base;
};

#ifndef MAX_GIC_NR
#define MAX_GIC_NR	1
#endif

static struct gic_chip_data gic_data[MAX_GIC_NR];

static inline void __iomem *gic_dist_base(unsigned int irq)
{
	struct gic_chip_data *gic_data = get_irq_chip_data(irq);
	return gic_data->dist_base;
}

static inline void __iomem *gic_cpu_base(unsigned int irq)
{
	struct gic_chip_data *gic_data = get_irq_chip_data(irq);
	return gic_data->cpu_base;
}

static inline unsigned int gic_irq(unsigned int irq)
{
	struct gic_chip_data *gic_data = get_irq_chip_data(irq);
	return irq - gic_data->irq_offset;
}

/*
 * Routines to acknowledge, disable and enable interrupts
 */
static void gic_ack_irq(unsigned int irq)
{

	spin_lock(&irq_controller_lock);
	writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
	spin_unlock(&irq_controller_lock);
}

static void gic_mask_irq(unsigned int irq)
{
	u32 mask = 1 << (irq % 32);

	spin_lock(&irq_controller_lock);
	writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
	spin_unlock(&irq_controller_lock);
}

static void gic_unmask_irq(unsigned int irq)
{
	u32 mask = 1 << (irq % 32);

	spin_lock(&irq_controller_lock);
	writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
	spin_unlock(&irq_controller_lock);
}

static int gic_set_type(unsigned int irq, unsigned int type)
{
	void __iomem *base = gic_dist_base(irq);
	unsigned int gicirq = gic_irq(irq);
	u32 enablemask = 1 << (gicirq % 32);
	u32 enableoff = (gicirq / 32) * 4;
	u32 confmask = 0x2 << ((gicirq % 16) * 2);
	u32 confoff = (gicirq / 16) * 4;
	bool enabled = false;
	u32 val;

	/* Interrupt configuration for SGIs can't be changed */
	if (gicirq < 16)
		return -EINVAL;

	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
		return -EINVAL;

	spin_lock(&irq_controller_lock);

	val = readl(base + GIC_DIST_CONFIG + confoff);
	if (type == IRQ_TYPE_LEVEL_HIGH)
		val &= ~confmask;
	else if (type == IRQ_TYPE_EDGE_RISING)
		val |= confmask;

	/*
	 * As recommended by the spec, disable the interrupt before changing
	 * the configuration
	 */
	if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
		writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
		enabled = true;
	}

	writel(val, base + GIC_DIST_CONFIG + confoff);

	if (enabled)
		writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);

	spin_unlock(&irq_controller_lock);

	return 0;
}

#ifdef CONFIG_SMP
static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
{
	void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
	unsigned int shift = (irq % 4) * 8;
	unsigned int cpu = cpumask_first(mask_val);
	u32 val;

	spin_lock(&irq_controller_lock);
	irq_desc[irq].node = cpu;
	val = readl(reg) & ~(0xff << shift);
	val |= 1 << (cpu + shift);
	writel(val, reg);
	spin_unlock(&irq_controller_lock);

	return 0;
}
#endif

static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
	struct gic_chip_data *chip_data = get_irq_data(irq);
	struct irq_chip *chip = get_irq_chip(irq);
	unsigned int cascade_irq, gic_irq;
	unsigned long status;

	/* primary controller ack'ing */
	chip->ack(irq);

	spin_lock(&irq_controller_lock);
	status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
	spin_unlock(&irq_controller_lock);

	gic_irq = (status & 0x3ff);
	if (gic_irq == 1023)
		goto out;

	cascade_irq = gic_irq + chip_data->irq_offset;
	if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
		do_bad_IRQ(cascade_irq, desc);
	else
		generic_handle_irq(cascade_irq);

 out:
	/* primary controller unmasking */
	chip->unmask(irq);
}

static struct irq_chip gic_chip = {
	.name		= "GIC",
	.ack		= gic_ack_irq,
	.mask		= gic_mask_irq,
	.unmask		= gic_unmask_irq,
	.set_type	= gic_set_type,
#ifdef CONFIG_SMP
	.set_affinity	= gic_set_cpu,
#endif
};

void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
{
	if (gic_nr >= MAX_GIC_NR)
		BUG();
	if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
		BUG();
	set_irq_chained_handler(irq, gic_handle_cascade_irq);
}

void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
			  unsigned int irq_start)
{
	unsigned int max_irq, i;
	u32 cpumask = 1 << smp_processor_id();

	if (gic_nr >= MAX_GIC_NR)
		BUG();

	cpumask |= cpumask << 8;
	cpumask |= cpumask << 16;

	gic_data[gic_nr].dist_base = base;
	gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;

	writel(0, base + GIC_DIST_CTRL);

	/*
	 * Find out how many interrupts are supported.
	 */
	max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
	max_irq = (max_irq + 1) * 32;

	/*
	 * The GIC only supports up to 1020 interrupt sources.
	 * Limit this to either the architected maximum, or the
	 * platform maximum.
	 */
	if (max_irq > max(1020, NR_IRQS))
		max_irq = max(1020, NR_IRQS);

	/*
	 * Set all global interrupts to be level triggered, active low.
	 */
	for (i = 32; i < max_irq; i += 16)
		writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);

	/*
	 * Set all global interrupts to this CPU only.
	 */
	for (i = 32; i < max_irq; i += 4)
		writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);

	/*
	 * Set priority on all global interrupts.
	 */
	for (i = 32; i < max_irq; i += 4)
		writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);

	/*
	 * Disable all interrupts.  Leave the PPI and SGIs alone
	 * as these enables are banked registers.
	 */
	for (i = 32; i < max_irq; i += 32)
		writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);

	/*
	 * Setup the Linux IRQ subsystem.
	 */
	for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
		set_irq_chip(i, &gic_chip);
		set_irq_chip_data(i, &gic_data[gic_nr]);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}

	writel(1, base + GIC_DIST_CTRL);
}

void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
{
	void __iomem *dist_base;
	int i;

	if (gic_nr >= MAX_GIC_NR)
		BUG();

	dist_base = gic_data[gic_nr].dist_base;
	BUG_ON(!dist_base);

	gic_data[gic_nr].cpu_base = base;

	/*
	 * Deal with the banked PPI and SGI interrupts - disable all
	 * PPI interrupts, ensure all SGI interrupts are enabled.
	 */
	writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
	writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);

	/*
	 * Set priority on PPI and SGI interrupts
	 */
	for (i = 0; i < 32; i += 4)
		writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);

	writel(0xf0, base + GIC_CPU_PRIMASK);
	writel(1, base + GIC_CPU_CTRL);
}

#ifdef CONFIG_SMP
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
	unsigned long map = *cpus_addr(*mask);

	/* this always happens on GIC0 */
	writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
}
#endif
Commit	Line	Data
f27ecacc RK	1	/*
	2	* linux/arch/arm/common/gic.c
	3	*
	4	* Copyright (C) 2002 ARM Limited, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Interrupt architecture for the GIC:
	11	*
	12	* o There is one Interrupt Distributor, which receives interrupts
	13	* from system devices and sends them to the Interrupt Controllers.
	14	*
	15	* o There is one CPU Interface per CPU, which sends interrupts sent
	16	* by the Distributor, and interrupts generated locally, to the
b3a1bde4 CM	17	* associated CPU. The base address of the CPU interface is usually
	18	* aliased so that the same address points to different chips depending
	19	* on the CPU it is accessed from.
f27ecacc RK	20	*
	21	* Note that IRQs 0-31 are special - they are local to each CPU.
	22	* As such, the enable set/clear, pending set/clear and active bit
	23	* registers are banked per-cpu for these sources.
	24	*/
	25	#include <linux/init.h>
	26	#include <linux/kernel.h>
	27	#include <linux/list.h>
	28	#include <linux/smp.h>
dcb86e8c	29	#include <linux/cpumask.h>
fced80c7	30	#include <linux/io.h>
f27ecacc RK	31
f27ecacc RK	32	#include <asm/irq.h>
f27ecacc RK	33	#include <asm/mach/irq.h>
	34	#include <asm/hardware/gic.h>
	35
c4bfa28a	36	static DEFINE_SPINLOCK(irq_controller_lock);
f27ecacc	37
b3a1bde4 CM	38	struct gic_chip_data {
	39	unsigned int irq_offset;
	40	void __iomem *dist_base;
	41	void __iomem *cpu_base;
	42	};
	43
	44	#ifndef MAX_GIC_NR
	45	#define MAX_GIC_NR 1
	46	#endif
	47
	48	static struct gic_chip_data gic_data[MAX_GIC_NR];
	49
	50	static inline void __iomem *gic_dist_base(unsigned int irq)
	51	{
	52	struct gic_chip_data *gic_data = get_irq_chip_data(irq);
	53	return gic_data->dist_base;
	54	}
	55
	56	static inline void __iomem *gic_cpu_base(unsigned int irq)
	57	{
	58	struct gic_chip_data *gic_data = get_irq_chip_data(irq);
	59	return gic_data->cpu_base;
	60	}
	61
	62	static inline unsigned int gic_irq(unsigned int irq)
	63	{
	64	struct gic_chip_data *gic_data = get_irq_chip_data(irq);
	65	return irq - gic_data->irq_offset;
	66	}
	67
f27ecacc RK	68	/*
f27ecacc RK	69	* Routines to acknowledge, disable and enable interrupts
f27ecacc RK	70	*/
	71	static void gic_ack_irq(unsigned int irq)
	72	{
c4bfa28a TG	73
c4bfa28a TG	74	spin_lock(&irq_controller_lock);
b3a1bde4	75	writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
c4bfa28a	76	spin_unlock(&irq_controller_lock);
f27ecacc RK	77	}
	78
	79	static void gic_mask_irq(unsigned int irq)
	80	{
	81	u32 mask = 1 << (irq % 32);
c4bfa28a TG	82
c4bfa28a TG	83	spin_lock(&irq_controller_lock);
b3a1bde4	84	writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
c4bfa28a	85	spin_unlock(&irq_controller_lock);
f27ecacc RK	86	}
	87
	88	static void gic_unmask_irq(unsigned int irq)
	89	{
	90	u32 mask = 1 << (irq % 32);
c4bfa28a TG	91
c4bfa28a TG	92	spin_lock(&irq_controller_lock);
b3a1bde4	93	writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
c4bfa28a	94	spin_unlock(&irq_controller_lock);
f27ecacc RK	95	}
f27ecacc RK	96
5c0c1f08 RV	97	static int gic_set_type(unsigned int irq, unsigned int type)
	98	{
	99	void __iomem *base = gic_dist_base(irq);
	100	unsigned int gicirq = gic_irq(irq);
	101	u32 enablemask = 1 << (gicirq % 32);
	102	u32 enableoff = (gicirq / 32) * 4;
	103	u32 confmask = 0x2 << ((gicirq % 16) * 2);
	104	u32 confoff = (gicirq / 16) * 4;
	105	bool enabled = false;
	106	u32 val;
	107
	108	/* Interrupt configuration for SGIs can't be changed */
	109	if (gicirq < 16)
	110	return -EINVAL;
	111
	112	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
	113	return -EINVAL;
	114
	115	spin_lock(&irq_controller_lock);
	116
	117	val = readl(base + GIC_DIST_CONFIG + confoff);
	118	if (type == IRQ_TYPE_LEVEL_HIGH)
	119	val &= ~confmask;
	120	else if (type == IRQ_TYPE_EDGE_RISING)
	121	val \|= confmask;
	122
	123	/*
	124	* As recommended by the spec, disable the interrupt before changing
	125	* the configuration
	126	*/
	127	if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
	128	writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
	129	enabled = true;
	130	}
	131
	132	writel(val, base + GIC_DIST_CONFIG + confoff);
	133
	134	if (enabled)
	135	writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
	136
	137	spin_unlock(&irq_controller_lock);
	138
	139	return 0;
	140	}
	141
a06f5466	142	#ifdef CONFIG_SMP
d5dedd45	143	static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
f27ecacc	144	{
b3a1bde4	145	void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
f27ecacc	146	unsigned int shift = (irq % 4) * 8;
0de26520	147	unsigned int cpu = cpumask_first(mask_val);
f27ecacc RK	148	u32 val;
f27ecacc RK	149
c4bfa28a	150	spin_lock(&irq_controller_lock);
41184f6a	151	irq_desc[irq].node = cpu;
f27ecacc RK	152	val = readl(reg) & ~(0xff << shift);
	153	val \|= 1 << (cpu + shift);
	154	writel(val, reg);
c4bfa28a	155	spin_unlock(&irq_controller_lock);
d5dedd45 YL	156
d5dedd45 YL	157	return 0;
f27ecacc	158	}
a06f5466	159	#endif
f27ecacc	160
0f347bb9	161	static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
b3a1bde4 CM	162	{
	163	struct gic_chip_data *chip_data = get_irq_data(irq);
	164	struct irq_chip *chip = get_irq_chip(irq);
0f347bb9	165	unsigned int cascade_irq, gic_irq;
b3a1bde4 CM	166	unsigned long status;
	167
	168	/* primary controller ack'ing */
	169	chip->ack(irq);
	170
	171	spin_lock(&irq_controller_lock);
	172	status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
	173	spin_unlock(&irq_controller_lock);
	174
0f347bb9 RK	175	gic_irq = (status & 0x3ff);
0f347bb9 RK	176	if (gic_irq == 1023)
b3a1bde4	177	goto out;
b3a1bde4	178
0f347bb9 RK	179	cascade_irq = gic_irq + chip_data->irq_offset;
	180	if (unlikely(gic_irq < 32 \|\| gic_irq > 1020 \|\| cascade_irq >= NR_IRQS))
	181	do_bad_IRQ(cascade_irq, desc);
	182	else
	183	generic_handle_irq(cascade_irq);
b3a1bde4 CM	184
	185	out:
	186	/* primary controller unmasking */
	187	chip->unmask(irq);
	188	}
	189
38c677cb DB	190	static struct irq_chip gic_chip = {
38c677cb DB	191	.name = "GIC",
f27ecacc RK	192	.ack = gic_ack_irq,
	193	.mask = gic_mask_irq,
	194	.unmask = gic_unmask_irq,
5c0c1f08	195	.set_type = gic_set_type,
f27ecacc	196	#ifdef CONFIG_SMP
c4bfa28a	197	.set_affinity = gic_set_cpu,
f27ecacc RK	198	#endif
	199	};
	200
b3a1bde4 CM	201	void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
	202	{
	203	if (gic_nr >= MAX_GIC_NR)
	204	BUG();
	205	if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
	206	BUG();
	207	set_irq_chained_handler(irq, gic_handle_cascade_irq);
	208	}
	209
	210	void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
	211	unsigned int irq_start)
f27ecacc RK	212	{
	213	unsigned int max_irq, i;
	214	u32 cpumask = 1 << smp_processor_id();
	215
b3a1bde4 CM	216	if (gic_nr >= MAX_GIC_NR)
	217	BUG();
	218
f27ecacc RK	219	cpumask \|= cpumask << 8;
	220	cpumask \|= cpumask << 16;
	221
b3a1bde4 CM	222	gic_data[gic_nr].dist_base = base;
b3a1bde4 CM	223	gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
f27ecacc RK	224
	225	writel(0, base + GIC_DIST_CTRL);
	226
	227	/*
	228	* Find out how many interrupts are supported.
	229	*/
	230	max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
	231	max_irq = (max_irq + 1) * 32;
	232
	233	/*
	234	* The GIC only supports up to 1020 interrupt sources.
	235	* Limit this to either the architected maximum, or the
	236	* platform maximum.
	237	*/
	238	if (max_irq > max(1020, NR_IRQS))
	239	max_irq = max(1020, NR_IRQS);
	240
	241	/*
	242	* Set all global interrupts to be level triggered, active low.
	243	*/
	244	for (i = 32; i < max_irq; i += 16)
	245	writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
	246
	247	/*
	248	* Set all global interrupts to this CPU only.
	249	*/
	250	for (i = 32; i < max_irq; i += 4)
	251	writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
	252
	253	/*
9395f6ea	254	* Set priority on all global interrupts.
f27ecacc	255	*/
9395f6ea	256	for (i = 32; i < max_irq; i += 4)
f27ecacc RK	257	writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
	258
	259	/*
9395f6ea RK	260	* Disable all interrupts. Leave the PPI and SGIs alone
9395f6ea RK	261	* as these enables are banked registers.
f27ecacc	262	*/
9395f6ea	263	for (i = 32; i < max_irq; i += 32)
f27ecacc RK	264	writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
	265
	266	/*
	267	* Setup the Linux IRQ subsystem.
	268	*/
b3a1bde4	269	for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
f27ecacc	270	set_irq_chip(i, &gic_chip);
b3a1bde4	271	set_irq_chip_data(i, &gic_data[gic_nr]);
10dd5ce2	272	set_irq_handler(i, handle_level_irq);
f27ecacc RK	273	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
	274	}
	275
	276	writel(1, base + GIC_DIST_CTRL);
	277	}
	278
b3a1bde4	279	void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
f27ecacc	280	{
9395f6ea RK	281	void __iomem *dist_base;
	282	int i;
	283
b3a1bde4 CM	284	if (gic_nr >= MAX_GIC_NR)
	285	BUG();
	286
9395f6ea RK	287	dist_base = gic_data[gic_nr].dist_base;
	288	BUG_ON(!dist_base);
	289
b3a1bde4 CM	290	gic_data[gic_nr].cpu_base = base;
b3a1bde4 CM	291
9395f6ea RK	292	/*
	293	* Deal with the banked PPI and SGI interrupts - disable all
	294	* PPI interrupts, ensure all SGI interrupts are enabled.
	295	*/
	296	writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
	297	writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
	298
	299	/*
	300	* Set priority on PPI and SGI interrupts
	301	*/
	302	for (i = 0; i < 32; i += 4)
	303	writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
	304
f27ecacc RK	305	writel(0xf0, base + GIC_CPU_PRIMASK);
	306	writel(1, base + GIC_CPU_CTRL);
	307	}
	308
	309	#ifdef CONFIG_SMP
82668104	310	void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
f27ecacc	311	{
82668104	312	unsigned long map = cpus_addr(mask);
f27ecacc	313
b3a1bde4 CM	314	/* this always happens on GIC0 */
b3a1bde4 CM	315	writel(map << 16 \| irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
f27ecacc RK	316	}
f27ecacc RK	317	#endif