amd64_edac: Remove polling mechanism

[net-next-2.6.git] / drivers / edac / edac_mce_amd.c

diff --git a/drivers/edac/edac_mce_amd.c b/drivers/edac/edac_mce_amd.c
index 97e64bcdbc061c3b593ee757bd66a6999afb4761..bae9351e9473872214d6bd9870776a2c48680909 100644 (file)
--- a/drivers/edac/edac_mce_amd.c
+++ b/drivers/edac/edac_mce_amd.c
@@ -133,7 +133,7 @@ static void amd_decode_dc_mce(u64 mc0_status)
        u32 ec  = mc0_status & 0xffff;
        u32 xec = (mc0_status >> 16) & 0xf;
 
-       pr_emerg(" Data Cache Error");
+       pr_emerg("Data Cache Error");
 
        if (xec == 1 && TLB_ERROR(ec))
                pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
@@ -176,7 +176,7 @@ static void amd_decode_ic_mce(u64 mc1_status)
        u32 ec  = mc1_status & 0xffff;
        u32 xec = (mc1_status >> 16) & 0xf;
 
-       pr_emerg(" Instruction Cache Error");
+       pr_emerg("Instruction Cache Error");
 
        if (xec == 1 && TLB_ERROR(ec))
                pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
@@ -233,7 +233,7 @@ static void amd_decode_bu_mce(u64 mc2_status)
        u32 ec = mc2_status & 0xffff;
        u32 xec = (mc2_status >> 16) & 0xf;
 
-       pr_emerg(" Bus Unit Error");
+       pr_emerg("Bus Unit Error");
 
        if (xec == 0x1)
                pr_cont(" in the write data buffers.\n");
@@ -275,7 +275,7 @@ static void amd_decode_ls_mce(u64 mc3_status)
        u32 ec  = mc3_status & 0xffff;
        u32 xec = (mc3_status >> 16) & 0xf;
 
-       pr_emerg(" Load Store Error");
+       pr_emerg("Load Store Error");
 
        if (xec == 0x0) {
                u8 rrrr = (ec >> 4) & 0xf;
@@ -304,7 +304,7 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
        if (TLB_ERROR(ec) && !report_gart_errors)
                return;
 
-       pr_emerg(" Northbridge Error, node %d", node_id);
+       pr_emerg("Northbridge Error, node %d", node_id);
 
        /*
         * F10h, revD can disable ErrCpu[3:0] so check that first and also the
@@ -342,13 +342,13 @@ static void amd_decode_fr_mce(u64 mc5_status)
 static inline void amd_decode_err_code(unsigned int ec)
 {
        if (TLB_ERROR(ec)) {
-               pr_emerg(" Transaction: %s, Cache Level %s\n",
+               pr_emerg("Transaction: %s, Cache Level %s\n",
                         TT_MSG(ec), LL_MSG(ec));
        } else if (MEM_ERROR(ec)) {
-               pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s",
+               pr_emerg("Transaction: %s, Type: %s, Cache Level: %s",
                         RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
        } else if (BUS_ERROR(ec)) {
-               pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, "
+               pr_emerg("Transaction type: %s(%s), %s, Cache Level: %s, "
                         "Participating Processor: %s\n",
                          RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
                          PP_MSG(ec));